CN118486337A - Memory device and wraparound reading method of memory device - Google Patents
Memory device and wraparound reading method of memory device Download PDFInfo
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- CN118486337A CN118486337A CN202310106454.6A CN202310106454A CN118486337A CN 118486337 A CN118486337 A CN 118486337A CN 202310106454 A CN202310106454 A CN 202310106454A CN 118486337 A CN118486337 A CN 118486337A
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- 230000003139 buffering effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
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- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
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Abstract
本发明提供一种内存装置及内存装置的环绕读取方法，所述内存装置，包括内存单元阵列、信号产生电路、字线解码器、位线解码器、感测放大器电路以及缓存器电路。信号产生电路根据环绕读取命令产生控制信号。字线解码器、位线解码器及感测放大器电路根据环绕读取命令对内存单元阵列所存储的数据进行第一次的读取，以输出第一笔环绕读取数据。缓存器电路缓存第一笔环绕读取数据，并在第一笔环绕读取数据被输出后，根据控制信号与所缓存的第一笔环绕读取数据输出后续的环绕读取数据。在缓存器电路输出后续的环绕读取数据的期间，字线解码器、位线解码器及感测放大器电路根据控制信号而被失能。
The present invention provides a memory device and a wraparound read method for the memory device, wherein the memory device comprises a memory cell array, a signal generating circuit, a word line decoder, a bit line decoder, a sense amplifier circuit and a buffer circuit. The signal generating circuit generates a control signal according to a wraparound read command. The word line decoder, the bit line decoder and the sense amplifier circuit perform a first read of the data stored in the memory cell array according to the wraparound read command to output a first wraparound read data. The buffer circuit caches the first wraparound read data, and after the first wraparound read data is output, outputs subsequent wraparound read data according to the control signal and the cached first wraparound read data. During the period when the buffer circuit outputs subsequent wraparound read data, the word line decoder, the bit line decoder and the sense amplifier circuit are disabled according to the control signal.
Description
Technical Field
The present invention relates to a memory device and a reading method thereof, and more particularly, to a flash memory with a wrap-around reading function and a reading method thereof.
Background
When a wrap around read (wrap around read) function of the flash memory is enabled, the read of data may be limited to one unit byte of a page. The wrap-around read function allows multiple applications using the cache to quickly acquire key addresses and then fill the cache with fixed length data without issuing multiple read commands. Specifically, reading starts from the start address specified by the surround read command, and once the end address of the unit byte is reached, the output of the data automatically wraps around to the start address for reading until the chip select signal cs# is pulled high to terminate the surround read command. However, during the surrounding read operation of the conventional flash memory, the word line and bit line switches are kept on, and the sense amplifier is continuously operated, so that the power consumption of the flash memory is relatively high during the surrounding read operation.
Disclosure of Invention
The invention provides a memory device and a surrounding reading method thereof, which can reduce power consumption when performing surrounding reading operation.
The memory device of the present invention includes a memory cell array, a signal generating circuit, a word line decoder, a bit line decoder, a sense amplifier circuit, and a buffer circuit. The memory cell array is configured to store data. The signal generating circuit is configured to generate a control signal according to the surround read command. The word line decoder is coupled to the memory cell array and configured to receive the control signal. The bit line decoder is coupled to the memory cell array and configured to receive the control signal. The sense amplifier circuit is coupled to the bit line decoder and configured to receive a control signal. The buffer circuit is coupled to the sense amplifier circuit and configured to receive the control signal. The word line decoder, bit line decoder and sense amplifier circuit are configured to read data stored in the memory cell array for a first time according to a surround read command to output first surround read data. The buffer circuit is configured to buffer the first surrounding read data, and output subsequent surrounding read data according to the control signal and the buffered first surrounding read data after the first surrounding read data is output. During the period when the buffer circuit outputs the subsequent surrounding read data, the word line decoder, bit line decoder and sense amplifier circuit are disabled according to the control signal.
The method for reading the memory device in a surrounding way comprises the following steps: according to the surround reading command, the word line decoder, the bit line decoder and the sense amplifier circuit are enabled to read the data stored in the memory cell array for the first time so as to output first surround reading data; generating a control signal according to the wrap-around read command; buffering the first pen surrounding read data by a buffer circuit; after the first round reading data is output, enabling the buffer circuit to output subsequent round reading data according to the control signal and the buffered first round reading data; and disabling the word line decoder, the bit line decoder, and the sense amplifier circuit in response to the control signal during a period in which the buffer circuit outputs subsequent surrounding read data.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention;
FIG. 2 is a schematic diagram of the memory cell and bit line switches of the embodiment of FIG. 1;
FIG. 3 is a schematic diagram illustrating a surround read operation according to an embodiment of the present invention;
FIG. 4 is a schematic diagram showing a signal generating circuit according to an embodiment of the invention;
fig. 5 shows a waveform diagram of an operation signal of the signal generating circuit of the embodiment of fig. 4;
FIG. 6 is a schematic diagram of a buffer circuit according to an embodiment of the invention;
FIG. 7 is a schematic diagram of a buffer circuit according to another embodiment of the present invention;
FIG. 8 is a flowchart illustrating steps of a wrap-around method according to an embodiment of the invention.
Detailed Description
Referring to fig. 1 and 2, the memory device 100 includes a memory cell array 110, a word line decoder 120, a bit line decoder 130, a sense amplifier circuit 140, and a register circuit 150. The memory cell array 110 includes a plurality of memory cells 200 for storing data. For clarity, fig. 1 shows only one memory cell 200 as an illustration, and memory device 100 is, for example, NOR flash memory, but the invention is not limited thereto. Memory device 100 may be any semiconductor memory that may perform a wraparound read operation.
Word line decoder 120 is coupled to memory cells 200 through word lines WL. Memory cell 200 is coupled to bit line switch MN0 through bit line BL. The bit line BL is coupled to the sense amplifier circuit 140 through bit line switch MN0. When the bit line switch MN0 is turned on, the bit line BL supplies data stored in the memory cell 200 to the sense amplifier circuit 140. The source line SL of memory cell 200 is coupled to system low voltage VSS. The register circuit 150 is coupled to the sense amplifier circuit 140.
In the present embodiment, according to the surround read command 0Ch, the word line decoder 120, the bit line decoder 130, and the sense amplifier circuit 140 are enabled to read data stored in a specified unit byte of the memory cell array 110 (hereinafter referred to as surround read data) for the first time and output the first surround read data. The buffer circuit 150 is configured to buffer the first pen wrap read data. Specifically, after the first read of the surrounding read data is completed, the control signal C0CLK9 will be switched to a first level (e.g., high) to disable the word line decoder 120, the bit line decoder 130 and the sense amplifier circuit 140. The register circuit 150 is configured to output subsequent wrap-around read data according to the first level control signal C0CLK9 and the buffered first wrap-around read data until the wrap-around read command is terminated.
Specifically, the memory cell 200 starts the surround read operation according to the surround read command 0 Ch. During the first read around read operation, the word line decoder 120 turns on the memory cell 200 through the word line WL to select the memory cell 200. Next, the bit line decoder 130 turns on the bit line switch MN0 by the address signal Y. When the bit line switch MN0 is turned on, the bit line BL supplies the data stored in the selected memory cell 200 to the sense amplifier circuit 140. Then, the sense amplifier circuit 140 performs a sensing operation and outputs the first wrap-around read data to the data line DL and the buffer circuit 150. The buffer circuit 150 is configured to receive and buffer the first wrap-around read data. After the first reading of the surrounding read data is completed (i.e. the first surrounding read data is outputted to the output terminal OUT through the data line DL), the control signal C0CLK9 is switched to the first level (e.g. high level) to deactivate the word line decoder 120, the bit line decoder 130 and the sense amplifier circuit 140. The register circuit 150 is configured to repeatedly output subsequent surrounding read data according to the control signal C0CLK9 of the first level and the buffered first surrounding read data until the chip select signal CS# is pulled high to terminate the surrounding read command.
In the present embodiment, the control signal C0CLK9 is switched back to the second level (e.g., low level) when the wrap-around read operation is ended.
In this embodiment, the word line decoder 120, the bit line decoder 130 and the sense amplifier circuit 140 may be hardware circuits designed and implemented based on circuit design methods well known to those skilled in the art. Unlike the prior art, the word line decoder 120, the bit line decoder 130 and the sense amplifier circuit 140 of the present embodiment have a disable circuit configured to receive the control signal C0CLK9, for example, a transistor switch configured to disable the word line decoder 120, the bit line decoder 130 and the sense amplifier circuit 140 according to the control signal C0CLK9 of the first level, so as to reduce the power consumption during the surrounding read operation.
In other words, in the present embodiment, in the surround read operation, only the first surround read data is output from the sense amplifier circuit 140, and the subsequent surround read data is output from the buffer circuit 150. Thus, during most of the wraparound read operation, the word line decoder 120, bit line decoder 130, and sense amplifier circuit 140 may be disabled to reduce power consumption when the wraparound read operation is performed.
Referring to fig. 2 and 3, in fig. 3, 4 data are simultaneously output at a time and have a fixed length n, and 4n data are output in a surrounding manner, but the invention is not limited thereto. In the present embodiment, in the surround read operation, only the first surround read data (e.g., data D0 to D3, i.e., data corresponding to the start address) is outputted from the sense amplifier circuits 140_0, 140_1, 140_2, 140_3, and the subsequent surround read data (e.g., data D4 to Dn-1) is outputted from the buffer circuit. For example, the second pen surrounding read data (e.g., data D4-D7) is output from the buffer circuits 150_4, 150_5, 150_6, 150_7, and the nth pen surrounding read data (e.g., data D4 n-4-D4 n-1) is output from the buffer circuits 150_4n-4, 150_4n-3, 150_4n-2, 150_4n-1. Then, the start address is automatically wrapped back, the data D0 to D3 previously buffered in the register circuits are used as n+1th round read data, and output from the register circuits corresponding to the sense amplifier circuits 140_0, 140_1, 140_2, 140_3, then n+2th round read data (i.e. the buffered data D4 to D7) is output from the register circuits 150_4, 150_5, 150_6, 150_7, and so on, and then the 2 nd round read data (i.e. the buffered data D4n-4 to D4 n-1) is output from the register circuits 150_4n-4, 150_4n-3, 150_4n-2, 150_4n-1, and so on, so as to complete the round read operation, wherein n is a positive integer greater than 2. Thus, during most of the wraparound read operation, the word line decoder 120, bit line decoder 130, and sense amplifier circuit 140 may be disabled to reduce power consumption when the wraparound read operation is performed.
Referring to fig. 4 and 5, the memory device 100 may further include a signal generating circuit 300 for generating and outputting a control signal C0CLK9 to the word line decoder 120, the bit line decoder 130, the sense amplifier circuit 140 and the register circuit 150 according to the surround read command 0Ch, the clock signal CLK and the register circuit initial state setting signal PU to control the word line decoder 120, the bit line decoder 130, the sense amplifier circuit 140 and the register circuit 150 to perform the surround read operation on the memory cell array 110. The buffer circuit initial state setting signal PU is configured to set an initial state of the buffer circuit after power-on.
In fig. 4, the signal generating circuit 300 includes a first switch SW1, a second switch SW2, a first latch circuit 310, a third switch SW3, a fourth switch SW4 and a second latch circuit 320. The first terminal of the first switch SW1 is coupled to the first voltage VDD, the second terminal of the first switch SW1 is coupled to the first terminal of the second switch SW2 and the first terminal of the first latch circuit 310, and the control terminal of the first switch SW1 is coupled to the first clock CLK9. The first terminal of the second switch SW2 is coupled to the second terminal of the first switch SW1 and the first terminal of the first latch circuit 310, the second terminal of the second switch SW2 is coupled to the second voltage VSS, and the control terminal of the second switch SW2 is coupled to the second clock CLK0. A second terminal of the first latch circuit 310 is coupled to a first terminal of the third switch SW 3.
The second terminal of the third switch SW3 is coupled to the first terminal of the fourth switch SW4 and the first terminal of the second latch circuit 320, and the control terminal of the third switch SW3 is coupled to the inverted signal CLK9b of the first clock CLK 9. The first terminal of the fourth switch SW4 is coupled to the second terminal of the third switch SW3 and the first terminal of the second latch circuit 320, the second terminal of the fourth switch SW4 is coupled to the second voltage VSS, and the control terminal of the fourth switch is coupled to the register circuit initial state setting signal PU. A second terminal of the second latch circuit 320 serves as an output terminal of the signal generating circuit 300. The control signal C0CLK9 is output from the output terminal of the signal generating circuit 300.
Specifically, the first two frequencies (labeled 0, 1 in fig. 5) of the clock signal CLK correspond to the first read period surrounding the read command 0 Ch. The word line decoder 120, the bit line decoder 130, and the sense amplifier circuit 140 perform the first round read data read of the round read operation on the memory cell 200 during the first read according to the round read command 0 Ch. At this time, the signal generating circuit 300 outputs the second voltage VSS according to the high second clock CLK0, the high first clock CLK9b, and the low first clock CLK9, so that the control signal C0CLK9 is maintained at the low level. Accordingly, the signal generating circuit 300 outputs the control signal C0CLK9 of the low level.
In fig. 4, during the first reading period, the first switch SW1 is turned off by the first clock CLK9, and the third switch SW3 is turned on by the first clock inversion signal CLK9 b. That is, the first switch SW1 and the third switch SW3 are not turned on at the same time. At the same time, the second switch SW2 is turned on by the second clock CLK0, so that the second voltage VSS is transferred to the output terminal of the signal generating circuit 300 through the second switch SW2, the first latch circuit 310, the third switch SW3 and the second latch circuit 320 to generate the control signal C0CLK9 with a low level.
Next, the first clock CLK9 and the inverse signal CLK9b of the first clock are respectively switched to the high level and the low level at a ninth clock (denoted as 9 in fig. 5) of the clock signal CLK. The signal generating circuit 300 outputs the first voltage VCC according to the low-level second clock CLK0, the low-level first clock inversion signal CLK9b, and the high-level first clock CLK9, so that the control signal C0CLK9 is changed and maintained at the high level. Accordingly, the signal generating circuit 300 outputs the control signal C0CLK9 at a high level. When the word line decoder 120, the bit line decoder 130 and the sense amplifier circuit 140 receive the control signal C0CLK9 with a high level (first level), they will be disabled, and when the register circuit 150 receives the control signal C0CLK9 with a first level, they will output the subsequent surrounding read data.
In fig. 4, during the period when the buffer circuit 150 outputs the subsequent surrounding read data, the first switch SW1 is turned on by the first clock CLK9, and the third switch SW3 is turned off by the first clock inversion signal CLK9b, so that the first voltage VCC passes through the first switch SW1 and is then latched in the first latch circuit 310. Next, the first switch SW1 is turned off by the first clock CLK9, the third switch SW3 is turned on by the first clock CLK9b, and the first voltage VSS is transferred to the output terminal of the signal generating circuit 300 through the third switch SW3 and the second latch circuit 320 to generate the control signal C0CLK9 with the first level. In addition, during the period when the buffer circuit 150 outputs the subsequent surrounding read data, the second switch SW2 is turned off by the second clock CLK0, and the fourth switch SW4 is turned off by the buffer circuit initial state setting signal PU.
On the other hand, the buffer circuit initial state setting signal PU is configured to set the initial state of the signal generating circuit 300 after power-on, and set the initial state of the control signal C0CLK9 to the second level.
In the present embodiment, the first two frequencies of the clock signal CLK correspond to the first reading period of the surround read command 0Ch for illustration only and are not intended to limit the present invention. The first clock CLK9 and the inverted signal CLK9b of the first clock are respectively switched to the high level and the low level at the ninth clock of the clock signal CLK, which are only for illustration and not for limitation of the present invention.
Referring to fig. 6, the register circuit 550 according to an embodiment of the invention includes a first transistor MP1, a second transistor MP2, a third transistor MN2 and a fourth transistor MN3, which are sequentially connected in series between a system high voltage VCC (first voltage) and a system low voltage VSS (second voltage). The first transistor MP1 is controlled by the control signal C0CLK9. The second transistor MP2 and the third transistor MN2 are commonly controlled by the sense data output from the sense amplifier circuit 140. The fourth transistor MN3 is controlled by the inverted signal C0CLK9b of the control signal C0CLK9. The first inverter 551 and the second inverter 553 form a latch 552 configured to latch the first wrap around read data DO.
In the present embodiment, the control signal C0CLK9 with a high level controls the register circuit 550 to output the buffered first surrounding read data to the output terminal OUT, and the control signal C0CLK9 with a high level controls the word line decoder 120, the bit line decoder 130, and the sense amplifier circuit 140 to stop the read operation on the memory cell array 110, so as to reduce the power consumption of the memory device 100.
Referring to fig. 7, a register circuit 650 according to another embodiment of the invention includes a register 652, a switch circuit 654, and an output terminal OUT. The sense amplifier circuit 140 is coupled to the buffer 652 and the output terminal OUT through the switch circuit 654. The switch circuit 654 includes a first switch SW1 and a second switch SW2. In this embodiment, the buffer 652 may be a hardware circuit designed and implemented by a circuit design method well known to those skilled in the art.
The control signal C0CLK9 having a high level controls the first switch SW1 to couple the terminal N2 to the output terminal OUT, and the control signal C0CLK9 having a low level controls the first switch SW1 to couple the terminal N1 to the output terminal OUT. The control signal C0CLK9 having a high level controls the second switch SW2 to be non-conductive and the control signal C0CLK9 having a low level controls the second switch SW2 to be conductive. Therefore, the control signal C0CLK9 with a low level controls the switch circuit 654 to connect the sense amplifier circuit 140 with the buffer 652 and the output terminal OUT, so that the sense amplifier circuit 140 can buffer the first surrounding read data DO in the buffer 652 and output the first surrounding read data DO to the output terminal OUT. Thereafter, the control signal C0CLK9 having a high level controls the switch circuit 654 such that the sense amplifier circuit 140 is not connected to the register 652 and the output terminal OUT. At this time, the register 652 can output the subsequent surrounding read data to the output terminal OUT through the terminal N2 according to the first surrounding read data DO and the high level control signal C0CLK 9. In addition, the control signal C0CLK9 having a high level controls the word line decoder 120, the bit line decoder 130, and the sense amplifier circuit 140 to stop the read operation of the memory cell array 110, so as to reduce the power consumption of the memory device 100.
Referring to fig. 1 and 8, the surround reading method of the present embodiment is at least applicable to the memory device 100 of fig. 1, but the present invention is not limited thereto. As shown in fig. 8, in step S100, the word line decoder, the bit line decoder, and the sense amplifier circuit are caused to perform a first reading of data stored in the memory cell array according to a surround read command to output a first surround read data from the sense amplifier circuit. In one embodiment, the first read is configured to output data corresponding to the start address. In step S110, a control signal is generated according to the wrap-around read command. In step S120, the first pen surrounding read data is buffered by the buffer circuit. In detail, the first surrounding read data and the subsequent surrounding read data are buffered by the buffer circuit. In step S130, after the first surrounding read data is output, the buffer circuit outputs the subsequent surrounding read data according to the control signal and the buffered first surrounding read data. In step S140, the word line decoder, the bit line decoder, and the sense amplifier circuit are disabled according to the control signal while the buffer circuit outputs the subsequent surrounding read data.
In addition, the method for reading the memory device in the surrounding manner according to the embodiments of the present invention can be taught, suggested and implemented adequately in the descriptions of the embodiments of fig. 2 to 7.
In summary, in the embodiments of the present invention, the word line decoder, the bit line decoder and the sense amplifier circuit are disabled during the period when the register circuit outputs the subsequent surrounding read data according to the control signal generated by the surrounding read command, so that the memory device can reduce the power consumption during the surrounding read operation.
Various modifications and alterations to the disclosed embodiments may be made by those skilled in the art without departing from the scope or spirit of this disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations provided they come within the scope of the appended claims and their equivalents.
Claims (18)
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310106454.6A CN118486337A (en) | 2023-02-13 | 2023-02-13 | Memory device and wraparound reading method of memory device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310106454.6A CN118486337A (en) | 2023-02-13 | 2023-02-13 | Memory device and wraparound reading method of memory device |
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| CN118486337A true CN118486337A (en) | 2024-08-13 |
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| CN202310106454.6A Pending CN118486337A (en) | 2023-02-13 | 2023-02-13 | Memory device and wraparound reading method of memory device |
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