CN118539914A - Level shift circuit, chip and electronic equipment - Google Patents

Abstract

The present application relates to the field of integrated circuits, and discloses a level shifting circuit, a chip, and an electronic device. The level shifting circuit includes a first voltage domain unit and a second voltage domain unit; the first voltage domain unit is connected to the second voltage domain unit; the first voltage domain unit is used to send a first voltage signal to the second voltage domain unit, and the second voltage domain unit is used to receive the first voltage signal, and convert the first voltage signal into a second voltage signal and then output it, wherein the first voltage signal is a floating voltage signal, and the second voltage signal is a fixed low voltage signal. Through the above circuit, the level of the signal of the power detection part in the power management chip system of the switching type DCDC can be quickly converted to the control part, that is, the rapid conversion from the floating voltage domain to the fixed low voltage domain is realized, and the power consumption of the circuit is limited, and the logic errors caused by the floating power supply change can be prevented through multiple capacitors and resistors.

Description

Level shift circuit, chip and electronic device

Technical Field

The present application relates to the field of integrated circuits, and in particular to a level shifting circuit, a chip and an electronic device.

Background Art

In a switch-type DCDC (DC to DC) power management chip system, it is necessary to detect the signal of the power part and transmit it to the control part. The power part is usually in a floating voltage domain that changes with VIN, VOUT, and the switch state; while the core control and logic parts are usually in a fixed voltage domain, such as the common 1.8V, 3.3V, 5V, etc. Therefore, level conversion is required. For example, a level shifting circuit can be used to make pins with different voltages conform to their own voltage domains and can communicate normally.

The voltage domain includes a floating voltage domain and a fixed voltage domain. The floating voltage domain is a voltage domain where the floating ground and the floating power supply change rapidly over time, while the fixed voltage domain is a voltage domain that does not change over time. Currently, the level shift circuit can realize the conversion from a fixed voltage domain to a fixed voltage domain, but cannot realize the conversion from a floating voltage domain to a fixed low voltage domain.

Summary of the invention

Based on the above problems, the present application provides a level shifting circuit, a chip and an electronic device.

First, the present application mentions a level shifting circuit, which includes a first voltage domain unit and a second voltage domain unit; the first voltage domain unit is connected to the second voltage domain unit; the first voltage domain unit is used to send a first voltage signal to the second voltage domain unit, and the second voltage domain unit is used to receive the first voltage signal and convert the first voltage signal into a second voltage signal and then output it, wherein the first voltage signal is a floating voltage signal and the second voltage signal is a fixed low voltage signal.

Through the above circuit, a fast conversion from a floating voltage domain to a fixed low voltage domain can be achieved, and the power consumption of the circuit is limited. In addition, logic errors caused by floating power supply changes can be prevented through multiple capacitors and resistors.

In a possible implementation of the first aspect above, the first voltage domain unit includes a control module and a bias current providing module, wherein the control module is used to generate a current signal and send the current signal to the bias current providing module; the bias current providing module is used to generate a bias current according to the current signal, and convert the bias current into a first voltage signal and send it to the second voltage domain unit; the second voltage domain unit includes a current mirror module and a signal output module, wherein the current mirror module is used to convert the first voltage signal into a second voltage signal, and the signal output module is used to output the second voltage signal.

In a possible implementation of the first aspect above, the first voltage domain unit includes a control module and a bias current providing module, wherein the bias current providing module is used to generate a bias current and convert the bias current into a first voltage signal, and the control module is used to control whether the first voltage signal is sent to the second voltage domain unit; the second voltage domain unit includes a double-end to single-end module and a logic judgment output module, wherein the double-end to single-end module is used to convert the first voltage signal into a second voltage signal, and the logic judgment output module is used to output the second voltage signal.

In a possible implementation of the first aspect above, the control module includes a first field effect transistor, a second field effect transistor, a first inverter, and a second inverter; the gate of the first field effect transistor is connected to the output end of the first inverter and the input end of the second inverter, the input end of the first inverter is connected to the input signal, and the output end of the second inverter is connected to the gate of the second field effect transistor; the source of the first field effect transistor is connected to the source of the second field effect transistor; the drain of the first field effect transistor is connected to the second voltage domain unit; and the drain of the second field effect transistor is connected to the second voltage domain unit.

In a possible implementation of the first aspect above, the control module includes: a fifth resistor and a sixth resistor; the first end of the fifth resistor is connected to the second voltage domain unit; the second end of the fifth resistor is connected to the drain of the first field effect transistor; the first end of the sixth resistor is connected to the second voltage domain unit; and the second end of the sixth resistor is connected to the drain of the second field effect transistor.

In a possible implementation of the first aspect above, the first end of the fifth resistor is connected to the source of the first field effect transistor; the second end of the fifth resistor is connected to the first end of the sixth resistor; and the second end of the sixth resistor is connected to the source of the second field effect transistor.

In a possible implementation of the first aspect above, the bias current providing module includes a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a first capacitor, a second capacitor, a third capacitor, a sixth capacitor, a first resistor, a second resistor and a third resistor; the drain of the third field effect transistor is connected to the source of the first field effect transistor and the first end of the first capacitor; the source of the third field effect transistor is connected to the second end of the first capacitor, the first end of the second capacitor, and the source of the fourth field effect transistor; the gate of the third field effect transistor is connected to the gate of the fifth field effect transistor, the drain of the fifth field effect transistor, the gate of the fourth field effect transistor, the first end of the third capacitor and the first end of the first resistor end; the drain of the fourth field effect transistor is connected to the source of the second field effect transistor and the second end of the second capacitor; the source of the fourth field effect transistor is connected to the second end of the first capacitor, the first end of the second capacitor, and the source of the third field effect transistor; the gate of the fourth field effect transistor is connected to the gate of the fifth field effect transistor, the drain of the fifth field effect transistor, the first end of the third capacitor and the first end of the first resistor; the source of the fifth field effect transistor is connected to the second end of the third capacitor, the first end of the third resistor and the first end of the sixth capacitor, and the second end of the third resistor is connected to the floating power supply; the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the floating ground and the second end of the sixth capacitor.

In a possible implementation of the first aspect above, the current mirror module includes: a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, a fourth capacitor and a fifth capacitor; the signal output module includes: a third inverter, and a fourth resistor; the gate of the sixth field effect transistor is connected to the drain of the sixth field effect transistor, the drain of the first field effect transistor, the gate of the seventh field effect transistor, the first end of the fourth capacitor and the gate of the tenth field effect transistor; the source of the sixth field effect transistor is connected to the source of the tenth field effect transistor, the source of the seventh field effect transistor, the source of the eighth field effect transistor, the source of the ninth field effect transistor, the source of the eleventh field effect transistor, the second end of the fourth capacitor, the first end of the fifth capacitor, the first end of the fourth resistor and the input of the third inverter. output terminal; the drain of the seventh field effect transistor is connected to the drain of the second field effect transistor, the gate of the eighth field effect transistor, the gate of the ninth field effect transistor, the drain of the ninth field effect transistor, the second end of the fifth capacitor, and the gate of the eleventh field effect transistor; the drain of the eighth field effect transistor is connected to the drain of the first field effect transistor, the gate of the seventh field effect transistor, the gate of the sixth field effect transistor, the drain of the sixth field effect transistor, the first end of the fourth capacitor, and the gate of the tenth field effect transistor; the drain of the tenth field effect transistor is connected to the drain of the twelfth field effect transistor, the gate of the twelfth field effect transistor, and the gate of the thirteenth field effect transistor; the drain of the eleventh field effect transistor is connected to the drain of the thirteenth field effect transistor, the input terminal of the third inverter, and the second end of the fourth resistor; the source of the twelfth field effect transistor is connected to the source of the thirteenth field effect transistor, the output terminal of the third inverter and the output signal.

In a possible implementation of the first aspect above, when the input signal is at a high level, the output end of the first inverter is at a low level, the output end of the second inverter is at a high level, the second field effect transistor is turned on, the fourth field effect transistor is turned on, the eighth field effect transistor is turned on, the ninth field effect transistor is turned on, and the eleventh field effect transistor is turned on, and the input voltage of the third inverter is pulled up, and the output end of the third inverter outputs a low level; the first field effect transistor is turned off, and the third field effect transistor is turned off.

In a possible implementation of the first aspect above, when the input signal is at a low level, the output end of the first inverter is at a high level, the output end of the second inverter is at a low level, the first field effect transistor is turned on, the third field effect transistor is turned on, the sixth field effect transistor is turned on, the seventh field effect transistor is turned on, the tenth field effect transistor is turned on, the twelfth field effect transistor is turned on, and the thirteenth field effect transistor is turned on, and the input voltage of the third inverter is pulled down, the output end of the third inverter outputs a high level, the eighth field effect transistor is turned off, the twelfth field effect transistor is turned off, and the thirteenth field effect transistor is turned off.

In a second aspect, the present application provides a chip, comprising the above-mentioned first aspect and any possible level shifting circuit of the first aspect.

In a third aspect, the present application provides an electronic device, comprising the first aspect and any possible level shifting circuit of the first aspect and the chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 shows a functional schematic diagram of a level shift circuit according to some embodiments of the present application;

FIG2 shows a functional schematic diagram of a level shift circuit in a floating voltage domain according to some embodiments of the present application;

FIG3 shows a schematic diagram of the relationship between a floating power supply and a floating ground in a floating voltage domain according to some embodiments of the present application;

FIG4A shows a circuit signal diagram according to some embodiments of the present application;

FIG4B shows a module diagram of a level shift circuit according to some embodiments of the present application;

4C(a) and 4C(b) are schematic diagrams showing a level shifting circuit according to some embodiments of the present application;

5(a) and 5(b) are schematic diagrams showing another level shifting circuit according to some embodiments of the present application;

6( a ) and 6 ( b ) are schematic diagrams showing another level shifting circuit according to some embodiments of the present application.

DETAILED DESCRIPTION

The illustrative embodiments of the present application include but are not limited to a level shift circuit, a chip and an electronic device. The technical solution of the present application is introduced below in conjunction with the accompanying drawings.

As mentioned above, in the power management chip system of the switching type DCDC, the signal of the power detection part needs to be level-converted when it is transmitted to the control part. The level shift circuit can convert the logic signal in the integrated circuit from one voltage domain to another voltage domain. Specifically, the signal of the power detection part needs to be converted from the floating voltage domain to the fixed low voltage domain when it is transmitted to the control part.

FIG1 shows a functional schematic diagram of a level shift circuit. As shown in FIG1 , an input signal in a first voltage domain is converted into an output signal in a second voltage domain through the level shift circuit. The first voltage domain may be a fixed voltage domain, for example, the size may be 0-5V, and the second voltage domain may be a fixed voltage domain, for example, the size may be 5-10V.

The function of the level shift circuit under the floating voltage domain is introduced below in conjunction with Figure 2. Figure 2 shows a functional schematic diagram of a level shift circuit under a floating voltage domain. As shown in Figure 2, the input signal in the first voltage domain is converted into an output signal in the second voltage domain through the level shift circuit. Among them, the first voltage domain can be a floating voltage domain, for example, the size can be 4-30V. When the integrated circuit is working normally, the voltage of the floating ground in the floating voltage domain can be between -1V and 30V, and the floating power supply changes with the change of the floating ground; the second voltage domain can be a fixed low voltage domain, for example, the size can be 0-5V. Figure 3 shows a schematic diagram of the relationship between the floating power supply and the floating ground in a floating voltage domain. As shown in Figure 3, the horizontal axis represents time and the vertical axis represents voltage. The floating power supply (FLOAT_VDD) changes with the change of the floating ground (FLOAT_VSS). In some embodiments, the difference between the floating power supply and the floating ground can be maintained at about 5V.

As mentioned above, currently, the level shift circuit can realize the conversion from a fixed voltage domain to another fixed voltage domain, but cannot realize the conversion from a floating voltage domain to a fixed low voltage domain.

To this end, the present application provides a level shift circuit. Specifically, as shown in FIG4A , the first voltage domain unit is connected to the second voltage domain unit; the first voltage domain unit is used to send a first voltage signal to the second voltage domain unit, and the second voltage domain unit is used to receive the first voltage signal and convert the first voltage signal into a second voltage signal and then output it, wherein the first voltage signal is a floating voltage signal and the second voltage signal is a fixed low voltage signal. In this way, the level shift circuit mentioned in the present application can realize a fast conversion from a floating voltage domain to a fixed low voltage domain, and limit the power consumption of the circuit, and can prevent logic errors caused by changes in floating power supply through multiple capacitors and resistors.

The level shift circuit mentioned in the present application is introduced below in conjunction with FIG. 4B , FIG. 4C(a) and FIG. 4C(b).

Fig. 4B shows a module diagram of a level shift circuit. As shown in Fig. 4B, the level shift circuit includes a first voltage domain unit and a second voltage domain unit, wherein the first voltage domain unit is a floating voltage domain, and the second voltage domain unit is a fixed voltage domain.

In some embodiments, the first voltage domain unit includes a control module and a bias current providing module. The bias current providing module is used to generate a bias current and convert the bias current into a first voltage signal to be transmitted to the second voltage domain unit via the control module; the control module includes control 1 and control 2, and the communication between the first voltage domain unit and the second voltage domain unit is turned on or off by control 1 and control 2, thereby controlling whether the first voltage signal is sent to the second voltage domain unit. Exemplarily, control 1 and control 2 are NMOS tubes.

In some embodiments, the second voltage domain unit includes a double-end to single-end module and a logic judgment output module. The double-end to single-end module is used to convert two current signals sent by the first voltage domain unit into a voltage signal through multiple current mirrors to send to the logic judgment output module, such as converting the first voltage signal into a second voltage signal; the logic judgment output module is used to output a corresponding signal based on the high and low of the received voltage signal, such as outputting the second voltage signal.

4C(a) and 4C(b) show schematic diagrams of a level shift circuit. As shown in FIGS. 4C(a) and 4C(b), the level shift circuit includes a first voltage domain unit 10 and a second voltage domain unit 20.

The first voltage domain unit 10 (the dotted line portion in the figure) includes a control module and a bias current providing module. The control module is used to generate a current signal and send the current signal to the bias current providing module; the bias current providing module is used to generate a bias current according to the current signal, and convert the bias current into a first voltage signal and send it to the second voltage domain unit 20.

The second voltage domain unit 20 (the part not marked with dotted lines in the figure) includes a current mirror module (corresponding to an instance of a double-ended to single-ended module) and a signal output module (corresponding to an instance of a logic judgment output module); the current mirror module is used to convert the first voltage signal into a second voltage signal, and the signal output module is used to output the second voltage signal.

The control module includes: a first field effect transistor M1, a second field effect transistor M2, a first inverter X1, and a second inverter X2. The gate of the first field effect transistor M1 is connected to the output of the first inverter X1 and the input of the second inverter X2, the input of the first inverter X1 is connected to the input signal, and the output of the second inverter X2 is connected to the gate of the second field effect transistor M2; the source of the first field effect transistor M1 is connected to the source of the second field effect transistor M2; the drain of the first field effect transistor M1 is connected to the second voltage domain unit 20; and the drain of the second field effect transistor M2 is connected to the second voltage domain unit 20.

The bias current providing module includes a third field effect transistor M3, a fourth field effect transistor M4, a fifth field effect transistor M5, a first capacitor C1, a second capacitor C2, a third capacitor C3, a sixth capacitor C6, a first resistor R1, a second resistor R2 and a third resistor R3.

Among them, the drain of the third field effect transistor M3 is connected to the source of the first field effect transistor M1 and the first end of the first capacitor C1; the source of the third field effect transistor M3 is connected to the second end of the first capacitor C1, the first end of the second capacitor C2, and the source of the fourth field effect transistor M4; the gate of the third field effect transistor M3 (bias current VBIAS_LS input end) is connected to the gate of the fifth field effect transistor M5 (bias current VBIAS_LS output end), the gate of the fourth field effect transistor M4 (bias current VBIAS_LS input end), the drain of the fifth field effect transistor M5, the first end of the third capacitor C3 and the first end of the first resistor R1.

The drain of the fourth field effect transistor M4 is connected to the source of the second field effect transistor M2 and the second end of the second capacitor C2; the source of the fourth field effect transistor M4 is connected to the second end of the first capacitor C1, the first end of the second capacitor C2, and the source of the third field effect transistor M3; the gate of the fourth field effect transistor M4 is connected to the gate of the fifth field effect transistor M5, the drain of the fifth field effect transistor M5, the first end of the third capacitor C3 and the first end of the first resistor R1.

The source of the fifth field effect transistor M5 is connected to the second end of the third capacitor C3, the first end of the third resistor R3 and the first end of the sixth capacitor C6, the second end of the third resistor R3 is grounded and connected to the floating power supply end; the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the floating ground and the second end of the sixth capacitor C6.

Among them, the current mirror module includes: a sixth field effect transistor M6, a seventh field effect transistor M7, an eighth field effect transistor M8, a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, a twelfth field effect transistor M12, a thirteenth field effect transistor M13, a fourth capacitor C4, and a fifth capacitor C5; the signal output module includes: a third inverter X3 and a fourth resistor R4.

The gate of the sixth field effect transistor M6 is connected to the drain of the sixth field effect transistor M6 , the drain of the first field effect transistor M1 , the gate of the seventh field effect transistor M7 , the first end of the fourth capacitor C4 and the gate of the tenth field effect transistor M10 .

The source of the sixth field effect transistor M6 is connected to the source of the tenth field effect transistor M10, the source of the seventh field effect transistor M7, the source of the eighth field effect transistor M8, the source of the ninth field effect transistor M9, the source of the eleventh field effect transistor M11, the second end of the fourth capacitor C4, the first end of the fifth capacitor C5, the first end of the fourth resistor R4 and the output end of the third inverter X3.

The drain of the seventh field effect transistor M7 is connected to the drain of the second field effect transistor M2, the gate of the eighth field effect transistor M8, the gate of the ninth field effect transistor M9, the drain of the ninth field effect transistor M9, the second end of the fifth capacitor C5, and the gate of the eleventh field effect transistor M11.

The drain of the eighth field effect transistor M8 is connected to the drain of the first field effect transistor M1, the gate of the seventh field effect transistor M7, the gate of the sixth field effect transistor M6, the drain of the sixth field effect transistor M6, the first end of the fourth capacitor C4, and the gate of the tenth field effect transistor M10.

The drain of the tenth field effect transistor M10 is connected to the drain of the twelfth field effect transistor M12 , the gate of the twelfth field effect transistor M12 , and the gate of the thirteenth field effect transistor M13 .

The drain of the eleventh field effect transistor M11 is connected to the drain of the thirteenth field effect transistor M13 , the input end of the third inverter X3 , and the second end of the fourth resistor R4 .

The source of the twelfth field effect transistor M12 is connected to the source of the thirteenth field effect transistor M13, the output terminal of the third inverter X3 and the output signal.

As shown in Fig. 4C (a) and 4C (b), the inverter X1 and the inverter X2 are used to provide an inverted logic signal. For example, when the input terminal of the inverter X1 is at a high level, the output terminal of the inverter X1 is at a low level, that is, when the input terminal of the inverter X2 is at a low level, the output terminal of the inverter is at a high level. The third field effect transistor M3 and the fourth field effect transistor M4 are used to provide a current source and can limit the power consumption of the level shift circuit.

The first field effect transistor M1 and the second field effect transistor M2 are high voltage field effect transistors and are used to provide a path from the AB point to the ground (FLOAT_VSS).

The current mirror formed by the ninth field effect transistor M9, the eleventh field effect transistor M11, the sixth field effect transistor M6, the tenth field effect transistor M10, the twelfth field effect transistor M12 and the thirteenth field effect transistor M13 is used to convert the double-ended signal at point AB into a single-ended signal at point C.

The sixth field effect transistor M6 , the seventh field effect transistor M7 , the eighth field effect transistor M8 , and the ninth field effect transistor M9 are used to improve the sensitivity of the level shift circuit.

Since the first end of the fourth resistor R4 is connected to the input end of the third inverter X3 and the output end of the inverter X3 is connected to the output signal, ie, the logic signal of the floating voltage domain, the fourth resistor R4 can be used to set the initial state of the output signal to a low level.

When the first field effect transistor M1 and the second field effect transistor M2 are turned off, the seventh field effect transistor M7 and the eighth field effect transistor M8 are used to pull up the voltage at the AB point to prevent logic errors.

The fourth capacitor and the fifth capacitor are used to balance the capacitance from the AB point to the ground (FLOAT_VSS) to prevent logic errors when the ground changes drastically. The third resistor and the sixth capacitor are used to filter the floating power supply.

The third field effect transistor M3 , the fourth field effect transistor M4 , the fifth field effect transistor M5 , the first resistor R1 , the second resistor R2 , and the third capacitor are used to provide current bias.

The sixth field effect transistor M6 and the ninth field effect transistor M9 are used to clamp the AB point, that is, to limit the potential of the AB point to a specified potential, which is an overvoltage protection technology.

As shown in Figures 4C(a) and 4C(b), when the input signal is at a high level, the output end of the first inverter X1 is at a low level, the output end of the second inverter X2 is at a high level, the second field effect transistor M2 is turned on, the fourth field effect transistor M4 is turned on, the ninth field effect transistor M9 is turned on, and the eleventh field effect transistor M11 is turned on. Among them, the current mirror composed of the ninth field effect transistor M9 and the eleventh field effect transistor M11 pulls up the voltage at point C, that is, pulls up the input voltage of the third inverter X3. The first field effect transistor is cut off and cannot pull down the voltage at point A. Since the eighth field effect transistor M8 is turned on, the voltage at point A is pulled up. Since the gate-source voltage of the current mirror composed of the sixth field effect transistor M6, the tenth field effect transistor M10, the twelfth field effect transistor M12, and the thirteenth field effect transistor M13 is equal to 0, the voltage at point C cannot be pulled down. Therefore, in the floating voltage domain, gm11>gm13, that is, the pulling force of the eleventh field effect transistor M11 is greater than that of the thirteenth field effect transistor M13, the voltage at point C is high, and the output end of the inverter X3 is low, that is, the output signal is low. In some embodiments, the current of the field effect transistor can be determined according to the following formula (1):

ID＝K(VGS-VTH)VDS (1)

In formula (1), ID is the current of the field effect transistor, K is the coefficient in the level shift circuit, VGS is the gate-source voltage of the field effect transistor, VTH is the threshold voltage of the field effect transistor, and VDS is the drain-source voltage of the field effect transistor.

In some embodiments, the voltage at point C can be determined according to the following formula (2):

gm11＝K11(VGS11-VTP)>gm13＝K13(VGS13-VTN) (2)

In formula (2), VGS11 is the gate-source voltage of the eleventh field effect transistor M11, K11 is the coefficient of the eleventh field effect transistor M11, and VTP is the threshold voltage of the eleventh field effect transistor M11; VGS13 is the gate-source voltage of the thirteenth field effect transistor M13, K13 is the coefficient of the thirteenth field effect transistor M13, and VTN is the threshold voltage of the thirteenth field effect transistor M13.

When the input signal is at a low level, the output end of the first inverter X1 is at a high level, the output end of the second inverter X2 is at a low level, the first field effect transistor M1 is turned on, the third field effect transistor M3 is turned on, the sixth field effect transistor M6 is turned on, the seventh field effect transistor M7 is turned on, the tenth field effect transistor M10 is turned on, the twelfth field effect transistor M12 is turned on, and the thirteenth field effect transistor M13 is turned on. Among them, the current mirror composed of the sixth field effect transistor M6, the tenth field effect transistor M10, the twelfth field effect transistor M12, and the thirteenth field effect transistor M13 pulls down the voltage at point C. In addition, since the second field effect transistor M2 is turned off, the voltage at point B cannot be pulled down, and since the seventh field effect transistor M7 is turned on, the voltage at point B is pulled up. The gate-source voltage of the current mirror composed of the ninth field effect transistor M9 and the eleventh field effect transistor M11 is equal to 0, and the voltage at point C cannot be pulled up. Therefore, in the floating voltage domain, gm11<gm13, that is, the pulling force of the eleventh field effect transistor M11 is smaller than that of the thirteenth field effect transistor M13, the voltage at point C is low, and the output end of the inverter X3 is high, that is, the output signal is high.

In some embodiments, the voltage at point C can be determined according to the following formula (3):

gm11＝K11(VGS11-VTP)<gm13＝K13(VGS13-VTN) (3)

In formula (3), VGS11 is the gate-source voltage of the eleventh field effect transistor M11, K11 is the coefficient of the eleventh field effect transistor M11, and VTP is the threshold voltage of the eleventh field effect transistor M11; VGS13 is the gate-source voltage of the thirteenth field effect transistor M13, K13 is the coefficient of the thirteenth field effect transistor M13, and VTN is the threshold voltage of the thirteenth field effect transistor M13.

When the floating voltage domain changes rapidly, if the parasitic capacitance from the AB point to the ground (FLOAT_VSS) is too large, the gate-source voltage of the sixth field effect transistor M6 and the ninth field effect transistor M9 may increase, thereby causing a logic error. The fourth capacitor C4 and the fifth capacitor C5 can be used to reduce the parasitic capacitance. At the same time, the third resistor R3 and the sixth capacitor C6 are used to filter the floating power supply. According to formula (4), high-frequency noise greater than the frequency fc is attenuated.

In formula (4), R is the resistance of the third resistor R3, C is the capacitance of the sixth capacitor R6, and fc is the frequency.

When the power supply voltage (VDD1_5V), floating power supply (LOAT_VDD), floating ground (LOAT_VSS), and ground terminal (FLOAT_VSS) are not fully established and not fully released, in order to prevent the output logic signal from being unstable, the fourth resistor R4 pulls the voltage at point C to a high level, and the output signal OUT of the level shifting circuit is a low level. Among them, the fourth resistor R4 is a large resistor, so the impact on the power supply and ground level conversion is small enough, and the equivalent resistance of the eleventh field effect transistor M11 is as shown in the following formula (5).

R＝gm ^-1 =[K(VGS11-VTH)]^-1 (5)

In formula (5), VGS11 is the gate-source voltage of the eleventh field effect transistor M11, VTH is the gate voltage that occurs when a specified current flows between the source and the drain, K is a coefficient, and R is the equivalent resistance of the eleventh field effect transistor M11.

In the level shifting circuit mentioned in the present application, a high-gain amplifier with a current source load is used in the floating voltage domain to send the output signal to the fixed low voltage domain, and a current mirror is used in the fixed low voltage domain to convert the dual-ended output into a single-ended output, so that fast conversion from the floating voltage domain to the fixed low voltage domain can be achieved, and multiple capacitors and resistors are used to reduce the risk of logical errors and further improve the performance of the circuit.

Another level shift circuit proposed in the present application is described below in conjunction with FIGS. 5( a ) and 5 ( b ) and FIGS. 6 ( a ) and 6 ( b ).

Since the measure of limiting power consumption includes the method of connecting resistors in series in addition to fixing the bias current, the power consumption of the circuit can also be adjusted by adjusting the size of the fifth resistor R5 and the sixth resistor R6, wherein the resistance of the fifth resistor R5 and the sixth resistor R6 are the same. For example, FIG5(a) and FIG5(b) show a schematic diagram of a level shift circuit, as shown in FIG5(a) and FIG5(b), compared with the level shift circuit shown in FIG4C(a) and FIG4C(b), the structure of the operational amplifier has changed, and the tail current source is replaced by a series load resistor.

The first voltage domain (the dotted line portion in the figure) includes a first field effect transistor M1, a second field effect transistor M2, a first inverter X1, a second inverter X2, a third resistor R3, a fifth resistor R5, a sixth resistor R6 and a sixth capacitor C6. Among them, the gate of the first field effect transistor M1 is connected to the output end of the first inverter X1 and the input end of the second inverter X2, the input end of the second inverter X2 is also connected to the floating voltage (FLOAT_VDD) and the ground end, the input end of the first inverter X1 is connected to the input signal, the input end of the first inverter X1 is also connected to the floating voltage (FLOAT_VDD) and the ground end, the output end of the second inverter X2 is connected to the gate of the second field effect transistor M2; the source of the first field effect transistor M1 is connected to the source of the second field effect transistor M2; the drain of the first field effect transistor M1 is connected to the fifth resistor R5 The first end of the fifth resistor R5 is connected to the second voltage domain unit 20; the drain of the second field effect transistor M2 is connected to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is connected to the second voltage domain unit 20 (the dotted line part is not marked in the figure); the first end of the third resistor R3 is connected to the floating voltage (FLOAT_VDD), the second end of the third resistor R3 is connected to the floating voltage (FLOAT_VDD1) (that is, connected to the input end of the first inverter X1 and the input end of the second inverter X2) and the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is connected to the floating ground (FLOAT_VSS).

The structure and principle of the second voltage domain unit 20 are consistent with those of the level shift circuit in FIGS. 4C(a) and 4C(b), and are not described in detail here.

6(a) and 6(b) show schematic diagrams of another level shift circuit. As shown in FIG6(a) and 6(b), compared with the level shift circuit shown in FIG4C(a) and 4C(b), the structure of the operational amplifier has changed, and the tail current source has been replaced with a resistive negative feedback structure.

The first voltage domain (the dotted line portion in the figure) includes a first field effect transistor M1, a second field effect transistor M2, a first inverter X1, a second inverter X2, a third resistor R3, a fifth resistor R5, a sixth resistor R6 and a sixth capacitor C6. Among them, the gate of the first field effect transistor M1 is connected to the output end of the first inverter X1 and the input end of the second inverter X2, the input end of the second inverter X2 is also connected to the floating voltage (FLOAT_VDD) and the ground end, the input end of the first inverter X1 is connected to the input signal, the input end of the first inverter X1 is also connected to the floating voltage (FLOAT_VDD) and the ground end, the output end of the second inverter X2 is connected to the gate of the second field effect transistor M2; the source of the first field effect transistor M1 is connected to the first end of the fifth resistor R5, the second end of the fifth resistor is connected to the first end of the sixth resistor, and the sixth capacitor C6 ... The second end of the resistor is connected to the source of the second field effect transistor M2; the drain of the first field effect transistor M1 is connected to the second voltage domain unit 20; the drain of the second field effect transistor M2 is connected to the second voltage domain unit 20 (the dotted line part is not marked in the figure); the first end of the third resistor R3 is connected to the floating voltage (FLOAT_VDD), the second end of the third resistor R3 is connected to the floating voltage (FLOAT_VDD1) (that is, connected to the input end of the first inverter X1 and the input end of the second inverter X2) and the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is connected to the floating ground (FLOAT_VSS).

The structure and principle of the second voltage domain unit 20 are consistent with those of the level shift circuit in FIGS. 4C(a) and 4C(b), and are not described in detail here.

In the level shifting circuit mentioned in the present application, a high-gain amplifier with a current source load is used in the floating voltage domain to send the output signal to the fixed low voltage domain, and a current mirror is used in the fixed low voltage domain to convert the dual-ended output into a single-ended output, so that fast conversion from the floating voltage domain to the fixed low voltage domain can be achieved, and multiple capacitors and resistors are used to reduce the risk of logical errors and further improve the performance of the circuit.

The present application provides a chip, comprising the level shifting circuit mentioned in the present application.

The present application provides an electronic device, comprising the level shifting circuit mentioned in the present application or the chip mentioned in the present application.

In the accompanying drawings, some structural or method features may be shown in a specific arrangement and/or order. However, it should be understood that such a specific arrangement and/or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and/or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

It should be noted that the units/modules mentioned in the various device embodiments of the present application are all logical units/modules. Physically, a logical unit/module can be a physical unit/module, or a part of a physical unit/module, or can be implemented as a combination of multiple physical units/modules. The physical implementation method of these logical units/modules themselves is not the most important. The combination of functions implemented by these logical units/modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units/modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units/modules in the above-mentioned device embodiments.

It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application.

Claims (12)

1. A level shift circuit, characterized in that the level shift circuit comprises a first voltage domain unit and a second voltage domain unit; The first voltage domain unit is connected to the second voltage domain unit; The first voltage domain unit is used to send a first voltage signal to the second voltage domain unit, and the second voltage domain unit is used to receive the first voltage signal and convert the first voltage signal into a second voltage signal and then output it, wherein the first voltage signal is a floating voltage signal and the second voltage signal is a fixed low voltage signal. 2. The level shift circuit according to claim 1, characterized in that the first voltage domain unit comprises a control module and a bias current providing module, wherein the control module is used to generate a current signal and send the current signal to the bias current providing module, and the bias current providing module is used to generate a bias current according to the current signal, and convert the bias current into the first voltage signal and send it to the second voltage domain unit; The second voltage domain unit includes a current mirror module and a signal output module, wherein the current mirror module is used to convert the first voltage signal into the second voltage signal, and the signal output module is used to output the second voltage signal. 3. The level shift circuit according to claim 1, characterized in that the first voltage domain unit comprises a control module and a bias current providing module, wherein the bias current providing module is used to generate a bias current and convert the bias current into the first voltage signal, and the control module is used to control whether the first voltage signal is sent to the second voltage domain unit; The second voltage domain unit includes a double-end to single-end module and a logic judgment output module, wherein the double-end to single-end module is used to convert the first voltage signal into the second voltage signal, and the logic judgment output module is used to output the second voltage signal. 4. The level shift circuit according to claim 2 or 3, characterized in that the control module comprises a first field effect transistor, a second field effect transistor, a first inverter, and a second inverter; The gate of the first field effect transistor is connected to the output end of the first inverter and the input end of the second inverter, the input end of the first inverter is connected to an input signal, and the output end of the second inverter is connected to the gate of the second field effect transistor; The source of the first field effect transistor is connected to the source of the second field effect transistor; The drain of the first field effect transistor is connected to the second voltage domain unit; A drain of the second field effect transistor is connected to the second voltage domain unit. 5. The level shift circuit according to claim 4, characterized in that the control module comprises: a fifth resistor and a sixth resistor; A first end of the fifth resistor is connected to the second voltage domain unit; The second end of the fifth resistor is connected to the drain of the first field effect transistor; A first end of the sixth resistor is connected to the second voltage domain unit; The second end of the sixth resistor is connected to the drain of the second field effect transistor. 6. The level shift circuit according to claim 5, characterized in that: A first end of the fifth resistor is connected to a source of the first field effect transistor; The second end of the fifth resistor is connected to the first end of the sixth resistor; The second end of the sixth resistor is connected to the source of the second field effect transistor. 7. The level shift circuit according to claim 5 or 6, characterized in that the bias current providing module comprises a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a first capacitor, a second capacitor, a third capacitor, a sixth capacitor, a first resistor, a second resistor and a third resistor; The drain of the third field effect transistor is connected to the source of the first field effect transistor and the first end of the first capacitor; The source of the third field effect transistor is connected to the second end of the first capacitor, the first end of the second capacitor, and the source of the fourth field effect transistor; The gate of the third field effect transistor is connected to the gate of the fifth field effect transistor, the drain of the fifth field effect transistor, the gate of the fourth field effect transistor, the first end of the third capacitor and the first end of the first resistor; The drain of the fourth field effect transistor is connected to the source of the second field effect transistor and the second end of the second capacitor; The source of the fourth field effect transistor is connected to the second end of the first capacitor, the first end of the second capacitor, and the source of the third field effect transistor; The gate of the fourth field effect transistor is connected to the gate of the fifth field effect transistor, the drain of the fifth field effect transistor, the first end of the third capacitor and the first end of the first resistor; The source of the fifth field effect transistor is connected to the second end of the third capacitor, the first end of the third resistor and the first end of the sixth capacitor, and the second end of the third resistor is connected to the floating power supply; The second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the floating ground and the second end of the sixth capacitor. 8. The level shift circuit according to claim 7, characterized in that the current mirror module comprises: a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, a fourth capacitor and a fifth capacitor; the signal output module comprises: a third inverter, and a fourth resistor; The gate of the sixth field effect transistor is connected to the drain of the sixth field effect transistor, the drain of the first field effect transistor, the gate of the seventh field effect transistor, the first end of the fourth capacitor and the gate of the tenth field effect transistor; The source of the sixth field effect transistor is connected to the source of the tenth field effect transistor, the source of the seventh field effect transistor, the source of the eighth field effect transistor, the source of the ninth field effect transistor, the source of the eleventh field effect transistor, the second end of the fourth capacitor, the first end of the fifth capacitor, the first end of the fourth resistor and the output end of the third inverter; The drain of the seventh field effect transistor is connected to the drain of the second field effect transistor, the gate of the eighth field effect transistor, the gate of the ninth field effect transistor, the drain of the ninth field effect transistor, the second end of the fifth capacitor, and the gate of the eleventh field effect transistor; The drain of the eighth field effect transistor is connected to the drain of the first field effect transistor, the gate of the seventh field effect transistor, the gate of the sixth field effect transistor, the drain of the sixth field effect transistor, the first end of the fourth capacitor, and the gate of the tenth field effect transistor; The drain of the tenth field effect transistor is connected to the drain of the twelfth field effect transistor, the gate of the twelfth field effect transistor, and the gate of the thirteenth field effect transistor; The drain of the eleventh field effect transistor is connected to the drain of the thirteenth field effect transistor, the input end of the third inverter, and the second end of the fourth resistor; The source of the twelfth field effect transistor is connected to the source of the thirteenth field effect transistor, the output terminal of the third inverter and the output signal. 9. The level shift circuit according to claim 8 is characterized in that, when the input signal is at a high level, the output end of the first inverter is at a low level, the output end of the second inverter is at a high level, the second field effect transistor is turned on, the fourth field effect transistor is turned on, the eighth field effect transistor is turned on, the ninth field effect transistor is turned on, and the eleventh field effect transistor is turned on, and the input voltage of the third inverter is pulled up, and the output end of the third inverter outputs a low level; the first field effect transistor is turned off, and the third field effect transistor is turned off. 10. The level shift circuit according to claim 8 is characterized in that when the input signal is at a low level, the output end of the first inverter is at a high level, the output end of the second inverter is at a low level, the first field effect transistor is turned on, the third field effect transistor is turned on, the sixth field effect transistor is turned on, the seventh field effect transistor is turned on, the tenth field effect transistor is turned on, the twelfth field effect transistor is turned on, and the thirteenth field effect transistor is turned on, and the input voltage of the third inverter is pulled down, the output end of the third inverter outputs a high level, the eighth field effect transistor is turned off, the twelfth field effect transistor is turned off, and the thirteenth field effect transistor is turned off. 11. A chip, characterized by comprising the level shift circuit according to any one of claims 1 to 10. 12 . An electronic device, comprising the level shift circuit according to claim 1 or the chip according to claim 11 .