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CN118551715B - A circuit processing method, device and electronic device for analyzing circuit performance - Google Patents

A circuit processing method, device and electronic device for analyzing circuit performance Download PDF

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CN118551715B
CN118551715B CN202410982594.4A CN202410982594A CN118551715B CN 118551715 B CN118551715 B CN 118551715B CN 202410982594 A CN202410982594 A CN 202410982594A CN 118551715 B CN118551715 B CN 118551715B
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matrix
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CN118551715A (en
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请求不公布姓名
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Hangzhou Xingxin Technology Co ltd
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

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Abstract

The application relates to a circuit processing method, electronic equipment and storage medium for analyzing circuit performance, wherein the method comprises the following steps of dividing an RC network to be analyzed into at least one sub-network according to the circuit communication relation of the RC network to be analyzed, wherein the sub-network is provided with a preset number of ports, and a preset circuit model is a circuit model with the preset number of ports; and compressing at least one sub-network based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed. According to the technical scheme, the RC network to be analyzed is compressed based on the circuit connection relation, the complexity of the RC network to be analyzed is reduced, the efficiency of analyzing the circuit performance is improved, meanwhile, the RC network is compressed in a mode of compressing the sub-network based on the preset circuit model with the same port number as the sub-network, and the accuracy of analyzing the circuit performance can be ensured.

Description

Circuit processing method and device for analyzing circuit performance and electronic equipment
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a circuit processing method, apparatus, electronic device, and storage medium for analyzing circuit performance.
Background
With technological progress, chip design has entered into the nanometer-scale era, the number of transistors integrated on a single chip can reach 10-12 orders of magnitude, and how to realize more powerful functions and higher efficiency in a tiny chip becomes an important issue in chip design. Taking circuit power consumption as an example, power consumption management is a very important consideration in the chip design process. High power consumption can not only cause the chip to heat up, affecting its performance and reliability, but can also limit its usable operating frequency and battery life. Therefore, the circuit performance analysis and calculation are the basis of chip design optimization, and the chip can be ensured to meet the design requirement only by mastering an accurate performance analysis means.
Because of the complexity of modern integrated circuit designs, accurate performance analysis models often require significant computational resources and time, while performance optimization processes require rapid feedback of performance analysis results, such that performance analysis requires a balance between accuracy and efficiency. Therefore, there is a need for an analysis scheme that can improve computational efficiency while also having higher accuracy.
Disclosure of Invention
In view of the above technical problems, the present application provides a circuit processing method, apparatus, electronic device, and storage medium for analyzing circuit performance, which can improve efficiency of analyzing circuit performance and ensure accuracy of analyzing circuit performance.
In order to solve the above technical problems, the present application provides a circuit processing method for analyzing circuit performance, the method comprising the following steps:
Dividing the RC network to be analyzed into at least one sub-network according to the circuit communication relation of the RC network to be analyzed, wherein the sub-network is provided with a preset number of ports, and the preset circuit model is a circuit model with the preset number of ports;
and compressing at least one sub-network based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed.
In some embodiments, the method further comprises:
and carrying out power consumption analysis on the compression network.
In some embodiments, the dividing the RC network to be analyzed into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed includes:
And according to the circuit connection relation of the RC network to be analyzed, respectively taking the parts which are not in connection relation with each other in the RC network to be analyzed as a sub-network so as to divide the sub-network into at least one sub-network.
In some embodiments, the compressing at least one sub-network based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed includes:
Compressing a sub-network to be compressed based on the preset circuit model, and determining compressed first circuit information of the sub-network to be compressed;
And determining second circuit information of the compression network according to the compressed first circuit information of each sub-network to be compressed.
In some embodiments, the compressing the sub-network to be compressed based on the preset circuit model, and determining the compressed first circuit information of the sub-network to be compressed includes:
determining a conductance matrix and a capacitance matrix of the sub-network to be compressed;
And performing reduced-order processing on the conductance matrix and the capacitance matrix based on the preset circuit model, and determining compressed first circuit information of the sub-network to be compressed.
In some embodiments, the determining the conductance matrix and the capacitance matrix of the sub-network to be compressed comprises:
And determining a linear time independent system equation corresponding to the sub-network to be compressed according to the port number and the circuit structure information of the sub-network to be compressed, wherein the linear time independent system equation comprises a conductance matrix and a capacitance matrix of the sub-network to be compressed.
In some embodiments, the step-down processing the conductance matrix and the capacitance matrix based on the preset circuit model, determining the compressed first circuit information of the sub-network to be compressed includes:
performing reduced-order processing on the conductance matrix and the capacitance matrix based on a projection matrix;
determining an admittance matrix function corresponding to the reduced conductance matrix and the capacitor matrix;
Determining compressed first circuit information of the sub-network to be compressed according to the admittance matrix function;
Determining second circuit information of the compressed network according to the compressed first circuit information of each sub-network to be compressed, including:
Determining circuit structure information corresponding to the preset circuit model according to the first circuit information;
And determining second circuit information of the compression network according to the circuit structure information of the preset circuit model corresponding to each sub-network to be compressed.
In some embodiments, before the step-down processing is performed on the conductance matrix and the capacitance matrix based on the preset circuit model to determine the compressed first circuit information of the sub-network to be compressed, the method further includes:
Rearranging elements in the conductance matrix and the capacitance matrix, so that the elements of the conductance matrix and the capacitance matrix corresponding to the description internal nodes of the sub-network to be compressed are located in a first preset area in the corresponding matrix, and the elements of the conductance matrix and the capacitance matrix corresponding to the description port nodes of the sub-network to be compressed are located in a second preset area in the corresponding matrix;
And/or, before the rearranging the elements of the conductance matrix and the capacitance matrix, the method further comprises:
the linear time independent system equation is converted to the frequency domain.
In some embodiments, after converting the linear time independent system equation to the frequency domain and rearranging the elements in the conductance matrix and the capacitance matrix, the system equation expression is as follows:
Wherein, Is an element describing an internal node,Is an element describing a port node,,,,In order for the sub-matrix to be compressed,For sub-matrices that do not require compression,O representsA zero matrix of the dimensions is used,Is the current at the input port;
the projection matrix is represented as follows:
Wherein, Is an identity matrix;
Performing reduced-order processing on the conductance matrix based on the projection matrix to obtain a reduced-order conductance matrix The expression is as follows:
Performing reduced-order processing on the capacitance matrix based on the projection matrix to obtain a reduced-order capacitance matrix The expression is as follows:
Wherein, ;
An admittance matrix function corresponding to the reduced conductance matrix and the capacitance matrix has the following characteristicsDimensional form:
Wherein, Is the inverse of the resistance,Is a capacitor.
The present application also provides a circuit processing apparatus for analyzing circuit performance, comprising:
The sub-network determining module is used for dividing the RC network to be analyzed into at least one sub-network according to the circuit connection relation of the RC network to be analyzed;
And the compression module is used for carrying out compression processing on at least one sub-network based on a preset circuit model so as to obtain a compression network corresponding to the RC network to be analyzed.
The application also provides an electronic device comprising a storage medium and a controller, characterized in that the storage medium has stored thereon a computer program which, when executed by the controller, implements the steps of the circuit processing method for analysing circuit performance as described above.
The present application also provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of a circuit processing method for analysing circuit performance as described above.
The circuit processing method, the electronic equipment and the storage medium for analyzing the circuit performance comprise the steps of dividing an RC network to be analyzed into at least one sub-network according to the circuit connection relation of the RC network to be analyzed, wherein the sub-network is provided with a preset number of ports, a preset circuit model is a circuit model with the preset number of ports, compressing the at least one sub-network based on the preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed, and analyzing the compressed network. According to the technical scheme, the RC network to be analyzed is compressed based on the circuit connection relation, the complexity of the RC network to be analyzed is reduced, the efficiency of analyzing the circuit performance is improved, meanwhile, the RC network is compressed in a mode of compressing the sub-network based on the preset circuit model, and the accuracy of analyzing the circuit performance can be guaranteed.
Drawings
FIG. 1 is a flow diagram illustrating a circuit processing method for analyzing circuit performance according to one embodiment.
Fig. 2 is a schematic diagram of an RC network to be analyzed, according to one embodiment.
Fig. 3 is a schematic diagram illustrating a predetermined circuit model according to an embodiment.
FIG. 4 is a schematic diagram illustrating another predetermined circuit model according to an embodiment.
Fig. 5 is a schematic diagram of a conductivity matrix shown according to an embodiment.
Fig. 6 is a schematic diagram of a capacitive matrix shown according to an embodiment.
Fig. 7 is a schematic diagram of a rearranged conductance matrix, according to one embodiment.
Fig. 8 is a schematic diagram of a rearranged capacitive matrix, according to an embodiment.
Fig. 9 is a schematic diagram of a projection matrix shown according to an embodiment.
FIG. 10 is a comparative schematic of analysis results shown according to one embodiment.
FIG. 11 is a comparative schematic diagram showing another analysis result according to an embodiment.
Fig. 12 is a schematic diagram showing a structure of a circuit processing apparatus for analyzing circuit performance according to an embodiment.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. In the present invention, "each" includes one and two or more numbers.
FIG. 1 is a flow diagram illustrating a circuit processing method for analyzing circuit performance according to one embodiment. As shown in fig. 1, the circuit processing method for analyzing circuit performance of the present application comprises the steps of:
S1, dividing an RC network to be analyzed into at least one sub-network according to a circuit connection relation of the RC network to be analyzed;
s2, compressing at least one sub-network based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed.
The RC network to be analyzed may be a power RC network under a package structure or at a PCB level (Printed circuit board ), or may be another RC network to be analyzed. Fig. 2 is a schematic diagram of an RC network to be analyzed, specifically, a power RC network, including a power supply network (VDD) and a ground network (VSS), but the RC network to be analyzed is not limited thereto.
The sub-network of the RC-network to be analyzed may be the RC-network to be analyzed itself, i.e. the whole RC-network to be analyzed corresponds to one sub-network. The sub-network of the RC network to be analyzed may also be a circuit network in the RC network to be analyzed, that is, the RC network to be analyzed is divided into more than one circuit network, and at least one of the divided circuit networks is used as the sub-network. The RC network is compressed in a mode of compressing the sub-network based on a preset circuit model, so that the analysis precision can be ensured.
In some embodiments, the sub-network has a preset number of ports, and the preset number of ports may be set according to needs, for example, two ports and three ports, which are preferred in this embodiment. The preset circuit model is a circuit model with a preset number of ports, that is, the number of ports of the preset circuit model is the same as the number of ports of the sub-network, and the complexity of the compressed RC network and the compression efficiency are determined by the selection of the preset circuit model.
In some embodiments, the preset circuit model may select a double-T model as shown in fig. 3, or a circuit model having three ports as shown in fig. 4, and the preset circuit model is not limited thereto according to the number of ports selected. Preferably, the sub-network selects a two-port network, and the preset circuit model selects a double-T model, so that the compression process is simpler, the compressed RC network has proper node number, and the efficiency and the precision of analyzing the circuit performance can be better considered. In some embodiments, a power consumption analysis or other circuit performance analysis may be performed on the compressed network.
The preset circuit models corresponding to different sub-networks can be the same or different, so that a proper preset circuit model can be selected according to the circuit information of the sub-networks, and analysis efficiency and analysis precision are considered.
According to the complexity of different sub-networks, all the sub-networks can be compressed, and part of the sub-networks can be compressed, so that the compression is not needed for the sub-networks with lower complexity, the compression speed is improved, and meanwhile, the analysis precision can be further ensured. When compression processing is performed on all the sub-networks, all the compressed sub-networks form a compression network. When the partial sub-networks are compressed, the sub-networks which are not compressed and the sub-networks which are compressed form a compressed network.
The RC network to be analyzed is divided according to the circuit connection relation of the RC network to be analyzed, so that the compression results of the sub-networks are more in line with the circuit connection relation of the original network, and the compression accuracy is improved. The RC network is provided with a plurality of current paths, the current paths can be mutually communicated, current can flow between different paths, the current paths can be not mutually communicated, no current flows between the current paths which are not mutually communicated, and a circuit communication relationship is used for indicating whether the current paths are mutually communicated.
In some embodiments, the user-specified io ports that need to be reserved are obtained, and the RC network to be analyzed is partitioned according to the number and distribution of ports.
In some embodiments, dividing the RC network to be analyzed into at least one subnetwork according to a circuit connectivity relationship of the RC network to be analyzed, comprising:
According to the circuit connection relation of the RC network to be analyzed, the parts which are not connected with each other in the RC network to be analyzed are respectively used as a sub-network so as to divide the sub-network into at least one sub-network.
The io port is reserved according to the circuit connection relation of the RC network to be analyzed, and each sub-network is correspondingly provided with the io port. Taking the RC network shown in fig. 2 as an example, after circuit division, VDD and VSS are respectively used as a sub-network, and are both two-port networks. The part without the communication relation refers to that no current flows between the two part networks, and the part without the communication relation in the RC network to be analyzed is respectively used as a sub-network, so that the compression processes of different sub-networks can be mutually decoupled, and the compression process is simplified.
In some embodiments, compressing at least one sub-network based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed includes:
compressing the sub-network to be compressed based on a preset circuit model, and determining compressed first circuit information of the sub-network to be compressed;
and determining second circuit information of the compressed network according to the compressed first circuit information of each sub-network.
And respectively compressing the sub-networks to be compressed to obtain compressed first circuit information of the sub-networks to be compressed. The first circuit information refers to mathematical information generated in the compression process for describing the corresponding circuit, and may be, for example, matrix, resistance, capacitance, conductance, and the like. The second circuit information is circuit structure information including resistance, capacitance and connection relation thereof, that is, the second circuit information is information which is processed according to mathematical information generated in the compression process and can represent the resistance, capacitance and connection relation thereof of the compression circuit.
When compression processing is carried out on all the sub-networks, second circuit information of the compression network is determined according to the first circuit information of all the compressed sub-networks. When compression processing is performed on a part of the sub-networks, the circuit configuration information of the sub-networks which are not compressed and the first circuit information of the sub-networks which are compressed determine the second circuit information of the compressed network. And (3) obtaining a netlist file for describing the compressed network according to the second circuit information of the compressed network, and performing required analysis by utilizing the netlist file corresponding to the compressed network based on the step (S3) to realize analysis of the RC network to be analyzed.
In some embodiments, compressing the sub-network to be compressed based on a preset circuit model, determining compressed first circuit information of the sub-network to be compressed includes:
s21, determining a conductance matrix and a capacitance matrix of a sub-network to be compressed;
S22, performing reduced-order processing on the conductance matrix and the capacitance matrix based on a preset circuit model, and determining compressed first circuit information of the sub-network to be compressed.
The method comprises the steps of carrying out reduced order processing on the conductance matrix and the capacitance matrix, and reducing the number of nodes of the sub-network to be compressed to the number of nodes corresponding to a preset circuit model, so that the number of nodes of the RC network to be analyzed is reduced, the complexity of a circuit is reduced, the analysis can be completed in a short time, and the analysis efficiency is improved.
In some embodiments, the conductance matrix is a symmetric non-negative definite matrix and the capacitance matrix is a diagonal matrix of capacitances to ground.
In some embodiments, S21, determining the conductance matrix and the capacitance matrix of the sub-network to be compressed includes:
And determining a linear time independent system equation corresponding to the sub-network to be compressed according to the port number and the circuit structure information of the sub-network to be compressed, wherein the linear time independent system equation comprises a conductance matrix and a capacitance matrix of the sub-network to be compressed.
Wherein, according to the circuit structure information, the following linear time independent system equation (LINEAR TIME-invariant, LTI) is generated for each sub-network to be compressed:
Wherein, Is a conductance matrix, a symmetrical non-negative definite matrix,Representing the voltage at the node and,Is a diagonal matrix of capacitances to ground (i.e. a capacitance matrix),Is the current at the input port and,Is the correlation matrix of the input port current and the nodes, p is the number of ports, p=2 in the equation of the two-port network, n is equal to the number of nodes, and t represents time.
In some embodiments, the linear time independent system equation may be converted to the frequency domain as follows:
Where s represents an argument in the frequency domain. After the conversion to the frequency domain, the expression of the equation is simpler, and the calculation process can be further simplified. The conductance matrix and the capacitance matrix are unchanged when the frequency domain is converted.
In some embodiments, S22, performing reduced-order processing on the conductance matrix and the capacitance matrix based on a preset circuit model, determining compressed first circuit information of the sub-network to be compressed, including:
Performing reduced-order processing on the conductance matrix and the capacitance matrix according to the projection matrix;
determining an admittance matrix function corresponding to the reduced conductance matrix and the capacitor matrix;
And determining compressed first circuit information of the sub-network to be compressed according to the admittance matrix function.
In some embodiments, determining second circuit information of the compressed network from the compressed first circuit information of each sub-network to be compressed includes:
determining circuit structure information corresponding to a preset circuit model according to the first circuit information;
And determining second circuit information of the compression network according to the circuit structure information of the preset circuit model corresponding to each sub-network to be compressed.
Wherein the projection matrix is used for performing reduced order processing on the conductance matrix and the capacitance matrix, so that after the conductance matrix and the capacitance matrix are reduced in order, an admittance matrix functionThe order reduction is also performed, and information in the admittance matrix function after the order reduction can be extracted as the first circuit information, and in this embodiment, the information used as the first circuit information in the admittance matrix function after the order reduction includes a conductance value and a capacitance value.
According to the information of the admittance matrix function, the circuit structure information corresponding to the preset circuit model can be determined, and the circuit structure information corresponding to the preset circuit model is equivalent to the compressed circuit structure information of the sub-network to be compressed.
In some embodiments, to further reduce the complexity of the calculation, S22 performs a reduced-order process on the conductance matrix and the capacitance matrix based on a preset circuit model, and before determining the compressed first circuit information of the sub-network to be compressed, the method further includes:
Rearranging elements in the conductance matrix and the capacitance matrix, so that the elements of the conductance matrix and the capacitance matrix corresponding to the description internal nodes of the sub-network to be compressed are located in a first preset area in the corresponding matrix, and the elements of the conductance matrix and the capacitance matrix corresponding to the description port nodes of the sub-network to be compressed are located in a second preset area in the corresponding matrix.
After rearranging the conductance matrix and the capacitance matrix, the system equation expression is as follows:
Wherein, Is an internal node which is connected to the network,Is a port node which,,,,In order for the sub-matrix to be compressed,For sub-matrices that do not require compression,O representsZero matrix of dimensions.
When the conductance matrix and the capacitance matrix are rearranged, elements describing the port nodes are found according to port numbers to be rearranged, and the positions of the other elements in the matrix are adapted to be adjusted, so that the elements describing the port nodes and the elements describing the internal nodes are respectively concentrated in corresponding areas of the matrix, for example, the elements describing the port nodes are adjusted to be positioned at the corner positions of the matrix, and the elements describing the internal nodes are adjusted to other areas beyond the corner positions.
After the conductance matrix and the capacitance matrix are rearranged, the expression of the projection matrix and the process of reducing the order of the conductance matrix and the capacitance matrix can be simplified. It can be understood that, on the basis of the technical concept of the present application, even if the conductance matrix and the capacitance matrix are not rearranged, the computational complexity is increased to a certain extent relative to the rearrangement processing, but the reduction of the conductance matrix and the capacitance matrix can be completed only by constructing a proper projection matrix, which is not described herein.
In some embodiments, after rearranging the conductance matrix and the capacitance matrix, the constructed projection matrix V may be represented as follows:
Wherein, Is an identity matrix. The projection matrix V is acted on two ends of the rearranged conductance matrix and the capacitor matrix to obtain a reduced conductance matrixCapacitive matrix:
Recording deviceThen:
Then, the admittance matrix function after the reduction can be obtained, and the admittance matrix function has the following characteristics Dimensional form:
Wherein, Is the inverse of the resistance,Is a capacitor.
And then, calculating circuit structure information corresponding to a preset circuit model according to the information of the admittance matrix function, and obtaining the compressed circuit structure information of the sub-network to be compressed. Specifically, "reduction" is performed on the reduced circuit equation (matrix), namely, circuit synthesis is performed, so as to obtain circuit structure information of a small-scale RC circuit, wherein the small-scale RC circuit is a sub-network after compression.
Taking the double-T model with five unknown elements (three resistors and two capacitors) as an example, as shown in fig. 2, a reduced-order circuit with the same properties as the original circuit is used, wherein R1>0, rm >0, R2>0, C1>0, and C2>0 are required. Using admittance functionsCan obtain circuit information satisfying the circuit model shown in fig. 2:
Wherein,
Wherein k may take any value satisfying the following conditions:
in general, it is possible to take 。
The first circuit information after the sub-network to be compressed is obtained, a series of sub-networks obtained by dividing are processed according to the steps, a series of compressed circuit models are finally obtained, and then the compressed circuit models are combined into a new compressed network, so that the netlist file corresponding to the compressed network can be utilized for carrying out required analysis.
Next, taking an RC network to be analyzed as a power network as an example, a calculation procedure of the circuit processing method for analyzing circuit performance of the present application is illustrated.
Firstly, the RC Spice model of the power supply network and the opposite network is extracted as follows:
.subckt VDD_0_arc 1 25
R1 6 1 1.7094193
R2 2 3 6.5406294
R3 4 5 6.5406294
R4 6 7 1.7094193
R5 8 9 1.0920632
R6 10 11 1.0920632
R7 12 13 1.0920632
R8 14 15 1.0920632
R9 16 17 1.0920632
R10 18 19 1.0899954
R11 20 21 1.0899954
R12 22 23 1.0899954
R13 24 25 0.2930939
R14 2 7 1.0899954
R15 3 8 1.0899954
R16 9 4 1.0899954
R17 5 10 0.2930939
R18 12 11 0.2930939
R19 14 13 0.2930939
R20 16 15 0.2930939
R21 18 17 0.2930939
R22 19 20 0.2930939
R23 21 22 1.4245161
R24 23 24 0.09495385
C1 1 02.388319e-14
C2 3 0 1.1778861e-14
C3 6 0 4.599731e-15
C4 9 0 5.2077555e-15
C5 10 0 1.2396841e-14
C6 12 0 5.4866686e-15
C7 18 0 2.0988753e-13
C8 21 0 2.0741826e-13
C9 25 0 2.0741826e-13
.ends
Taking R1 6 1.7094193 as an example, R1 is a resistor name, 6 and 1 are node numbers corresponding to R1, and 1.7094193 is a resistor value (unit: ohm). Taking C1.388319 e-14 as an example, C1 is a resistor name, 1 and 0 are node numbers corresponding to C1 respectively, wherein 0 represents ground, 2.388319e-14 is a capacitance value (unit: method).
Next, the io port 1,25 that needs to be reserved is selected. It can be seen that the network has only one two-port network, so that the network is not divided, and the conductance matrix and the capacitance matrix are directly generated according to the netlist information. The conductance matrix is shown in fig. 5, and the capacitance matrix is shown in fig. 6.
Then, the conductance matrix and the capacitance matrix are rearranged according to the port numbers, the rearrangement result of the conductance matrix is shown in fig. 7, and the rearrangement result of the capacitance matrix is shown in fig. 8. From the division result, it is possible to obtain,,I.e.A sub-matrix of 1 to 23 rows and 1 to 23 columns of G,A sub-matrix of 1 to 23 rows and 24 to 25 columns of G,A sub-matrix of 24 to 25 rows and 1 to 23 columns of G,A sub-matrix of 24 to 25 rows and 24 to 25 columns of G is similarly available;,,,。
Next, a reduced order process is performed, and a projection matrix is constructed as shown in fig. 9. The reduced admittance matrix function can be calculated, wherein the conductance value and the capacitance value are the first circuit information:
as shown in fig. 2, according to the reduced admittance function matrix information, the compressed circuit structure information can be obtained by calculation as follows:
R1 = 13.50991857;
Rm = 17.18914469;
R2 = 1.37244980;
C1 = 1.29439360e-13;
C2 = 5.58637737e-13。
Finally, taking power consumption analysis as an example, simulating the compressed circuit, and obtaining simulation results as shown in fig. 10 and 11, wherein two curves in fig. 10 are overlapped, the simulation results are correct, the maximum error of the two curves in fig. 11 is 0.019%, and the simulation results are within an acceptable range.
As shown in fig. 12, the present application further provides a circuit processing apparatus for analyzing circuit performance, including:
The sub-network determining module 11 is configured to divide the RC network to be analyzed into at least one sub-network according to a circuit connection relationship of the RC network to be analyzed, where the sub-network has a preset number of ports, and the preset circuit model is a circuit model with a preset number of ports;
The compression module 12 is configured to perform compression processing on at least one sub-network based on a preset circuit model, so as to obtain a compression network corresponding to the RC network to be analyzed.
In some embodiments, the apparatus further comprises an analysis module for performing a power consumption analysis on the compressed network.
In some embodiments, when the RC network to be analyzed is divided into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed, the sub-network determining module 11 is configured to:
According to the circuit connection relation of the RC network to be analyzed, the parts which are not connected with each other in the RC network to be analyzed are respectively used as a sub-network so as to divide the sub-network into at least one sub-network.
In some embodiments, compression module 12 is configured to:
compressing the sub-network to be compressed based on a preset circuit model, and determining compressed first circuit information of the sub-network to be compressed;
And determining second circuit information of the compressed network according to the compressed first circuit information of each sub-network to be compressed.
In some embodiments, the compressing module 12 is configured to, when performing compression processing on the sub-network to be compressed based on the preset circuit model and determining the compressed first circuit information of the sub-network to be compressed:
Determining a conductance matrix and a capacitance matrix of a sub-network to be compressed;
and performing reduced-order processing on the conductance matrix and the capacitance matrix based on a preset circuit model, and determining compressed first circuit information of the sub-network to be compressed.
In some embodiments, in determining the conductance matrix and the capacitance matrix of the subnetwork to be compressed, the compression module 12 is configured to:
And determining a linear time independent system equation corresponding to the sub-network to be compressed according to the port number and the circuit structure information of the sub-network to be compressed, wherein the linear time independent system equation comprises a conductance matrix and a capacitance matrix of the sub-network to be compressed.
In some embodiments, when performing the reduced-order processing on the conductance matrix and the capacitance matrix based on the preset circuit model and determining the compressed first circuit information of the sub-network to be compressed, the compression module 12 is configured to:
Performing reduced-order processing on the conductance matrix and the capacitance matrix according to the projection matrix;
determining an admittance matrix function corresponding to the reduced conductance matrix and the capacitor matrix;
And determining compressed first circuit information of the sub-network to be compressed according to the admittance matrix function.
In some embodiments, the compression module 12 is configured to determine the second circuit information of the compression network according to the compressed first circuit information of each sub-network to be compressed:
determining circuit structure information corresponding to a preset circuit model according to the first circuit information;
And determining second circuit information of the compression network according to the circuit structure information of the preset circuit model corresponding to each sub-network to be compressed.
In some embodiments, the apparatus further includes a rearrangement module configured to, before performing a reduced-order process on the conductance matrix and the capacitance matrix based on a preset circuit model, determine compressed first circuit information of the sub-network to be compressed:
Rearranging elements in the conductance matrix and the capacitance matrix, so that the elements of the conductance matrix and the capacitance matrix corresponding to the description internal nodes of the sub-network to be compressed are positioned in a first preset area in the corresponding matrix, and the elements of the conductance matrix and the capacitance matrix corresponding to the description port nodes of the sub-network to be compressed are positioned in a second preset area in the corresponding matrix;
and/or the apparatus further comprises a conversion module for, prior to reordering the conductance matrix and the capacitance matrix:
The linear time independent system equation is converted to the frequency domain.
In some embodiments, after converting the linear time independent system equation to the frequency domain and rearranging the elements in the conductance matrix and the capacitance matrix, the system equation expression is as follows:
Wherein, Is an element describing an internal node,Is an element describing a port node,,,,In order for the sub-matrix to be compressed,For sub-matrices that do not require compression,O representsA zero matrix of the dimensions is used,Is the current at the input port;
the projection matrix is represented as follows:
Wherein, Is an identity matrix;
Performing reduced-order processing on the conductance matrix based on the projection matrix to obtain a reduced-order conductance matrix The expression is as follows:
Performing reduced-order processing on the capacitance matrix based on the projection matrix to obtain a reduced-order capacitance matrix The expression is as follows:
Wherein, ;
An admittance matrix function corresponding to the reduced conductance matrix and the capacitance matrix has the following characteristicsDimensional form:
Wherein, Is the inverse of the resistance,Is a capacitor.
The specific implementation process of the steps executed by each module in the circuit processing device for analyzing the circuit performance is referred to the description of the method embodiment, and will not be repeated.
The present application also provides an electronic device including a storage medium and a controller, the storage medium having stored thereon a computer program which, when executed by the controller, implements the steps of the circuit processing method for analyzing circuit performance as described in the above embodiments.
The present application also provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the circuit processing method for analysing circuit performance as described in the above embodiments.
The circuit processing method, the electronic equipment and the storage medium for analyzing the circuit performance comprise the steps of dividing an RC network to be analyzed into at least one sub-network according to the circuit connection relation of the RC network to be analyzed, and compressing the at least one sub-network based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed, wherein the sub-network is provided with a preset number of ports, and the preset circuit model is a circuit model with the preset number of ports. According to the technical scheme, the RC network to be analyzed is compressed based on the circuit connection relation, the complexity of the RC network to be analyzed is reduced, the efficiency of analyzing the circuit performance is improved, meanwhile, the RC network is compressed in a mode of compressing the sub-network based on the preset circuit model, and the accuracy of analyzing the circuit performance can be guaranteed.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims (12)

1.一种用于分析电路性能的电路处理方法，其特征在于，所述方法包括以下步骤：1. A circuit processing method for analyzing circuit performance, characterized in that the method comprises the following steps: 根据待分析的RC网络的电路连通关系，将所述待分析的RC网络划分为至少一子网络，所述子网络具有预设数量的端口；According to the circuit connectivity relationship of the RC network to be analyzed, the RC network to be analyzed is divided into at least one sub-network, wherein the sub-network has a preset number of ports; 基于预设电路模型对至少一所述子网络进行压缩处理，以得到所述待分析的RC网络对应的压缩网络，包括：Compressing at least one of the sub-networks based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed includes: 基于所述预设电路模型对待压缩的子网络进行压缩处理，确定所述待压缩的子网络的压缩后的第一电路信息，所述预设电路模型为具有所述预设数量的端口的电路模型，第一电路信息是指压缩过程中产生的用于描述电路的数学信息，包括电容、电导；Based on the preset circuit model, the sub-network to be compressed is compressed to determine the compressed first circuit information of the sub-network to be compressed, wherein the preset circuit model is a circuit model with the preset number of ports, and the first circuit information refers to mathematical information generated during the compression process for describing the circuit, including capacitance and conductance; 根据所述第一电路信息确定所述预设电路模型对应的电路结构信息；Determine circuit structure information corresponding to the preset circuit model according to the first circuit information; 根据各所述待压缩的子网络对应的预设电路模型的电路结构信息，确定所述压缩网络的第二电路信息，所述第二电路信息为电路结构信息。According to the circuit structure information of the preset circuit model corresponding to each of the sub-networks to be compressed, the second circuit information of the compressed network is determined, where the second circuit information is the circuit structure information. 2.根据权利要求1所述的方法，其特征在于，所述方法还包括：2. The method according to claim 1, characterized in that the method further comprises: 对所述压缩网络进行功耗分析。A power consumption analysis is performed on the compression network. 3.根据权利要求1所述的方法，其特征在于，所述根据待分析的RC网络的电路连通关系，将所述待分析的RC网络划分为至少一子网络，包括：3. The method according to claim 1, characterized in that the step of dividing the RC network to be analyzed into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed comprises: 根据所述待分析的RC网络的电路连通关系，将所述待分析的RC网络中相互不具有连通关系的部分分别作为一所述子网络，以划分得到至少一所述子网络。According to the circuit connectivity relationship of the RC network to be analyzed, the parts of the RC network to be analyzed that are not connected to each other are respectively taken as a sub-network to obtain at least one sub-network. 4.根据权利要求1所述的方法，其特征在于，所述基于预设电路模型对待压缩的子网络进行压缩处理，确定所述待压缩的子网络的压缩后的第一电路信息，包括：4. The method according to claim 1, characterized in that the compressing the sub-network to be compressed based on the preset circuit model to determine the compressed first circuit information of the sub-network to be compressed comprises: 确定所述待压缩的子网络的电导矩阵和电容矩阵；Determining the conductivity matrix and the capacitance matrix of the sub-network to be compressed; 基于所述预设电路模型对所述电导矩阵和电容矩阵进行降阶处理，确定所述待压缩的子网络的压缩后的第一电路信息。The conductance matrix and the capacitance matrix are subjected to order reduction processing based on the preset circuit model to determine compressed first circuit information of the sub-network to be compressed. 5.根据权利要求4所述的方法，其特征在于，所述确定所述待压缩的子网络的电导矩阵和电容矩阵，包括：5. The method according to claim 4, characterized in that the determining of the conductance matrix and the capacitance matrix of the sub-network to be compressed comprises: 根据所述待压缩的子网络的端口数量与电路结构信息，确定所述待压缩的子网络对应的线性时无关系统方程，其中，所述线性时无关系统方程中包含所述待压缩的子网络的电导矩阵和电容矩阵。According to the number of ports and circuit structure information of the sub-network to be compressed, a linear time-independent system equation corresponding to the sub-network to be compressed is determined, wherein the linear time-independent system equation includes a conductance matrix and a capacitance matrix of the sub-network to be compressed. 6.根据权利要求5所述的方法，其特征在于，所述基于所述预设电路模型对所述电导矩阵和电容矩阵进行降阶处理，确定所述待压缩的子网络的压缩后的第一电路信息之前，所述方法还包括：6. The method according to claim 5, characterized in that before the step of reducing the order of the conductance matrix and the capacitance matrix based on the preset circuit model to determine the compressed first circuit information of the sub-network to be compressed, the method further comprises: 对所述电导矩阵和电容矩阵中的元素进行重排，使所述电导矩阵和电容矩阵中对应所述待压缩的子网络的描述内部节点的元素位于相应矩阵中的第一预设区域，使所述电导矩阵和电容矩阵中对应所述待压缩的子网络的描述端口节点的元素位于相应矩阵中的第二预设区域；Rearranging the elements in the conductance matrix and the capacitance matrix so that the elements describing the internal nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a first preset area in the corresponding matrix, and the elements describing the port nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a second preset area in the corresponding matrix; 和/或，所述对所述电导矩阵和电容矩阵的元素进行重排之前，所述方法还包括：And/or, before rearranging the elements of the conductivity matrix and the capacitance matrix, the method further comprises: 将所述线性时无关系统方程转换至频域。The linear time-independent system equations are transformed into the frequency domain. 7.根据权利要求5所述的方法，其特征在于，所述基于所述预设电路模型对所述电导矩阵和电容矩阵进行降阶处理，确定所述待压缩的子网络的压缩后的第一电路信息，包括：7. The method according to claim 5, characterized in that the step of reducing the order of the conductance matrix and the capacitance matrix based on the preset circuit model to determine the compressed first circuit information of the sub-network to be compressed comprises: 基于投影矩阵对所述电导矩阵和电容矩阵进行降阶处理；Performing order reduction processing on the conductance matrix and the capacitance matrix based on the projection matrix; 确定与降阶后的电导矩阵和电容矩阵对应的导纳矩阵函数；Determine the admittance matrix function corresponding to the reduced-order conductance matrix and capacitance matrix; 根据所述导纳矩阵函数确定所述待压缩的子网络的压缩后的第一电路信息。The compressed first circuit information of the sub-network to be compressed is determined according to the admittance matrix function. 8.根据权利要求7所述的方法，其特征在于，所述基于所述预设电路模型对所述电导矩阵和电容矩阵进行降阶处理，确定所述待压缩的子网络的压缩后的第一电路信息之前，所述方法还包括：8. The method according to claim 7, characterized in that before the step of reducing the order of the conductance matrix and the capacitance matrix based on the preset circuit model to determine the compressed first circuit information of the sub-network to be compressed, the method further comprises: 对所述电导矩阵和电容矩阵中的元素进行重排，使所述电导矩阵和电容矩阵中对应所述待压缩的子网络的描述内部节点的元素位于相应矩阵中的第一预设区域，使所述电导矩阵和电容矩阵中对应所述待压缩的子网络的描述端口节点的元素位于相应矩阵中的第二预设区域；Rearranging the elements in the conductance matrix and the capacitance matrix so that the elements describing the internal nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a first preset area in the corresponding matrix, and the elements describing the port nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a second preset area in the corresponding matrix; 和/或，所述对所述电导矩阵和电容矩阵的元素进行重排之前，所述方法还包括：And/or, before rearranging the elements of the conductivity matrix and the capacitance matrix, the method further comprises: 将所述线性时无关系统方程转换至频域。The linear time-independent system equations are transformed into the frequency domain. 9.根据权利要求8所述的方法，其特征在于，将所述线性时无关系统方程转换至频域，并对所述电导矩阵和电容矩阵中的元素进行重排后，所述系统方程表达式如下：9. The method according to claim 8, characterized in that after converting the linear time-independent system equation to the frequency domain and rearranging the elements in the conductance matrix and the capacitance matrix, the system equation expression is as follows: ， , 其中，是描述内部节点的元素，是描述端口节点的元素，，，，，，，，，，，为需要压缩的子矩阵，，为不需要压缩的子矩阵，，O代表维的零矩阵，是输入端口的电流；in, is an element that describes an internal node. is an element describing a port node, , , , , , , , , , , is the sub-matrix that needs to be compressed, , is the sub-matrix that does not need to be compressed, , O represents dimensional zero matrix, is the current at the input port; 所述投影矩阵表示如下：The projection matrix is expressed as follows: ， , 其中，，是单位矩阵；in, , is the identity matrix; 基于所述投影矩阵对所述电导矩阵进行降阶处理，得到降阶后的电导矩阵 表示如下：The conductivity matrix is reduced in order based on the projection matrix to obtain a reduced-order conductivity matrix. It is expressed as follows: ， , 基于所述投影矩阵对所述电容矩阵进行降阶处理，得到降阶后的电容矩阵，表示如下：The capacitance matrix is reduced in order based on the projection matrix to obtain a reduced capacitance matrix. , which is expressed as follows: ， , 其中，；in, ; 与降阶后的电导矩阵和电容矩阵对应的导纳矩阵函数，具有如下维形式：The admittance matrix function corresponding to the reduced-order conductance matrix and capacitance matrix has the following Dimensional form: ， , 其中，，为电阻的倒数，，为电容。in, , is the reciprocal of resistance, , is the capacitance. 10.一种用于分析电路性能的电路处理装置，其特征在于，包括：10. A circuit processing device for analyzing circuit performance, comprising: 子网络确定模块，用于根据待分析的RC网络的电路连通关系，将所述待分析的RC网络划分为至少一子网络，所述子网络具有预设数量的端口；A sub-network determination module, configured to divide the RC network to be analyzed into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed, wherein the sub-network has a preset number of ports; 压缩模块，用于基于预设电路模型对至少一所述子网络进行压缩处理，以得到所述待分析的RC网络对应的压缩网络，包括：A compression module, used for compressing at least one of the sub-networks based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed, comprising: 基于所述预设电路模型对待压缩的子网络进行压缩处理，确定所述待压缩的子网络的压缩后的第一电路信息，所述预设电路模型为具有所述预设数量的端口的电路模型，第一电路信息是指压缩过程中产生的用于描述电路的数学信息，包括电容、电导；Based on the preset circuit model, the sub-network to be compressed is compressed to determine the compressed first circuit information of the sub-network to be compressed, wherein the preset circuit model is a circuit model with the preset number of ports, and the first circuit information refers to mathematical information generated during the compression process for describing the circuit, including capacitance and conductance; 根据所述第一电路信息确定所述预设电路模型对应的电路结构信息；Determine circuit structure information corresponding to the preset circuit model according to the first circuit information; 根据各所述待压缩的子网络对应的预设电路模型的电路结构信息，确定所述压缩网络的第二电路信息，所述第二电路信息为电路结构信息。According to the circuit structure information of the preset circuit model corresponding to each of the sub-networks to be compressed, the second circuit information of the compressed network is determined, where the second circuit information is the circuit structure information. 11.一种电子设备，包括存储介质与控制器，其特征在于，所述存储介质上存储有计算机程序，所述计算机程序被所述控制器执行时实现如权利要求1至9中任一项所述的用于分析电路性能的电路处理方法的步骤。11. An electronic device, comprising a storage medium and a controller, wherein a computer program is stored on the storage medium, and when the computer program is executed by the controller, the steps of the circuit processing method for analyzing circuit performance as described in any one of claims 1 to 9 are implemented. 12.一种存储介质，其特征在于，所述存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至9中任一项所述的用于分析电路性能的电路处理方法的步骤。12. A storage medium, characterized in that a computer program is stored on the storage medium, and when the computer program is executed by a processor, the steps of the circuit processing method for analyzing circuit performance according to any one of claims 1 to 9 are implemented.
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