CN118591279B

CN118591279B - Columnar capacitor and forming method thereof

Info

Publication number: CN118591279B
Application number: CN202411067360.3A
Authority: CN
Inventors: 钟晓伟
Original assignee: Hangzhou Jihai Semiconductor Co ltd
Current assignee: Hangzhou Jihai Semiconductor Co ltd
Priority date: 2024-08-06
Filing date: 2024-08-06
Publication date: 2024-11-19
Anticipated expiration: 2044-08-06
Also published as: CN118591279A

Abstract

The invention provides a columnar capacitor and a forming method thereof, and belongs to the technical field of semiconductor device manufacturing. The columnar capacitor comprises a substrate, a conductive columnar core, a cylindrical dielectric layer, a conductive layer and a first conductive structure; wherein, the conductive column core is arranged in the substrate, and the conductive column core extends along the horizontal direction; the cylindrical medium layer circumferentially coats the surface of the conductive column core and exposes part of the surface of the conductive column core; the conductive layer is arranged between the conductive column core and the substrate, and the conductive layer is coated on the periphery of the cylindrical dielectric layer along the circumferential direction; the first conductive structure is in conductive contact with the exposed surface of the conductive column core and is insulated and isolated from the conductive layer. The columnar capacitor provided by the invention is easy to stack in the three-dimensional space of the integrated circuit to form a capacitor array with high capacity and high stability.

Description

Columnar capacitor and forming method thereof

Technical Field

The invention relates to the technical field of semiconductor device manufacturing, in particular to a columnar capacitor and a forming method thereof.

Background

In the semiconductor field, capacitance is a critical electronic component that has a direct impact on the performance of integrated circuits. The existing capacitor is limited by the structure, capacity and forming process, and is difficult to form a capacitor array with high density and high stability in the limited space of an integrated circuit, and cannot be adapted to the integrated circuit which needs high-density integration and high-capacity storage.

Therefore, it is necessary to design a columnar capacitor and a method for forming the same to solve the above-mentioned problems.

Disclosure of Invention

In view of the above drawbacks of the prior art, the present invention provides a columnar capacitor and a forming method thereof, so as to solve the technical problem that it is difficult to form a capacitor array with high density and high stability in a limited space by using the existing capacitor devices (such as planar capacitor and deep trench capacitor).

To achieve the above and other related objects, the present invention provides a columnar capacitor including a substrate, a conductive columnar core, a columnar dielectric layer, a conductive layer, and a first conductive structure;

Wherein, the conductive column core is arranged in the substrate, and the conductive column core extends along the horizontal direction; the cylindrical medium layer circumferentially coats the surface of the conductive column core and exposes part of the surface of the conductive column core; the conductive layer is arranged between the conductive column core and the substrate, and the conductive layer is coated on the periphery of the cylindrical dielectric layer along the circumferential direction; the first conductive structure is in conductive contact with the exposed surface of the conductive column core and is insulated and isolated from the conductive layer.

The invention also provides a forming method of the columnar capacitor, which comprises the following steps:

Providing a substrate;

Forming a trench on a substrate, and forming a conductor layer in the trench; steps are arranged at two ends of the groove, and the steps at two ends of the groove support the conductor layer so that gaps are reserved between part of the conductor layer and the side wall and the bottom wall of the groove;

Rounding the surface angle of the conductor layer to form a conductive column core;

Forming a dielectric layer on the surfaces of the groove and the conductive column core; the dielectric layer comprises a cylindrical dielectric layer positioned on the surface of the conductive column core and a groove surface dielectric layer positioned on the surface of the groove;

Forming a conductive layer in the groove, so that the conductive layer circumferentially surrounds the cylindrical dielectric layer;

And forming a first conductive structure above the conductive column core, wherein the first conductive structure is in conductive connection with the conductive column core and is insulated and isolated from the conductive layer.

The invention provides a columnar capacitor and a forming method thereof, wherein the columnar capacitor is transversely arranged in a shallow groove of a substrate, compared with the prior capacitor, the columnar capacitor does not need to use the substrate as a back electrode, and a conductive column core transversely arranged and a conductive layer surrounding the outer side of the conductive column core are respectively used as two end electrodes. The columnar capacitor structure is arranged in the shallow groove of the substrate, so that the columnar capacitor can be formed in the front-end process or the back-end process, and the columnar capacitor is based on the columnar structure extending along the plane direction of the substrate, so that the columnar capacitor is easier to stack in a three-dimensional space with high capacity and high stability.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a top view of a pillar capacitor according to an embodiment of the invention

FIG. 2 is a cross-sectional view of a pillar-shaped capacitor along the A-A direction (first direction) according to an embodiment of the present invention;

FIG. 3 is a cross-sectional view of a pillar capacitor along the B-B direction (second direction) according to an embodiment of the present invention;

FIG. 4 is a flow chart of a method for forming a pillar capacitor according to an embodiment of the invention;

FIG. 5 is a schematic diagram of a substrate provided in an embodiment of the invention;

FIG. 6 is a flowchart of step S2 according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of forming a first recess on a substrate and filling a sacrificial layer in the first recess according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of forming a second recess in a substrate according to an embodiment of the invention;

FIG. 9 is a cross-sectional view of FIG. 8 taken along the direction A-A (first direction);

FIG. 10 is a cross-sectional view of FIG. 8 taken along the direction B-B (second direction);

FIG. 11 is a schematic diagram of filling a second groove with a conductive layer according to an embodiment of the present invention;

FIG. 12 is a cross-sectional view of FIG. 11 taken along the direction A-A (first direction);

FIG. 13 is a cross-sectional view of FIG. 11 taken along the B-B direction (second direction);

FIG. 14 is a schematic view of removing a sacrificial layer to form a trench according to an embodiment of the invention;

FIG. 15 is a cross-sectional view taken along the direction A-A (first direction) of FIG. 14;

FIG. 16 is a cross-sectional view of FIG. 14 taken along the direction B-B (second direction);

FIG. 17 is a cross-sectional view in the A-A direction (first direction) of a mask layer formed on a substrate after filling a conductor layer in a second recess in accordance with one embodiment of the present invention;

FIG. 18 is a cross-sectional view in the B-B direction (second direction) of a mask layer formed on a substrate after filling a conductor layer in a second recess in accordance with one embodiment of the present invention;

FIG. 19 is a cross-sectional view in the A-A direction (first direction) after forming a trench in an embodiment of the present invention;

FIG. 20 is a cross-sectional view in the B-B direction (second direction) after forming a trench in an embodiment of the invention;

FIG. 21 is a cross-sectional view in the A-A direction of a conductive post core formed in accordance with one embodiment of the present invention;

FIG. 22 is a flowchart of step S5 according to an embodiment of the present invention;

FIG. 23 is a cross-sectional view of A-A direction (first direction) of a dielectric layer and a conductive layer formed sequentially on the surfaces of a trench and a conductive pillar in accordance with an embodiment of the present invention;

FIG. 24 is a flowchart of step S6 according to an embodiment of the present invention;

fig. 25 is a B-B direction (second direction) cross-sectional view of a first conductive structure formed on a substrate in accordance with an embodiment of the present invention.

Description of element reference numerals

100. A substrate; 110. a mask layer; 111. an opening; 112. a through hole; 200. a groove; 210. a first groove; 211. a sacrificial layer; 220. a second groove; 221. a conductor layer; 230. a step; 300. a conductive pillar core; 400. a dielectric layer; 410. a cylindrical dielectric layer; 420. a slot surface dielectric layer; 500. a conductive layer; 510. a diffusion barrier layer; 520. a seed layer; 530. a metal layer; 700. a first conductive structure; 710. a diffusion barrier layer; 720. a seed layer; 730. a metal layer; 800. and a second conductive structure.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

In the present application, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.

In integrated circuits, capacitance is an important electronic component used for energy storage, filtering, and the like. With the continuous development of integrated circuit technology, the requirements of integrated circuit on integration level and performance become higher and higher, and to meet the requirements of high performance and integration level, the stacked capacitor (Stacked Capacitor) is gradually a mainstream capacitor device structure form in the integrated circuit, for example, in a Dynamic Random Access Memory (DRAM), the stacked capacitor can significantly increase the capacitance value of a unit area, and has become one of key technologies for increasing the storage density and reducing the power consumption.

However, applicants have found that existing capacitor structures suffer from significant drawbacks that limit their use in high density integrated circuits. For example, the conventional planar capacitor is composed of opposite planar electrodes, and the planar capacitor has a larger capacitance area, resulting in a smaller capacitance per unit area, which makes it difficult to form a capacitor array with high capacitance density when stacked, and which is prone to generate larger parasitic capacitance, thereby adversely affecting delay, power consumption and reliability of circuit signals. Compared with a planar capacitor, the deep trench capacitor provides higher capacity density and better electric field distribution, but the processing process is complex, the deep trench capacitor is required to be processed and formed by a deep trench process, the process technical requirement is high, an insulating Substrate (SOI) is usually required to realize the deep trench capacitor, the filling difficulty of the deep trench is high, the filling material is easy to accumulate stress in a small-size space, and the reliability of a device is easy to influence; meanwhile, the deep trench capacitor is not easy to vertically stack based on the self structural characteristics, and the manufacturing procedure is difficult to adapt to the back-end process, so that the application of the deep trench capacitor in the prior process integrated circuit is limited.

Based on the above problems, the present invention provides a columnar capacitor and a forming method thereof, the columnar capacitor is arranged in a shallow trench along a horizontal direction, a relative area between two ends of the columnar capacitor is large and has high capacity density, a deep trench is not required to be processed during forming, a process problem caused by processing the deep trench is effectively improved, and the columnar capacitor is integrally arranged in the shallow trench, compared with the existing capacitor, a substrate is not required to be used as a back electrode, a conductive column core and a conductive layer surrounding the outer side of the conductive column core are respectively arranged as two ends of the electrode, so that the columnar capacitor has high integration and easy processing, the forming process can be adapted to a front-stage process and a rear-stage process, and a capacitor array with high capacity and high stability can be easily stacked in a three-dimensional space with high and flat surfaces.

Referring to fig. 1 to 3, the columnar capacitor includes a substrate 100, a conductive pillar core 300, a cylindrical dielectric layer 410, a conductive layer 500, and a first conductive structure 700.

As shown in fig. 1-3, the substrate 100 may be any material that meets the needs of the integrated circuit base, and as an example, the substrate 100 may include any one or more of a semiconductor material, an insulating material, or a combination thereof. When the substrate 100 is made of a semiconductor material, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or other group III/V compound semiconductors may be selected. In addition to the semiconductor materials listed above, the substrate 100 may also be Si/SiGe, si/SiC, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or silicon-germanium-on-insulator (SGOI), among others. When the substrate 100 is selected from an insulating material, the insulating material may be an organic insulator, an inorganic insulator, or a combination thereof. The present application is described in detail with reference to substrate 100 as a semiconductor substrate upon which one or more semiconductor devices, such as transistors, memories, sensors, etc., may be fabricated.

As shown in fig. 1 to 3, a conductive post 300 is provided in a substrate 100, the conductive post 300 extends in a horizontal direction in the substrate 100, and the conductive post 300 is made of a conductive material.

The cylindrical dielectric layer 410 circumferentially coats the surface of the conductive pillar core 300 and exposes a portion of the surface of the conductive pillar core 300, for example, the cylindrical dielectric layer 410 circumferentially coats the cylindrical surface of the conductive pillar core 300 and exposes a surface of at least one end of the conductive pillar core 300 upward. The cylindrical dielectric layer 410 may employ at least one dielectric material, including an inorganic dielectric material or an organic dielectric material. In some embodiments, the dielectric material used for the cylindrical dielectric layer 410 includes, but is not limited to, silicon oxide (SiO ₂), silicon nitride (SiN), silsesquioxane hydrogen polymer (HSQ), silsesquioxane methane polymer (MSQ), methyl silicate compound, carbon doped oxide, and the like.

The conductive layer 500 is disposed in the substrate 100, the conductive layer 500 is filled between the conductive pillar core 300 and the substrate 100, and the conductive layer 500 is circumferentially wrapped around the cylindrical dielectric layer 410. In the substrate 100, the conductive pillar core 300, the cylindrical dielectric layer 410 and the conductive layer 500 cooperate to form a columnar capacitor structure, and the conductive layer 500 and the conductive pillar core 300 serve as two end electrodes of the capacitor structure, are oppositely arranged along the circumferential cylindrical surface, and are insulated and isolated by the cylindrical dielectric layer 410. The top of the conductive layer 500 may be higher than the surface of the substrate 100, and the top of the conductive layer 500 may be lower than or flush with the surface of the substrate 100, so as to facilitate the processing of the subsequent structure.

The first conductive structure 700 is disposed on the substrate 100, and the first conductive structure 700 extends into the substrate 100 and is in conductive contact with a portion of the surface of the conductive pillar 300 that is exposed without being covered by the cylindrical dielectric layer 410. The first conductive structure 700 is electrically connected to the conductive stud core 300 and is insulated from the conductive layer 500. The first conductive structure 700 conductively connects the conductive post 300 with external circuitry on the substrate 100 for directing external power to the conductive post 300.

As shown in fig. 1, in some embodiments, the columnar capacitor further includes a second conductive structure 800, the second conductive structure 800 being in conductive connection with the conductive layer 500, the second conductive structure 800 being for conductive connection of the conductive layer 500 with external circuitry on the substrate 100. In an example, the second conductive structure 800 is disposed on the surface of the conductive layer 500, and the second conductive structure 800 is in conductive contact with the conductive layer 500.

As shown in fig. 2 and 3, in some embodiments, the substrate 100 has a trench 200 thereon, the trench 200 has a width and a depth that are larger than the outer diameter of the conductive post 300 in the circumferential section, both ends of the trench 200 have steps 230, the side walls of the steps 230 meet the bottom wall of the trench 200, and the top surface of the steps 230 is higher than the bottom wall of the trench 200. The conductive pillar core 300 is disposed in the trench 200, both ends of the conductive pillar core 300 are respectively located on the steps 230 at both ends of the trench 200, the conductive pillar core 300 is fixed in the trench 200 with the support of the steps 230 at both ends, and the bottom surface is higher than the bottom wall of the trench 200. The middle part between the two ends of the conductive column core 300 is suspended in the groove 200, the middle part of the conductive column core 300 is not contacted with the side wall and the bottom wall of the groove 200, and a gap exists between the column surface of the middle part of the conductive column core 300 and the groove 200 in the manufacturing process, so that necessary space is provided for surrounding the conductive column core 300 in the groove 200 along the circumferential direction by the cylindrical medium layer 410 and the conductive layer 500. In the preparation process, a dielectric layer 400 is formed on the inner wall (bottom wall and side wall) of the trench 200 and the surface of the conductive pillar 300, the dielectric layer 400 includes a cylindrical dielectric layer 410 located on the surface of the conductive pillar 300 and a groove-surface dielectric layer 420 located on the inner wall surface of the trench 200, and the cylindrical dielectric layer 410 circumferentially coats the surface of the conductive pillar 300, and does not coat a part of the surface of at least one end of the conductive pillar 300, so that a part of the surface of at least one end of the conductive pillar 300 is exposed upward. The conductive layer 500 is filled in the trench 200, the conductive layer 500 is disposed on the dielectric layer 400, and the conductive layer 500 located outside the cylindrical dielectric layer 410 is disposed around the circumferential periphery of the conductive stud core 300. This causes conductive layer 500 to be disposed circumferentially opposite conductive post 300 and to be insulated therefrom by cylindrical dielectric layer 410, thereby forming a columnar capacitance.

The columnar capacitor structure formed by the conductive pillar core 300, the cylindrical dielectric layer 410 and the conductive layer 500 extends in the horizontal direction on the substrate 100, so that the deep trench 200 is not required to be processed when the columnar capacitor is formed on the substrate 100, and the columnar capacitor can be continuously formed in the trench 200 only by processing the shallow trench 200. This effectively reduces the difficulty of filling material in the trench 200 when forming the capacitor and improves the problem of the filling material in the trench 200 being prone to build up stress. In addition, based on the structural features of the columnar cells extending along the horizontal direction and the processing mode in the shallow grooves 200 on the surface of the substrate 100, the columnar cells with high capacity are easy to stack in a three-dimensional space with high capacity and high stability, and the formation process of the columnar cells can be adapted to the front-end process and the back-end process.

As shown in fig. 2 and 3, in some embodiments, the substrate 100 includes a mask layer 110, where the mask layer 110 is disposed on top of the substrate 100, and the mask layer 110 covers at least the trench 200 and two axial ends of the conductive stud 300, and the mask layer 110 has an opening 111 thereon, where the opening 111 is integrally connected to the trench 200, and the surface of the trench 200 and the surface of the conductive stud 300 between the two axial ends of the conductive stud 300 are exposed by the opening 111. The mask layer 110 has a through hole 112 thereon, the through hole 112 is located above the end of the conductive pillar core 300, and the through hole 112 penetrates through the mask layer 110 in the height direction so that a part of the surface of the end of the conductive pillar core 300 is exposed upward. The first conductive structure 700 is disposed on the mask layer 110, and the first conductive structure 700 extends from the surface of the mask layer 110 to the inside of the mask layer 110 through the via 112 and is in conductive contact with the end of the conductive stud core 300 through the via 112.

The mask layer 110 may be made of the same material as the substrate 100, such as any one or more of semiconductor material and insulating material. When the mask layer 110 is made of a semiconductor material, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or other group III/V compound semiconductors may be used. In addition to the semiconductor materials listed above, the mask layer 110 may also be Si/SiGe, si/SiC, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or silicon-germanium-on-insulator (SGOI), among others. When the mask layer 110 is made of an insulating material, the insulating material may be an organic insulator, an inorganic insulator, or a combination thereof.

As shown in fig. 1 to 3, in some embodiments, the first conductive structure 700 includes a diffusion barrier 710, a seed layer 720, and a metal layer 730 disposed in order from bottom to top. In an example, the diffusion barrier 710 is disposed on the inner wall (bottom wall and side wall) of the via 112 and the surface of the conductive stud core 300 exposed by the via 112, the diffusion barrier 710 may prevent metal ions from diffusing to the surroundings to improve reliability and electromigration characteristics, and the diffusion barrier 710 may also increase adhesion between the metal layer 730 and the substrate 100, enhancing mechanical stability of the structure. The material of the diffusion barrier layer 710 may be, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), silicon carbide (SiC), nitrogen doped silicon carbide (NDC), or any combination thereof, and may also be a cobalt (Co) based alloy, such as Co-Ti, co-W, co-Mo, or Co-Ta, etc. The seed layer 720 is disposed over the diffusion barrier 710, and the seed layer 720 is used to provide a conductive substrate to facilitate the subsequent electroplating of the metal layer 730 and to ensure good adhesion between the metal layer 730 and the underlying structure. The seed layer 720 may be selected from copper (Cu), titanium (Ti), chromium (Cr), cobalt (Co), ruthenium (Ru), or an alloy of any two or more, for example. A metal layer 730 is disposed over the seed layer 720 and fills the via 112. The metal material of the metal layer 730 may be selected from aluminum (Al), copper (Cu), tungsten (W) silver (Ag), cobalt (Co), ruthenium (Ru) or an alloy of any two or more, such as copper-aluminum alloy, or the like having a low resistivity, and optionally, the metal is selected from copper.

As shown in fig. 1 to 3, in some embodiments, the conductive layer 500 includes a diffusion barrier layer 510, a seed layer 520, and a metal layer 530 sequentially disposed from bottom to top, as in the first conductive structure 700. In an example, the diffusion barrier layer 510 is disposed on the dielectric layer 400, and the diffusion barrier layer 510 can prevent metal ions from diffusing to the surrounding to improve reliability and electromigration characteristics, and the diffusion barrier layer 510 can also increase adhesion between the metal layer 530 and the dielectric layer 400, enhancing mechanical stability of the structure. The seed layer 520 is disposed over the diffusion barrier layer 510, and the seed layer 520 is used to provide a conductive substrate to facilitate the subsequent electroplating process of the metal layer 530 and to ensure good adhesion between the metal layer 530 and the underlying structure. A metal layer 530 is disposed over the seed layer 520 and fills the trench 200. Note that the types of materials selected for the diffusion barrier layer 510, the seed layer 520, and the metal layer 530 in the conductive layer 500 are similar to those of the first conductive structure 700, and will not be described herein.

As shown in fig. 1 to 3, in some embodiments, the conductive pillar core 300 is made of silicon germanium or silicon carbide, for example, silicon germanium material doped with elements such as aluminum (Al), manganese (Mn), gallium (Ga), boron (B), and phosphorus (P), and silicon carbide material doped with elements such as aluminum (Al), manganese (Mn), boron (B), nitrogen (N), and phosphorus (P). The silicon germanium or silicon carbide has good interface compatibility with the material of the common substrate 100 (such as silicon material), and the silicon germanium or silicon carbide is selected as the material of the conductive pillar core 300, so that the stress and defects at the interface between the conductive pillar core 300 and the substrate 100 can be reduced, and the interface stability between the conductive pillar core 300 and the substrate 100 can be improved. In addition, silicon germanium or silicon carbide is used as the material of the conductive pillar core 300, and the electrode resistance (Rs) of the capacitor can be reduced by doping modification, so that the response speed of the capacitor is improved.

Referring to fig. 4, the present invention further provides a method for forming a columnar capacitor, which at least includes the following steps:

S1, providing a substrate 100;

S2, forming a groove 200 on the substrate 100, and forming a conductor layer 221 in the groove 200, wherein the width of the formed conductor layer 221 is smaller than the width of the groove 200, and the height of the conductor layer 221 is smaller than the depth of the groove 200; steps 230 are arranged at two ends of the groove 200, the steps 230 at two ends of the groove 200 support the conductor layer 221, so that the conductor layer 221 is suspended in the groove 200, and a gap is reserved between the middle part between the two ends of the conductor layer 221 and the side wall and the bottom wall of the groove 200;

s3, rounding the surface angle of the conductor layer 221 to form a conductive pillar core 300;

S4, forming a dielectric layer 400 on the surfaces of the groove 200 and the conductive column core 300; the dielectric layer 400 includes a cylindrical dielectric layer 410 located on the conductive pillar core surface 300 and a groove-surface dielectric layer 420 located on the inner wall surface of the groove 200;

s5, forming a conductive layer 500 in the groove 200, so that the conductive layer 500 circumferentially surrounds the cylindrical dielectric layer 410;

and S6, forming a first conductive structure 700 above the conductive plunger 300, wherein the first conductive structure 700 is in conductive connection with the conductive plunger 300 and is insulated from the conductive layer 500.

As shown in fig. 5, in some embodiments, in step S1, the substrate 100 may be provided as any material that meets the requirements of the integrated circuit base, and as an example, the substrate 100 includes any one or more of a semiconductor material and an insulating material. When the substrate 100 is made of a semiconductor material, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or other group III/V compound semiconductors may be selected. In addition to the semiconductor materials listed above, the substrate 100 may also be Si/SiGe, si/SiC, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or silicon-germanium-on-insulator (SGOI), among others. When the substrate 100 is selected from an insulating material, the insulating material may be an organic insulator, an inorganic insulator, or a combination thereof. The present application is described in detail with reference to substrate 100 as a semiconductor substrate upon which one or more semiconductor devices, such as transistors, memories, sensors, etc., may be fabricated.

As shown in fig. 6, in some embodiments, step S2 includes the steps of:

S21, forming a first groove 210 on the substrate 100, wherein the first groove 210 extends along a first direction;

As shown in fig. 7, in step S21, a first groove 210 may be etched in a preset area on the substrate 100, and a groove body etched to form the first groove 210 extends along a first direction, where the first direction is parallel to the surface of the substrate 100. For example, in one example, a photoresist is coated on the surface of the substrate 100 to form a photoresist layer; exposing and developing the photoresist layer to form a photoresist layer with an etching window; the window-exposed substrate 100 (i.e., the substrate 100 not covered by the patterned photoresist) is etched using an etching process, such as Reactive Ion Etching (RIE), with the patterned photoresist layer as a mask, and the photoresist is removed after etching using a conventional ashing or stripping process such that the first recess 210 is formed in the substrate 100.

S22, filling and forming a sacrificial layer 211 in the first groove 210;

As shown in fig. 7, in step S22, the sacrificial layer 211 is filled in the first recess 210, and for example, any suitable Deposition process, such as chemical Vapor Deposition (Chemical Vapor Deposition, CVD), physical Vapor Deposition (Physical Vapor Deposition, PVD), plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition, PECVD), atomic layer Deposition (Atomic layer Deposition, ALD), etc., may be used to fill the sacrificial layer 211 in the first recess 210. Step S22 further includes removing the sacrificial layer 211 higher than the surface of the first recess 210 so that the sacrificial layer 211 is flush with the surface of the substrate 100, for example, polishing the surface of the substrate 100 using a chemical mechanical polishing (CHEMICAL MECHANICAL plane) process so that the sacrificial layer 211 is flush with the surface of the substrate 100.

S23, forming a second groove 220 on the substrate 100 and the sacrificial layer 211; the second groove 220 is used for positioning the conductive post 300, and primarily defines the outer diameter of the conductive post 300.

As shown in fig. 8 to 10, in step S23, a second groove 220 is formed to extend in a second direction on the surface of the substrate 100, the second groove 220 partially overlaps with the first groove 210, the second groove 220 is embedded in the first groove 210 in the depth direction, the width of the second groove 220 in the first direction is smaller than the width of the first groove 210, the side walls of the second groove 220 on both sides in the first direction are spaced apart from the side walls of the first groove 210 by the sacrificial layer 211, the length of the second groove 220 in the second direction is longer than the length of the first groove 210, and the two end bodies of the second groove 220 in the second direction extend to the outside of the first groove 210; and, the depth of the second groove 220 is lower than that of the first groove 210, and the end groove body of the second groove 220 in the second direction cooperates with the bottom wall and the side wall of the first groove 210 which meet to form a step 230 structure.

As shown in fig. 8 to 10, in step S23, a predetermined region of the surfaces of the substrate 100 and the sacrificial layer 211 is etched by a conventional photolithography means to form a second groove 220 on the substrate 100; for example, in one example, photoresist is coated on the surfaces of the substrate 100 and the sacrificial layer 211 to form a photoresist layer; exposing and developing the photoresist layer to form an etching window at a preset position of the photoresist layer, wherein the etching window is arranged in an extending manner along the second direction; the substrate 100 and the sacrificial layer 211 exposed by the etching window are removed using an etching process, such as Reactive Ion Etching (RIE), using the patterned photoresist layer as a mask, and the photoresist is removed after etching using a conventional ashing or stripping process, thereby forming the second recess 220.

S24, filling and forming a conductor layer 221 in the second groove 220; as shown in fig. 11 to 13, since both end grooves of the second groove 220 in the second direction extend to the outside of the first groove 210 and the depth of the second groove 220 is smaller than that of the first groove 210, both ends of the conductor layer 221 are placed in the grooves at both ends of the second groove 220, and the middle portion of the conductor layer 221 located between both ends is circumferentially supported by at least three sides (bottom surface and both side surfaces) of the sacrificial layer 211. The height of the conductor layer 221 is higher than the bottom wall height of the first recess 210 under the surrounding support of the sacrificial layer 211.

As shown in fig. 11 to 13, in step S24, the second groove 220 is filled with the conductor layer 221, and for example, the second groove 220 may be filled with the conductor layer 221 by using any suitable deposition process, such as CVD, PVD, PECVD, ALD. In addition, in an example, step S24 further includes removing the conductor layer 221 higher than the surface of the second groove 220 so that the conductor layer 221 is flush with the surface of the substrate 100, for example, polishing the surface of the substrate 100 using a CMP process so that the conductor layer 221 is flush with the surface of the substrate 100.

It should be noted that, any conductive material may be used as the material of the conductive layer 221, and in an embodiment, the conductive layer 221 may be made of silicon germanium or silicon carbide having conductivity, for example, silicon germanium material doped with elements such as aluminum (Al), manganese (Mn), gallium (Ga), boron (B), and phosphorus (P), and silicon carbide material doped with elements such as aluminum (Al), manganese (Mn), boron (B), nitrogen (N), and phosphorus (P).

S25, removing the sacrificial layer 211 in the first groove 210, so that the second groove 220 and the first groove 210 are communicated to form a groove 200.

As shown in fig. 14 to 16, in step S25, a selective etching process (such as wet etching) is used to remove the sacrificial layer 211 in the first recess 210, so that the second recess 220 and the first recess 210 communicate to form the trench 200, and the conductor layer 221 remains in the trench 200. The groove bodies at two ends of the second groove 220 in the second direction are connected with the first groove 210 to form a step 230, the top surface of the step 230 is higher than the bottom wall of the groove 200, two ends of the conductor layer 221 are respectively positioned on the steps 230 at two ends of the groove 200, the conductor layer 221 is fixed in the groove 200 under the support of the steps 230 at two ends, the middle part between the two ends of the conductor layer 221 is suspended in the groove 200, the middle part of the conductor layer 221 is not contacted with the side wall and the bottom wall of the groove 200, and a gap exists between the cylinder surface of the middle part of the conductor layer 221 and the groove 200.

The material of the sacrificial layer 211 is a material that can be selectively etched away relative to the material of the conductive layer 221 and the substrate 100, and in one example, the material of the substrate 100 is Si, the material of the conductive layer 221 is SiGe, and the material of the sacrificial layer 211 is SiN.

In addition, referring to fig. 17 to 20, in some embodiments, during the forming process of the trench 200 in step S2, further includes: forming a mask layer 110 on the substrate 100 through a deposition process so as to insulate the first conductive structure 700 and the conductive layer 500 formed by a subsequent process; an opening 111 is formed on the mask layer 110 by a photolithography process, the mask layer 110 covers at least two ends of the conductor layer 221, and a part of the surface of the trench 200 is exposed through the opening 111, so that the sacrificial layer 211 in the first groove 210 is removed by subsequent wet etching.

As shown in fig. 17 to 20, in an example, after filling the second groove 220 with the conductor layer 221 in step S24, the method further includes: a mask layer 110 is formed on the substrate 100, the conductor layer 221 and the sacrificial layer 211 by a deposition process, and an opening 111 is formed on the mask layer 110 by a photolithography process, so that the mask layer 110 covers at least two ends of the conductor layer 221 and exposes a portion of the surface of the trench 200 through the opening 111, so that the sacrificial layer 211 in the first recess 210 is removed by subsequent wet etching. Wherein, after the sacrificial layer 211 is removed, the opening 111 on the mask layer 110 communicates with the first recess 210 and the second recess 220 to form the trench 200.

Referring to fig. 21, in some embodiments, in step S3, a thermal oxidation process is used to perform oxidation treatment on the exposed surfaces of the trench 200 and the conductor layer 221 for several times, so that the exposed surfaces of the trench 200 and the conductor layer 221 form an oxide layer; after each oxidation treatment, the oxide layer formed on the surfaces of the trench 200 and the conductor layer 221 is removed by wet etching, so that corners of the trench 200 and corners of the surface of the conductor layer 221 are rounded, thereby causing the conductor layer 221 to become a conductive pillar core 300 in a cylindrical or elliptic cylindrical shape.

Referring to fig. 23, in step S4, a dielectric layer 400 is formed on the surfaces of the trench 200 and the conductive post 300, and the dielectric layer 400 includes a cylindrical dielectric layer 410 on the conductive post 300 and a trench surface dielectric layer 420 on the inner wall surface of the trench 200. Specifically, an inter-layer dielectric layer (INTERLAYER DIELECTRIC, ILD) is formed sequentially over the exposed trench 200 and conductive post 300 surfaces by CVD, ALD, PVD or other suitable deposition process; forming a high-dielectric-constant dielectric layer on the surface of the inner-layer dielectric layer, wherein the dielectric constant of the high-dielectric-constant dielectric layer is at least higher than that of the inner-layer dielectric layer, and the high-dielectric-constant dielectric layer can provide better electrical insulation performance and is beneficial to reducing leakage current of a device; a barrier layer is formed on the surface of the high-k dielectric layer, and is used to protect the surface of the dielectric layer 400 and prevent metal ions from diffusing into the dielectric layer 400.

Wherein, the dielectric material of the inner dielectric layer is at least one of silicon oxide (SiO ₂), silicon nitride (Si ₃N₄) and silicon oxynitride (SiON _x); for example, in one embodiment, the interlayer dielectric layer is formed of SiO ₂. The high-k dielectric layer is formed of a dielectric material having a high dielectric constant, exemplary high-k dielectric materials for the high-k dielectric layer include hafnium oxide (HfO), titanium oxide (TiO ₂), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta ₂O₅), hafnium silicate (HfSiO ₄), a metal oxide (ti) and a metal oxide (ti) oxide, Zirconia (ZrO ₂), zirconium silicate (ZrSiO ₂), lanthanum oxide (La ₂O₃), alumina (Al ₂O₃), Zirconium oxide (ZrO), yttrium oxide (Y ₂O₃), strontium titanate (SrTiO ₃, TO), barium titanate (BaTiO ₃, BTO), barium zirconium oxide (BaZrO), lanthanum hafnium oxide (HfLaO), Lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium strontium titanate ((Ba, sr) TiO ₃; BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. In one embodiment, the high-k dielectric layer is formed of HfO. The barrier layer may be titanium nitride (TiN) or tantalum nitride (TaN).

Referring to fig. 22 and 23, in some embodiments, step S5 includes the steps of:

s51, forming a diffusion barrier layer 510 on the dielectric layer 400;

In step S51, the diffusion barrier layer 510 is used to prevent diffusion of metal ions into the surrounding dielectric layer 400, thereby improving reliability and electromigration characteristics. The material of the diffusion barrier layer 510 may be, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or any combination thereof, and may also be a cobalt (Co) based alloy, such as a conductive material of Co-Ti, co-W, co-Mo, or Co-Ta. The diffusion barrier 510 may be formed by a deposition process such as PVD, CVD, or ALD, or a sputtering process.

S52, forming a seed layer 520 on the diffusion barrier layer 510;

In step S52, the seed layer 520 may provide a conductive substrate to facilitate the electroplating process of the subsequent metal layer 530, and ensure good adhesion between the metal layer 530 and the underlying structure. The seed layer 520 may be selected from copper (Cu), titanium (Ti), chromium (Cr), cobalt (Co), ruthenium (Ru), or an alloy thereof. Optionally, the seed layer 520 is made of copper metal. The seed layer 520 may be formed by a sputtering or deposition process, such as CVD, PVD, ALD a.

S53, forming a metal layer 530 on the seed layer 520, such that the metal layer 530 fills the trench 200 to form a conductive layer 500 surrounding the conductive post 300 in the trench 200.

In step S53, a metal material is formed on the seed layer 520 by an electrochemical plating process, such that the metal material fills the trench 200 to form a metal layer 530 in communication with the periphery of the conductive pillar core 300. Wherein the metal layer 530 is selected from aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru) or an alloy of any two or more, such as an aluminum copper alloy or the like, having a conductive material with a relatively low resistivity, optionally the metal layer 530 is selected from copper.

Referring to fig. 24 and 25, in some embodiments, step S6 includes the steps of:

S61, forming a through hole 112 on the mask layer 110, wherein the through hole 112 exposes a part of the surface of the end of the conductive post 300;

s62, filling the through hole 112 to form a first conductive structure 700, where the first conductive structure 700 is electrically connected to the exposed surface of the conductive pillar core 300. For example, in one example, specifically, a diffusion barrier layer 710 is formed on an inner wall of the via 112 and an exposed surface of the conductive stud core 300, a seed layer 720 is formed on the diffusion barrier layer 710, and a metal layer 730 is formed on the seed layer 720 such that the metal layer 730 fills the via 112, thereby completing the formation of the first conductive structure 700 on the substrate 100. Note that the types of materials selected for the diffusion barrier layer 710, the seed layer 720, and the metal layer 730 in the first conductive structure 700 are similar to those in the conductive layer 500, and will not be described herein.

In addition, referring to fig. 25, in some embodiments, the method of forming a columnar capacitor further includes forming a second conductive structure 800 on the conductive layer 221 in step S6.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A columnar capacitor, comprising:

A substrate;

a conductive pillar core disposed in the substrate, the conductive pillar core extending in a horizontal direction;

The cylindrical medium layer circumferentially coats the surface of the conductive column core and exposes part of the surface of the conductive column core;

the conductive layer is arranged between the conductive column core and the substrate, and the conductive layer is coated on the periphery of the cylindrical dielectric layer along the circumferential direction;

a first conductive structure in conductive contact with the exposed surface of the conductive stud core and insulated from the conductive layer;

the substrate is provided with a groove, the conductive column core is positioned in the groove, steps are arranged at two ends of the groove, two ends of the conductive column core are arranged on the steps, and the bottom of the conductive column core is higher than the bottom wall of the groove.

2. The columnar capacitor of claim 1 wherein the first conductive structure is disposed on the substrate and has a via therein exposing a portion of the surface of the conductive stud core end, the first conductive structure being in conductive contact with the exposed surface of the conductive stud core through the via.

3. The columnar capacitor of claim 1 wherein the conductive columnar core is made of silicon germanium or silicon carbide having conductivity.

4. The columnar capacitor according to claim 1, wherein, the columnar capacitor further comprises a second conductive structure, and the second conductive structure is arranged on the conductive layer.

5. A method of forming a columnar capacitor, comprising:

Providing a substrate;

Forming a trench on the substrate, and forming a conductor layer in the trench; steps are arranged at two ends of the groove, and the steps at two ends of the groove support the conductor layer so that gaps are reserved between part of the conductor layer and the side wall and the bottom wall of the groove;

6. The forming method according to claim 5, wherein a mask layer is formed over the substrate and an opening is formed over the mask layer in the trench forming process; the mask layer at least covers two ends of the conductor layer, and exposes part of the surface of the groove through the opening.

7. The forming method according to claim 5, wherein forming a trench over the substrate and forming a conductor layer in the trench, comprises:

forming a first groove on the substrate, wherein the first groove extends along a first direction;

filling and forming a sacrificial layer in the first groove;

forming a second groove on the substrate and the sacrificial layer, wherein an end part of the second groove in a second direction extends out of the first groove, and the depth of the second groove is lower than that of the first groove;

filling and forming a conductor layer in the second groove;

Removing the sacrificial layer in the first groove, so that the second groove is communicated with the first groove to form a groove; the junction of the second groove and the first groove forms a step so as to support the conductor layer at two ends.

8. The method of forming of claim 7, further comprising, after filling the second recess with the conductor layer:

forming a mask layer on the substrate, the conductor layer and the sacrificial layer, and forming an opening on the mask layer, wherein the opening at least exposes the surface of the sacrificial layer;

Wherein, after the sacrificial layer is removed, the opening communicates with the first groove and the second groove to form the trench.

9. The forming method according to claim 6 or 8, characterized in that forming a first conductive structure over the conductive pillar core, comprises:

forming a through hole on the mask layer, wherein the through hole exposes a part of the surface of the end part of the conductive post core;

And filling the through holes to form first conductive structures, wherein the first conductive structures are in conductive interconnection with the exposed surfaces of the conductive column cores.