CN118655948A - Fast dynamic bias circuit based on capacitive coupling - Google Patents

Abstract

The invention relates to the field of bias circuits, in particular to a fast dynamic bias circuit based on capacitive coupling. The scheme comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a coupling capacitor, wherein the drain electrode of the first MOS tube is connected with a grid electrode, externally applied bias current is loaded on the drain electrode of the first MOS tube, the source electrode of the first MOS tube is grounded, the grid electrode of the first MOS tube is connected with the source electrode of the fifth MOS tube, the grid electrode of the first MOS tube is grounded through the decoupling capacitor, the grid electrode of the fifth MOS tube is connected with the grid electrode of the second MOS tube through the coupling capacitor, the drain electrode of the fifth MOS tube is connected with the grid electrode of the second MOS tube, an external clock is loaded on the grid electrode of the fifth MOS tube and the coupling capacitor controls the switch of the fifth MOS tube, the source electrode of the second MOS tube is grounded, and the drain electrode of the second MOS tube is connected with an amplifier differential input pair tube formed by the third MOS tube and the fourth MOS tube.

Description

Fast dynamic bias circuit based on capacitive coupling

Technical Field

The invention relates to the field of bias circuits, and in particular to a fast dynamic bias circuit based on capacitive coupling.

Background Art

In some circuits controlled by two-phase clocks, such as switched capacitor circuits, the circuit is usually held in one of the clock phases and works in the other clock phase. Typical switched capacitor circuits include stage circuits in pipeline analog-to-digital converters. The stage circuits in the analog-to-digital converter include modules such as comparators and amplifiers, where both the comparator and the amplifier work periodically, one of the phases is the holding phase, and the other phase processes the signal, i.e., the amplification phase. In the holding phase, the circuit does not work. In order to achieve low power consumption, it is possible to consider using dynamic biasing technology to periodically turn the circuit on and off, turning it on when working and turning it off when holding the phase to save power consumption. Dynamic biasing technology usually needs to consider the recovery speed of the circuit from off to on and the cost of dynamically biasing the circuit itself.

Existing dynamic bias circuits, such as a dynamic bias LDO circuit disclosed in CN106249794A, use capacitor coupling to sample the transient change of the output voltage, and generate two dynamic bias signals by comparing with the fixed bias voltage. The dynamic bias signal opens or closes the charging and discharging loop of the parasitic capacitance at the gate end of the power tube according to the change of the output voltage, thereby adjusting the gate end voltage of the power tube and stabilizing the output voltage.

The circuit for generating fixed bias voltages Vb1 and Vb2 in this scheme includes a reference voltage Vref, an amplifier OP1, transistors M1 to M4, and a resistor Rs. The dynamic bias circuit includes resistors R1 and R2, capacitors C1 and C2, and amplifiers OP2 and OP3, which are used to generate superimposed signals Vb3 and Vb4 of dynamic bias and fixed bias; Vb3 controls the gate voltage of transistors M6 and M7, and Vb4 controls the gate voltage of transistors M5 and M8. However, its structure is complex. When the dynamic bias is adjusted, it is necessary to control the conductivity of transistors M6 and M7 or the conductivity of transistors M5 and M8 respectively. When the transistor is turned on, there will be a turn-on voltage, which will occupy a certain voltage margin and reduce the overall dynamic range of the amplifier.

Summary of the invention

The purpose of the present invention is to overcome the shortcomings of the prior art and provide a fast dynamic bias circuit based on capacitor coupling. The present invention has a simple structure and does not require a switch MOS tube to be connected in series under the bias tube, thereby eliminating the voltage loss caused by the conduction of the switch tube and expanding the dynamic range of the operational amplifier.

The present invention adopts the following technical scheme to achieve the above-mentioned purpose. The present invention provides a fast dynamic bias circuit based on capacitor coupling, including a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube Msw, a decoupling capacitor Cd and a coupling capacitor Cc. The drain of the first MOS tube M1 is connected to the gate, an external bias current IB is loaded on the drain of the first MOS tube M1, the source of the first MOS tube M1 is grounded to VSS, the gate of the first MOS tube M1 is connected to the source of the fifth MOS tube Msw, and the gate of the first MOS tube M1 is connected to the gate of the fifth MOS tube Msw. The decoupling capacitor Cd is also connected to the ground VSS, the gate of the fifth MOS tube Msw is connected to the gate of the second MOS tube M2 through the coupling capacitor Cc, the drain of the fifth MOS tube Msw is connected to the gate of the second MOS tube M2, the external clock ck is loaded to the gate of the fifth MOS tube Msw and the coupling capacitor Cc to control the switch of the fifth MOS tube Msw, the source of the second MOS tube M2 is connected to the ground VSS, the drain of the second MOS tube M2 is connected to the differential input pair of the amplifier composed of the third MOS tube M3 and the fourth MOS tube M4; the decoupling capacitor Cd suppresses the jitter of the bias voltage.

When the external clock ck is at a high level, the fifth MOS tube Msw is turned on, and the gate voltage Vg of the second MOS tube M2 is equal to the bias voltage VB, then the second MOS tube M2 generates a bias current to provide the differential input pair of the amplifier with the required bias for operation;

When the external clock ck changes from a high level to a low level, the fifth MOS transistor Msw is turned off, the gate voltage Vg of the second MOS transistor M2 is disconnected from the bias voltage VB, and the external clock ck pulls down the gate voltage Vg of the second MOS transistor M2 through the coupling capacitor Cc. The magnitude of the pull-down depends on the ratio of the coupling capacitor Cc to the gate capacitance of the second MOS transistor M2, and the bias current of the second MOS transistor M2 is turned off.

The beneficial effects of the present invention are:

The present invention does not need to connect a switch MOS tube in series under the bias tube M2, thereby eliminating the voltage loss caused by the switch tube conduction voltage and expanding the dynamic range of the operational amplifier. At the same time, the fifth MOS tube Msw of the present invention can be designed to be very small, reducing the load of ck and reducing the impact caused by the switch opening and closing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a structural diagram of a fast dynamic bias circuit based on capacitive coupling provided by an embodiment of the present invention.

DETAILED DESCRIPTION

To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention.

The invention provides a fast dynamic bias circuit based on capacitor coupling. The circuit only uses a group of capacitors and MOS switches and can realize the switching of the circuit dynamic bias under the control of a clock.

Specifically, as shown in FIG. 1 , a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube Msw, a decoupling capacitor Cd and a coupling capacitor Cc are included. The drain of the first MOS tube M1 is connected to the gate, and an external bias current IB is loaded on the drain of the first MOS tube M1. The source of the first MOS tube M1 is grounded to VSS, and the gate of the first MOS tube M1 is connected to the source of the fifth MOS tube Msw. The gate of the first MOS tube M1 is also grounded to VSS through the decoupling capacitor Cd. The fifth MOS tube M The gate of the fifth MOS tube Msw is connected to the gate of the second MOS tube M2 through the coupling capacitor Cc, the drain of the fifth MOS tube Msw is connected to the gate of the second MOS tube M2, the external clock ck is loaded to the gate of the fifth MOS tube Msw and the coupling capacitor Cc to control the switch of the fifth MOS tube Msw, the source of the second MOS tube M2 is grounded to VSS, the drain of the second MOS tube M2 is connected to the differential input pair of the amplifier composed of the third MOS tube M3 and the fourth MOS tube M4, IP is the positive input terminal of the differential input pair, and IN is the negative input terminal of the differential input pair.

When the control clock ck is at a high level, the fifth MOS transistor Msw is turned on, the gate voltage Vg of the second MOS transistor M2 is equal to the bias voltage VB, and the second MOS transistor M2 generates a bias current to provide the differential input pair of the amplifier composed of the third MOS transistor M3 and the fourth MOS transistor M4 with the required bias for operation. At this time, the operational amplifier is in an on state;

When ck changes from a high level to a low level, the fifth MOS transistor Msw is turned off, and the gate voltage Vg of the second MOS transistor M2 is disconnected from the bias voltage VB. At this time, the gate voltage Vg node of the second MOS transistor M2 is a high-resistance node. According to the charge conservation principle, ck pulls down the gate voltage Vg of the second MOS transistor M2 through the coupling capacitor Cc. The magnitude of the pull-down depends on the ratio of the coupling capacitor Cc to the gate capacitance of the second MOS transistor M2. However, as long as the magnitude of the pull-down exceeds the overdrive voltage (usually about 200mV) of the normal operation of the second MOS transistor M2, the bias current of the second MOS transistor M2 can be completely turned off. This means that only a smaller coupling capacitor Cc is needed to realize the level shift of the gate voltage Vg node of the second MOS transistor M2, thereby reducing the load of the clock ck. At this time, the operational amplifier enters the off state;

When ck changes from a low level to a high level again, according to the charge conservation principle, the gate voltage Vg of the second MOS tube M2 will quickly and automatically return to the voltage position of the bias voltage VB, realizing the rapid switching of the bias current of the second MOS tube M2, and the operational amplifier re-enters the open state. According to the above process, the bias tube, i.e., the switch of the second MOS tube M2, is mainly driven by the control clock ck. Whenever the gate voltage Vg of the second MOS tube M2 is to be connected to the bias voltage VB, the gate voltage Vg of the second MOS tube M2 has autonomously returned to the position of the bias voltage VB. Therefore, there is no need for the bias voltage VB to drive the second MOS tube M2 to turn on, and the bias voltage VB is almost not impacted. Moreover, the fifth MOS tube Msw is only used to supplement the leakage current of the gate voltage Vg node of the second MOS tube M2, so the fifth MOS tube Msw can be designed to be very small, which also reduces the load of ck and reduces the impact caused by the opening and closing of the switch. Finally, compared with the traditional dynamic bias technology, the circuit proposed by the present invention does not need to connect the switch MOS tube in series under the bias tube M2, so it also eliminates the voltage loss caused by the turn-on voltage of the switch tube, and expands the dynamic range of the operational amplifier.

The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims (2)

1. The fast dynamic bias circuit based on capacitive coupling is characterized by comprising a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a coupling capacitor, wherein the drain electrode of the first MOS tube is connected with a grid electrode, externally applied bias current is loaded on the drain electrode of the first MOS tube, the source electrode of the first MOS tube is grounded, the grid electrode of the first MOS tube is connected with the source electrode of the fifth MOS tube, the grid electrode of the fifth MOS tube is connected with the grid electrode of the second MOS tube through the coupling capacitor, the drain electrode of the fifth MOS tube is connected with the grid electrode of the second MOS tube, an external clock is loaded on the grid electrode of the fifth MOS tube and the coupling capacitor, the switch of the fifth MOS tube is controlled, the source electrode of the second MOS tube is grounded, and the drain electrode of the second MOS tube is connected with a differential input pair tube of an amplifier formed by the third MOS tube and the fourth MOS tube;

When the external clock is at a high level, the fifth MOS tube is conducted, the grid voltage of the second MOS tube is equal to the bias voltage, the second MOS tube generates bias current, and bias needed by work is provided for the differential input pair tube of the amplifier;

When the external clock is changed from high level to low level, the fifth MOS tube is turned off, the grid voltage of the second MOS tube is disconnected with the bias voltage, the external clock pulls down the grid voltage of the second MOS tube through the coupling capacitor, the pulling-down amplitude depends on the ratio of the coupling capacitor to the grid capacitor of the second MOS tube, and then the bias current of the second MOS tube is turned off.

2. The capacitive coupling based fast dynamic bias circuit according to claim 1, further comprising a decoupling capacitor, wherein the gate of the first MOS transistor is further coupled to ground through the decoupling capacitor.