CN118673876B

CN118673876B - A standardized detection method for chip design

Info

Publication number: CN118673876B
Application number: CN202411164521.0A
Authority: CN
Inventors: 谢堃; 王洪鹏; 凌瑜彬
Original assignee: Zhongyin Microelectronics Nanjing Co ltd
Current assignee: Zhongyin Microelectronics Nanjing Co ltd
Priority date: 2024-08-23
Filing date: 2024-08-23
Publication date: 2024-11-12
Anticipated expiration: 2044-08-23
Also published as: CN118673876A

Abstract

The invention provides a normalization detection method aiming at a chip design link, which relates to the technical field of chip design normalization detection, and ensures that P_RING using PSUB2 must be connected to 0V group name or positioned in DNW/NBL area through strict DRC error detection, thereby avoiding the problem of signal clamping caused by misuse of the PSUB 2. The strict detection mode can not only prevent design errors and improve the reliability and accuracy of the design, but also save cost and time, has important educational significance for design teams, and remarkably improves the quality and efficiency of chip design flow.

Description

Normalization detection method for chip design link

Technical Field

The invention relates to the technical field of chip design normalization detection, in particular to a normalization detection method aiming at a chip design link.

Background

In the chip design link, common isolation techniques include real substrate isolation techniques and dummy substrate isolation methods. The actual substrate isolation technology generally adopts a structure with physical changes such as SOI/DNW/NBL, and the false substrate isolation only acts in the LVS link and does not participate in the actual chip logic operation. This technique does not truly isolate the substrate at the physical level.

In the prior art, due to the fact that design engineers and layout engineers are insufficient in understanding basic processes, false substrate isolation can be misused, DRC parts in a process LVS file are only reminded in a warning mode, even errors can not be detected, part of signals are clamped at 0V, basic functions of a chip cannot be verified, labor cost is wasted, research and development period is greatly increased, and the whole project is influenced. Therefore, it is necessary to provide a normalization detection method capable of strictly detecting false substrate isolation from misuse, and a chip design flow.

The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and therefore it may include information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a normalization detection method aiming at a chip design link so as to solve the problems in the background technology.

In order to achieve the above purpose, the present invention provides the following technical solutions:

A normalization detection method for chip design links specifically comprises the following steps:

s1: based on user setting, carrying out hierarchical division on the structure of the chip, creating a hierarchical structure diagram, carrying out functional description on each level of the chip, and adding a label to the description of each level;

S2: in the circuit design tool, defining the connection attribute for each layer, and defining the reference potential as a 0V substrate in a PSUB2 detection file;

S3: writing an LVS rule file according to the description of each layer and the corresponding connection attribute by utilizing an SVRF format tool, performing layer calculation, and forming a corresponding DRC detection statement according to the result of the layer calculation;

S4: and performing LVS verification on the chip by using an LVS tool, detecting whether the definition of the connection attribute and the reference potential of each layer is correct, performing DRC verification on the chip by using a DRC tool, detecting the connection relation between the annular P+ region and the 0V substrate of the chip by using the PSUB2 detection file and the position relation of the annular P+ region, and generating an error report according to the detection result.

Preferably, when the structure of the chip is divided into layers, the chip is divided into a plurality of groups of different sub-modules, and the hierarchy chart is used for marking each sub-module and the hierarchy relation thereof.

Preferably, the attribute tags added according to the connection relation between the layers comprise pins, a substrate, a power supply and a signal line.

Preferably, the step of performing DRC verification on the chip using the DRC tool includes:

constructing a PSUB2 detection file by using a DRC tool, and defining a PSUB2 layer, a ring-shaped P+ region layer, a DNW layer and an NBL layer in the PSUB2 detection file;

defining a PSUB2 layer in a PSUB2 detection file to be connected with a reference potential of a 0V substrate;

Writing a detection rule in the PSUB2 detection file to detect whether the PSUB2 layer is positioned in the region of the DNW layer or the NBL layer;

And writing a detection rule in the PSUB2 detection file, detecting whether a ring-shaped P+ region layer which uses the PSUB2 layer but is not connected with the reference potential of the 0V substrate and is not in the DNW layer or NBL layer region exists, and generating an error report if the ring-shaped P+ region layer exists.

Compared with the prior art, the invention has the beneficial effects that:

The present invention ensures that the P_RING using PSUB2 must be connected to the 0V group name or located within the DNW/NBL region through strict DRC error checking, thereby avoiding the signal clamping problem due to misuse of PSUB 2. The strict detection mode can not only prevent design errors and improve the reliability and accuracy of the design, but also save cost and time, has important educational significance for design teams, and remarkably improves the quality and efficiency of chip design flow.

Drawings

FIG. 1 is a schematic flow chart of the whole method of the invention.

Detailed Description

The present invention will be further described in detail with reference to specific embodiments in order to make the objects, technical solutions and advantages of the present invention more apparent.

It is to be noted that unless otherwise defined, technical or scientific terms used herein should be taken in a general sense as understood by one of ordinary skill in the art to which the present invention belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "up", "down", "left", "right" and the like are used only to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed accordingly.

Examples:

Referring to fig. 1, the present invention provides a technical solution:

A normalization detection method for a chip design link is characterized by comprising the following specific steps:

S1: based on user setting, carrying out hierarchical division on the structure of the chip, creating a hierarchical structure diagram, dividing the chip into a plurality of groups of different sub-modules when carrying out hierarchical division on the structure of the chip, wherein the hierarchical structure diagram is used for marking each sub-module and the hierarchical relationship thereof, carrying out functional description on each hierarchy of the chip, and adding a label to the description of each hierarchy.

In this step, through hierarchical division and creation of a hierarchical structure diagram, complex chip designs can be managed more systematically, the readability and maintainability of the designs are improved, the responsibility of each module is clarified, confusion and misunderstanding in the design are reduced, the connection relation of the designs is more visual, subsequent verification and problem positioning are facilitated, errors in the design process are reduced, and the design quality is improved.

S2: in the circuit design tool, its connection properties, including pins, substrate, power supply, and other critical nodes, are defined for each level, and the reference potential, i.e., group name, is defined as 0V substrate in the PSUB2 detection file. The group name refers to a node or signal used as a reference potential in a circuit design, and is typically used to provide a stable reference potential to ensure proper operation of the circuit. In actual design, the group name may be denoted as GND, VSS, etc., which is typically connected to the substrate of the chip or some specific circuit area. SOI/DNW/NBL techniques, which provide physical-level substrate isolation, i.e., true substrate isolation, can be effective in noise reduction or design using non-zero volt potential substrates, whereas PSUB2 (or other speaker-specific names) only works in the LVS link and does not participate in the actual chip mask logic operation, i.e., false substrate isolation. This technique does not truly isolate the substrate at the physical level, and misuse of PSUB2 can lead to serious design problems such as signal clamping at 0V, inability to verify the basic functions of the chip, time and cost waste.

In this step, the connection attribute and the reference potential are uniformly defined, so that the consistency of the design can be ensured, the group name is definitely defined as 0V, the subsequent DRC detection can be more definitely and simply, the subsequent verification step is simplified, the efficiency of the whole design flow is improved, and the error is directly presented in a DRC (Design Rule Check) mode, so that the defect that the warning is only carried out in a warning mode is avoided. Since DRC errors are mandatory, the design engineer must address these errors to make subsequent designs, thus ensuring PSUB2 is not erroneously used for non-zero volt signal designs, avoiding signal clamping at 0V, and significantly improving design reliability.

S3: writing LVS rule files according to the description of each layer and the corresponding connection attribute by using SVRF format tools such as Calibre or Hercules, performing layer calculation, and forming corresponding DRC detection sentences according to the result of the layer calculation;

S4: LVS verification is performed on the chip by using an LVS tool, such as Calibre, and whether the definition of the connection attribute and the reference potential of each layer is correct or not is detected. LVS is an abbreviation for Layout Versus Schematic, also known as "layout vs. schematic". This is a check method used in the integrated circuit design and verification process, mainly to ensure that the physical Layout (Layout) of the chip is completely consistent with the Schematic diagram (scheme) of the design stage.

And performing DRC verification on the chip by using a DRC tool, detecting the connection relation between the annular P+ region and the 0V substrate of the PSUB2 detection file and the position relation of the annular P+ region in the chip, and generating an error report according to the detection result. DRC is an abbreviation for Design Rule Checking, also called "design rule checking," used to ensure that the design layout meets the design rules of the manufacturing process, and potential layout problems can be discovered and corrected prior to chip fabrication, thereby improving production yields and avoiding failures in the manufacturing process.

In this step, compared with the conventional single verification method, the hierarchical connection attribute of the design and the connection relation of the PSUB2 layer are ensured to completely accord with the design specification through double verification of the LVS and the DRC tool, and the generated error report can accurately position the problems in the design, so that timely correction is facilitated.

The step of performing DRC verification on the chip using the DRC tool includes:

Taking a PSUB2 detection file written by a specific SVRF rule as an example:

firstly, performing hierarchical definition on a PSUB2 layer, a ring-shaped P+ region layer, a DNW layer and an NBL layer:

LAYER PSUB2

LAYER P_RING

LAYER DNW

LAYER NBL

second, the connection rule of the group name and 0V substrate needs to be defined:

CONNECT NAME NET=0V TO PSUB2

Third, find the annular p+ region layer using PSUB2 layer:

INSIDE P_RING PSUB2 P_RING_USING_PSUB2

Fourth, marking the PSUB2 layer which is not connected with the 0V substrate group name:

NOT CONNECTED PSUB2 0V NOT_CONNECTED_PSUB2

fifth, find the annular P+ region layer using PSUB2 layer not connected to 0V substrate group name:

INSIDE P_RING_USING_PSUB2 NOT_CONNECTED_PSUB2 P_RING_USING_INVALID_PSUB2

Sixth, searching a ring-shaped P+ region layer which is not in the DNW or NBL layer region:

NOT_INSIDE P_RING DNW OUTSIDE_DNW_P_RING

NOT_INSIDE P_RING NBL OUTSIDE_NBL_P_RING

seventh, the annular P+ region layer which is not in the DNW or NBL layer region is synthesized:

OR OUTSIDE_DNW_P_RING OUTSIDE_NBL_P_RING OUTSIDE_DNW_NBL_P_RING

Eighth step, a PSUB2 layer, to which a 0V substrate group name is not attached, is used, and a ring-shaped p+ region layer within the DNW or NBL layer region is not marked:

AND P_RING_USING_INVALID_PSUB2 OUTSIDE_DNW_NBL_P_RING INVALID_P_RING_USING_PSUB2

Ninth, generating an error report:

DRC CHECK "P+RING uses PSUB2 but not connected to 0V or not in DNW/NBL region" INVALID_P_RING_USING_PSUB2

the above-mentioned p+ RING in the PSUB2 detection file error report refers to a RING-shaped p+ region layer, and the PSUB2 detection file is used to indicate all RING-shaped p+ region layers that use PSUB2 layers, but are not connected to the reference potential of the 0V substrate, and are not in the DNW layer or NBL layer region. The overall PSUB2 test file is as follows:

Layer of definition

LAYER PSUB2

LAYER P_RING

LAYER DNW

LAYER NBL

V/definition 0-group name connection rule

CONNECT NAME NET=0V TO PSUB2

P_RING using PSUB2 for the// lookup

INSIDE P_RING PSUB2 P_RING_USING_PSUB2

PSUB2 that is not connected to 0V group name is/is searched for

NOT CONNECTED PSUB2 0V NOT_CONNECTED_PSUB2

P_RING using PSUB2 unconnected to 0V group name for// lookup

INSIDE P_RING_USING_PSUB2 NOT_CONNECTED_PSUB2 P_RING_USING_INVALID_PSUB2

P_RING not within DNW/NBL is/are looked up

NOT_INSIDE P_RING DNW OUTSIDE_DNW_P_RING

NOT_INSIDE P_RING NBL OUTSIDE_NBL_P_RING

P_RING not within DNW/NBL is synthesized/synthesized

OR OUTSIDE_DNW_P_RING OUTSIDE_NBL_P_RING OUTSIDE_DNW_NBL_P_RING

P_RING with/find not within DNW/NBL and with invalid PSUB2

Error-reporting method

Through the automatic rule generation and DRC detection statement, the high efficiency and accuracy of the verification process are ensured, the automation and the intellectualization of the whole design flow are promoted, the times of repeated work and repeated modification are reduced, the false use of PSUB2 by non-zero volt signals is avoided, the waste of labor cost and sheet flow cost is caused, and the overall design efficiency is improved.

In summary, the method and the device have the remarkable advantages in the aspects of systematic management, standardized definition, automatic rule generation, double verification and the like through the steps. Compared with the prior art, the invention ensures that the P_RING using PSUB2 must be connected to 0V group name or located in DNW/NBL area through strict DRC error checking, thereby avoiding the problem of signal clamping caused by misuse of PSUB 2. The strict detection mode can not only prevent design errors and improve the reliability and accuracy of design, but also save cost and time, and has important educational significance for design teams. The beneficial effects are reflected in detail in the background technology, and the quality and efficiency of the chip design flow are obviously improved.

The above formulas are all formulas with dimensions removed and numerical values calculated, the formulas are formulas with a large amount of data collected for software simulation to obtain the latest real situation, and preset parameters in the formulas are set by those skilled in the art according to the actual situation.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. Those of skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application.

Claims

1. A method for standardization detection of chip design, characterized in that the specific steps include:

S1: Based on user settings, the chip structure is divided into layers and a hierarchical structure diagram is created. Then, each layer of the chip is functionally described and labels are added to the description of each layer.

S2: In the circuit design tool, define the connection properties for each layer and define the reference potential as 0V substrate in the PSUB2 detection file;

S3: Using the SVRF format tool, write the LVS rule file and perform hierarchical calculation according to the description of each level and its corresponding connection attributes, and form the corresponding DRC detection statement according to the result of the hierarchical calculation;

S4: Use the LVS tool to perform LVS verification on the chip to detect whether the connection attributes and reference potential definitions of each layer are correct, and then use the DRC tool to perform DRC verification on the chip to detect the connection relationship between the ring-shaped P+ area and the 0V substrate using the PSUB2 detection file in the chip, as well as the position relationship of the ring-shaped P+ area, and generate an error report based on the detection results;

The steps of using the DRC tool to perform DRC verification on the chip include:

Use the DRC tool to build a PSUB2 test file, and define the PSUB2 layer, annular P+ area layer, DNW layer, and NBL layer in the PSUB2 test file;

In the PSUB2 test file, define that the PSUB2 layer is connected to the reference potential of the 0V substrate;

Write detection rules in the PSUB2 detection file to detect whether the PSUB2 layer is located in the area of the DNW layer or the NBL layer;

Write detection rules in the PSUB2 detection file to detect whether there is a ring-shaped P+ region layer that uses the PSUB2 layer but is not connected to the reference potential of the 0V substrate and is not in the DNW layer or NBL layer area. If so, an error report is generated.

2. According to claim 1, a standard detection method for chip design is characterized in that: when the chip structure is hierarchically divided, the chip is divided into several groups of different sub-modules, and the hierarchical structure diagram is used to mark each sub-module and its hierarchical relationship.

3. According to claim 1, a standard detection method for chip design links is characterized in that the attribute labels added according to the connection relationship between the levels include pins, substrates, power supplies, and signal lines.