CN118694537B - Trusted image sensor chip based on 4T-APS optical reconfigurable strong PUF - Google Patents
Trusted image sensor chip based on 4T-APS optical reconfigurable strong PUF Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0866—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
- H04N25/41—Extracting pixel data from a plurality of image sensors simultaneously picking up an image, e.g. for increasing the field of view by combining the outputs of a plurality of sensors
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Abstract
本发明公开了一种基于4T‑APS光学可重构强PUF的可信图像传感器芯片，其包括可信图像传感器、偏置调节电路、行扫描器、列扫描器、信号读出电路、控制电路、模拟选择器以及比较器，其中，可信图像传感器包括多个感光像素单元；偏置调节电路与每一列感光像素单元连接；每一行感光像素单元均与行扫描器连接；每一列感光像素单元与信号读出电路及模拟选择器连接，模拟选择器与比较器连接，比较器用于输出PUF响应；控制电路与行扫描器及信号读出电路连接，以提供第一控制信号；列扫描器与模拟选择器和信号读出电路连接，以为模拟选择器提供第二控制信号及为读出电路提供列扫描信号实现数字成像信号读出。本发明实现了图像传感器的可信任传感功能。
The present invention discloses a trusted image sensor chip based on 4T-APS optical reconfigurable strong PUF, which includes a trusted image sensor, a bias adjustment circuit, a row scanner, a column scanner, a signal readout circuit, a control circuit, an analog selector and a comparator, wherein the trusted image sensor includes a plurality of photosensitive pixel units; the bias adjustment circuit is connected to each column of photosensitive pixel units; each row of photosensitive pixel units is connected to the row scanner; each column of photosensitive pixel units is connected to the signal readout circuit and the analog selector, the analog selector is connected to the comparator, and the comparator is used to output a PUF response; the control circuit is connected to the row scanner and the signal readout circuit to provide a first control signal; the column scanner is connected to the analog selector and the signal readout circuit to provide a second control signal for the analog selector and provide a column scanning signal for the readout circuit to realize digital imaging signal readout. The present invention realizes the trusted sensing function of the image sensor.
Description
Technical Field
The invention relates to the technical field of integrated circuit hardware security, in particular to a trusted image sensor chip based on 4T-APS optical reconfigurable strong PUF.
Background
In recent years, the Internet of things represented by CMOS image sensors (CMOS Image sensor, CIS) has been rapidly developed under the promotion of smart phones, internet of things (Internet of things) (IoT), industries 4.0 and 5G, and the like. The global market size for CMOS image sensors estimated by the company Yole Group in france would be 290 billion dollars by 2028. In addition, the image sensor nodes are widely distributed on the edge equipment of the Internet of things and used for scenes involving a large amount of private information such as face payment, fingerprint identification, identity authentication, secret video conference, authorized digital view and the like, so that people have urgent information security demands on application of the image sensor nodes.
The image sensor is taken as an important component for changing the life style of human beings in the ecological system of the Internet of things, and is always a weak link and a target of network physical attack. One report from SAM company shows that over 10 hundred million attacks against the internet of things have occurred in 2021, of which nearly 9 hundred million are phishing attacks related to the internet of things, whereas attacks against cameras alone reach 2700 ten thousand. Moreover, the image sensor is also faced with the threats of demonstration attack, virtual camera attack, fake/falsify of image by the generated artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) technology, and the like. Furthermore, due to the demanding requirements of image sensor devices for size, cost and portability, the power consumption and processing power of many image sensor devices are highly limited, making it difficult to meet high security requirements.
For the security threat and security hole caused by the unreliability of the image sensor chip, how to implement the anti-fraud technology from the hardware level with the image sensor as a core has attracted a great deal of attention from researchers in the field. In order to realize the security authentication of the image sensor, namely to develop a trusted image sensor, researchers have recently proposed a technical scheme of integrating a general encryption and authentication circuit module onto the image sensor so as to ensure the security and the authenticity of a terminal sensor node, and an upper user does not need to worry about the security problem of relatively complex software in an imaging system. However, this scheme has problems of high cost, complex process, high power consumption, susceptibility to physical intrusion attacks on the key stored in the nonvolatile memory, and the like, so that it cannot be widely applied to the field of image sensors. The physical unclonable function (PHYSICALLY UNCLONABLE FUNCTION, PUF) is used as a lightweight hardware security primitive, the data information with the characteristics of uniqueness, randomness, unclonability and the like is easily generated by forward extraction of the unavoidable process deviation in the chip manufacturing process, the information is generated in real time, the additional storage is not needed, the hardware resource is saved, the risk of physical attack is reduced, and an economic and feasible lightweight solution is provided for the fields of key generation, identity authentication, information security and the like. Therefore, how to fuse the image sensor with the strong PUF security technology and implement the trusted sensing function of the image sensor is a problem that needs to be solved.
Therefore, in order to solve the above problems, the present invention provides a trusted image sensor chip based on a 4T-APS optically reconfigurable strong PUF that can fuse an image sensor with the strong PUF.
Disclosure of Invention
The invention provides a trusted image sensor chip based on a 4T-APS optical reconfigurable strong PUF, and aims to solve the problem that the existing image sensor cannot realize a trusted sensing function.
In order to solve the technical problems, the invention provides a trusted image sensor chip based on 4T-APS optical reconfigurable strong PUF, which comprises a trusted image sensor, a bias adjusting circuit, a row scanner, a column scanner, a signal readout circuit, a control circuit, an analog selector and a comparator, wherein the trusted image sensor comprises a plurality of photosensitive pixel units, each photosensitive pixel unit can conduct independent sensitization to output corresponding light sensing output voltage, the bias adjusting circuit is connected with each column of photosensitive pixel units in the trusted image sensor to conduct bias adjustment on the magnitude of input current in each column of photosensitive pixel units, the control signal input end of each row of photosensitive pixel units is connected with the control end of the row scanner, the output end of each column of photosensitive pixel units is connected with the signal readout circuit and the analog selector, the analog selector is connected with the comparator, the comparator is used for outputting response, the control signal input end of each column of photosensitive pixel units is connected with the control signal readout circuit, and the analog selector is connected with the column scanner and the analog selector, and the control signal readout circuit is connected with the digital selector and the digital selector.
Further, the bias adjusting circuit comprises a tail current source tube and a current mirror, and the tail current source tube and the current mirror are respectively connected with the voltage output end of each photosensitive pixel unit in a row of photosensitive pixel units.
Further, the drain electrode of the tail current source tube is connected with the current mirror and the photosensitive pixel unit, the source electrode of the tail current source tube is grounded, and the grid electrode of the tail current source tube is used for inputting reference voltage.
Further, the photosensitive pixel unit includes a photodiode, a transfer transistor, a reset transistor, a source follower transistor and a row select transistor, wherein, the drain of the reset transistor is connected with the drain of the source follower transistor, the source of the reset transistor is connected with the drain of the transfer transistor and the gate of the source follower transistor, the source of the source follower transistor is connected with the source of the row select transistor, the gate of the row select transistor is connected with the control end of the row scanner, the drain of the row select transistor is used as the voltage output end of the photosensitive pixel unit, the source of the transfer transistor is connected with the cathode of the photodiode, and the anode of the photodiode is grounded.
Further, the gate of the reset transistor is used for inputting a reset signal, the gate of the transmission transistor is used for inputting a transmission signal, and the drain of the reset transistor and the drain of the source follower transistor are used for inputting a voltage stabilizing voltage.
Further, the bias voltage of the current mirror is adjusted to provide stable saturation current for each column of the photosensitive pixel units, so that the trusted image sensor is in a digital imaging working mode.
Further, the bias voltage of the tail current source tube is regulated to enable the source following transistor in each column of the photosensitive pixel units to be in a subthreshold region, so that the trusted image sensor is in a strong physical unclonable function working mode, and a hardware trust root required for realizing security authentication is provided for the trusted image sensor.
Further, the signal readout circuit comprises a column parallel programmable gain amplifier, an analog-to-digital converter and a latch shift circuit, wherein the input end of the column parallel programmable gain amplifier is connected with the output end of each column of the photosensitive pixel unit, the output end of the column parallel programmable gain amplifier is connected with the input end of the analog-to-digital converter, the output end of the analog-to-digital converter is connected with the latch shift circuit, and the column scanner is connected with the latch shift circuit.
Further, the latch shift circuit includes a shift register composed of a plurality of latches connected in series.
Further, the analog-to-digital converter is a column-parallel 10-bit successive approximation register analog-to-digital converter.
The invention discloses a trusted image sensor chip based on 4T-APS optical reconfigurable strong PUF, which comprises a trusted image sensor, a bias adjusting circuit, a row scanner, a column scanner, a signal readout circuit, a control circuit, an analog selector and a comparator, wherein the trusted image sensor comprises a plurality of photosensitive pixel units, each photosensitive pixel unit can conduct independent sensitization to output corresponding light sensing output voltage, the bias adjusting circuit is connected with each column of the photosensitive pixel units in the trusted image sensor to conduct bias adjustment on the magnitude of input current in each column of the photosensitive pixel units, the control signal input end of each row of the photosensitive pixel units is connected with the control end of the row scanner, the output end of each column of the photosensitive pixel units is connected with the signal readout circuit and the analog selector, the analog selector is connected with the comparator and is used for outputting response, the control circuit is connected with the row scanner and the signal readout circuit and the analog selector to provide digital signals for the first column scanner and the second scanner, and the analog selector is connected with the control signal readout circuit. In the circuit structure, by multiplexing a plurality of photosensitive pixel units in the trusted image sensor, through the row scanner, the column scanner, the bias adjusting circuit, the signal reading circuit, the analog selector and the comparator, not only digital imaging signals can be output, but also PUF responses can be output, hardware trust roots required by security authentication are provided for the trusted image sensor, and the trusted sensing function of the image sensor is further realized. The invention discloses a trusted image sensor chip based on 4T-APS optical reconfigurable strong PUF, which solves the problem that the existing image sensor cannot realize a trusted sensing function.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram of the overall architecture of a trusted image sensor chip based on a 4T-APS optically reconfigurable strong PUF provided by an embodiment of the present invention;
FIG. 2 is a diagram of a digital imaging mode of operation and a column shared bias circuit for a strong physical unclonable function mode of operation provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram of output voltages at different input stimuli provided by an embodiment of the present invention;
fig. 4 is an equivalent circuit schematic diagram of a photosensitive pixel unit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a strong PUF of a trusted image sensor provided by an embodiment of the present invention;
FIG. 6 is a diagram of an application effect of a trusted image sensor chip based on a 4T-APS optically reconfigurable strong PUF provided by an embodiment of the present invention;
FIG. 7 is another application effect diagram of a trusted image sensor chip based on a 4T-APS optically reconfigurable strong PUF provided by an embodiment of the present invention;
FIG. 8 is a diagram of yet another application effect of a trusted image sensor chip based on a 4T-APS optically reconfigurable strong PUF provided by an embodiment of the present invention;
FIG. 9 is a diagram of another application effect of a trusted image sensor chip based on a 4T-APS optically reconfigurable strong PUF provided by an embodiment of the present invention;
FIG. 10 is a diagram of the next application effect of a trusted image sensor chip based on a 4T-APS optically reconfigurable strong PUF provided by an embodiment of the present invention;
Reference numerals:
PIX, trusted image sensor, 11, bias adjusting circuit, 12, row scanner, 13, column scanner, 14, signal reading circuit, 141, parallel programmable gain amplifier, 142, analog-to-digital converter, 143, latch shift circuit, 15, control circuit, 16, analog selector, 17, comparator.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
Fig. 1 to 10 show an embodiment of a trusted image sensor chip based on a 4T-APS optically reconfigurable strong PUF provided by the present invention. The trusted image sensor PIX chip based on the 4T-APS optically reconfigurable strong PUF of the present embodiment includes a trusted image sensor PIX, a bias adjustment circuit 11, a row scanner 12, a column scanner 13, a signal readout circuit 14, a control circuit 15, an analog selector 16, and a comparator 17, where the trusted image sensor PIX includes a plurality of photosensitive pixel units, each of the photosensitive pixel units can perform independent sensitization to output a corresponding light sensing output voltage, the bias adjustment circuit 11 is connected to each column of the photosensitive pixel units in the trusted image sensor PIX to perform bias adjustment on the magnitude of an input current in each column of the photosensitive pixel units, a control signal input end of each row of the photosensitive pixel units is connected to a control end of the row scanner 12, an output end of each column of the photosensitive pixel units is connected to the signal readout circuit 14 and the analog selector 16, the analog selector 16 is connected to the comparator 17, the comparator 17 is connected to the control signal readout circuit 14 and the analog selector circuit 14, and the second row scanner 14 is provided with the control signal readout circuit 14 and the analog selector circuit 14. In this embodiment, the first control signal and the second control signal are both control signals, and have a control function. Row Scanner for each function in FIG. 1 is a Row Scanner 12,Column Scanner, a column Scanner 13, PGA (Programmable GAIN AMPLIFIER), a column parallel Programmable gain amplifier 141, SAR ADC (Successive-approximation-REGISTERADC), a column parallel 10-bit successive approximation register analog-to-digital converter 142, latches, SHIFT REGISTERS, a shift register, controller, control circuit 15, analog Mux, comparator, 17, pixel, and photosensitive pixel cell. It should be noted that, in this embodiment, by multiplexing a plurality of photosensitive pixel units in the trusted image sensor PIX, not only a digital imaging signal but also a PUF response can be output through the row scanner 12, the column scanner 13, the bias adjustment circuit 11, the signal readout circuit 14, the analog selector 16, and the comparator 17, so that a hardware trust root required for providing security authentication for implementing the trusted image sensor PIX is provided, and thus a trusted sensing function of the image sensor is implemented.
Referring to fig. 1, in an embodiment, for example, the signal readout circuit 14 includes a column-parallel programmable gain amplifier 141, an analog-to-digital converter 142 and a latch shift circuit 143, wherein an input end of the column-parallel programmable gain amplifier 141 is connected to an output end of each column of the photosensitive pixel units, an output end of the column-parallel programmable gain amplifier 141 is connected to an input end of the analog-to-digital converter 142, an output end of the analog-to-digital converter 142 is connected to the latch shift circuit 143, and the column scanner 13 is connected to the latch shift circuit 143. Specifically, the latch shift circuit 143 includes a shift register composed of a plurality of latches connected in series. More specifically, the analog-to-digital converter 142 is a column-parallel 10-bit successive approximation register analog-to-digital converter 142. Referring to fig. 2, in an embodiment, for example, the bias adjustment circuit 11 includes a tail current source tube and a current mirror, and the tail current source tube and the current mirror are respectively connected to a voltage output terminal of each of the photosensitive pixel units in a row of the photosensitive pixel units. Specifically, the drain electrode of the tail current source tube is connected with the current mirror and the photosensitive pixel unit, the source electrode of the tail current source tube is grounded, and the grid electrode of the tail current source tube is used for inputting reference voltage. the photosensitive pixel unit comprises a photodiode, a transmission transistor, a reset transistor, a source following transistor and a row selection transistor, wherein the drain electrode of the reset transistor is connected with the drain electrode of the source following transistor, the source electrode of the reset transistor is connected with the drain electrode of the transmission transistor and the grid electrode of the source following transistor, the source electrode of the source following transistor is connected with the source electrode of the row selection transistor, the grid electrode of the row selection transistor is connected with the control end of the row scanner 12, the drain electrode of the row selection transistor is used as the voltage output end of the photosensitive pixel unit, the source electrode of the transmission transistor is connected with the negative electrode of the photodiode, and the positive electrode of the photodiode is grounded. More specifically, the gate of the reset transistor is used for inputting a reset signal, the gate of the transmission transistor is used for inputting a transmission signal, and the drain of the reset transistor and the drain of the source follower transistor are used for inputting a regulated voltage. It should be noted that in this embodiment, the bias voltage of the current mirror is adjusted to provide a stable saturation current for each column of the photosensitive pixel units so that the trusted image sensor PIX is in a digital imaging working mode, and the bias voltage of the tail current source tube is adjusted to make the source follower transistor in each column of the photosensitive pixel units be in a subthreshold region so that the trusted image sensor PIX is in a strong physical unclonable function working mode, so as to provide a hardware trust root required for realizing security authentication for the trusted image sensor PIX. It should be noted that in this embodiment, in the digital imaging working mode, the trusted image sensor PIX firstly has two functions through the PGA, namely, the PGA obtains and amplifies the output signal from the photosensitive pixel unit to increase the effective input range of the SAR ADC, and secondly, the reset noise in the pixel can be completely eliminated by subtracting the signal voltage from the reset voltage, wherein the reset voltage is the voltage output by the trusted image sensor PIX after resetting the photosensitive pixel, and the signal voltage is the voltage output by the trusted image sensor PIX after exposing the pixel for a period of time. The SAR ADC is responsible for quantizing the amplified voltage signal into a digital signal, which is then stored in a latch in a shift register for reading by the column scanner 13. In the strong physical unclonable function operation mode, the trusted image sensor PIX arbitrarily selects pixels in two columns of photosensitive pixel units through the analog selector 16 to enter the comparator 17 to output PUF responses, and at this time, both the PGA and the SAR ADC can be selectively turned off to reduce power consumption overhead.
It should be further noted that, in the present embodiment, in the digital imaging operation mode, the column lines in the trusted image sensor PIX are biased using a shared constant current source (e.g., a current mirror) to operate the source follower transistor M SF in the selected photosensitive pixel cell in the saturation region. In the strong physical unclonable function mode, the source follower transistor M SF in the selected photosensitive pixel cell can be alternately biased to the subthreshold region by adding a subthreshold current load M bias,Mbias called a tail current source tube, so that a nonlinear exponential relationship is formed between the output voltage V out and the bias current I bias. Furthermore, a shift register based line scanner 12, which is used in a wide range of digital imaging modes of operation, is multiplexed to provide input stimuli for the optically reconfigurable strong PUF. Thus, there may be at most 2 M -1 different selection combinations per column of pixels. In the case of providing a uniform and constant reset signal V RST, the output voltage V out of the above-described 2 M -1 combination is different due to unavoidable device mismatch between different pixels. And, by multiplexing the column scanner 13 in the digital imaging operation mode, two columns of entropy sources V out can be arbitrarily selected for comparison and digitization, and then the response thereof is output. Thus, the total CRP (Challenge-response) space of the strong PUF proposed by the present embodiment can be further extended. It is well known that image resolution in digital imaging modes of operation can reach 1200 tens of thousands (i.e., 3120×4160), even 5000 tens of thousands (i.e., 6144×8192). Thus, based on the proposed strong PUF design, its total CRP space can reach a scale of 1.41×10 946 and 1.13×10 1857, respectively. At the same time, it is worth emphasizing that the above-described optically reconfigurable strong PUF with huge CRP space can be achieved by adding N columns of shared single transistor based subthreshold current load and ultra low design overhead of one 2-input digital comparator 17. furthermore, by switching off the added current load M bias, the proposed optically reconfigurable strong PUF can be disabled without any impact on the digital imaging mode of operation.
In an embodiment, for example, after fusing the image sensor and the strong PUF, performing theoretical analysis for resisting machine learning attack on the fused trusted image sensor chip specifically includes (1) analysis of entropy source of PUF and (2) analysis for resisting machine learning attack.
(1) PUF entropy source analysis
As described above, the photosensitive pixel unit of the image sensor is designed by adopting a 4T-APS structure, and the strong PUF in the optically reconfigurable sensor multiplexes the trusted image sensor as its entropy source. It should be noted that in the trusted image sensor, each photosensitive pixel unit includes a photodiode PD, a transfer transistor M TG, a reset transistor M RST, a source follower transistor M SF, and a row select transistor M SEL, and is surrounded by a guard ring formed by an N-well/deep N-well layer to reduce crosstalk between pixels. In this embodiment, two spatial Non-uniformities existing in the mainstream CIS pixels, namely spatial dark signal Non-Uniformity (DSNU) and light response Non-Uniformity (Photo Response Non-Uniformity, PRNU), may be used as entropy, and by using different physical mechanisms behind the two entropy sources, a PUF based on DSNU generated in a dark environment may be optically reconstructed by irradiating uniform monochromatic light, which is equivalent to an RGB color filter array that is widely used for white light in a practical application scenario.
In a strong physical unclonable function operating mode based on DSNU, the reset transistor M RST is normally on, while the transfer transistor M TG is normally off, and even if there is illumination, the photocurrent generated by the photodiode PD will not affect the node voltage V FD. At this time, the floating diffusion FD node voltage is expressed as in formula (1):
VFD＝VDD-Vth,RST (1)
In formula (1), V th,RST represents the threshold voltage of M RST. The voltage output on the column line after passing through M SF can be expressed as in equation (2):
Vout＝Av·VFD＝Av·(VDD-Vth,RST) (2)
In equation (2), a v is the voltage gain of M SF, and as can be seen from equation (2), the output voltage on the column line is related to both the reset transistor M RST and the source follower transistor M SF, i.e., they necessarily affect the output voltage on the column line due to unavoidable process variations in the manufacturing process of the reliable image sensor chip. To verify the distribution characteristics of the proposed entropy sources, a statistical analysis of the entropy sources of the optically reconfigurable strong PUF in DSNU mode is first performed, as shown in fig. 3, showing a statistical histogram based on the output voltage V out at 4096 different input stimuli, where the mean and standard deviation of V out are 765mV and 10.38mV, respectively.
When the PRNU-based strong physical unclonable function operating mode is operated, the reset transistor M RST and the transfer transistor M TG in the selected photosensitive pixel cell on the column line are in a normally-on state during the response generation period after input excitation, and the voltage of the photodiode PD is identical to the voltage of the FD node. If an external reverse voltage is applied to the photodiode PD, it operates in a photoconductive mode, which is like a variable resistor whose resistance varies with the variation of the illumination intensity. The photocurrent flows through an external circuit that provides a bias voltage and may measure the output current or voltage. Therefore, an equivalent circuit schematic diagram of the photosensitive pixel unit is shown in fig. 4.
In fig. 4, the photodiode PD can be represented by a current source and a parallel ideal diode, the ideal diode representing a PN junction, the current sources I PH、ID and I R representing photocurrent, dark current and noise current generated by incident light, respectively, and a junction capacitor C J and a parallel resistor R SH connected in parallel with other elements. A series resistance R S is connected in series with all elements in the model, R L representing the reset transistor M RST. The voltage on the FD node may be expressed as shown in equation (3):
After buffering by the source follower transistor M SF, the output voltage on the column line can be expressed as shown in equation (4):
In equation (4), a v is the voltage gain of the source follower transistor M SF, and the output voltage on the column line when the PUF is operating under illumination is related not only to the threshold voltage of the reset transistor M RST and the voltage gain of the source follower transistor M SF, but also to the junction capacitance of the photodiode PD and the incident light. As shown in fig. 3, a statistical histogram of the output entropy sources V out based on 4096 different input challenges in the strong physical unclonable function mode of operation based on PRNU is shown with mean and standard deviation of 653mV and 15.76mV, respectively. The standard deviation is 1.52 times of the working mode of the strong physical unclonable function based on DSNU, and the stability of the PUF is effectively improved.
(2) Machine learning attack resistance analysis
The most widely adopted approach to combat machine learning modeling attacks today is to introduce nonlinear structures to increase the complexity of CRP mapping, in particular, to exploit the exponential relationship between voltage and current of transistors operating in the subthreshold regime to significantly increase CRP space complexity and, more importantly, also reduce overall power consumption. In this work, the tail current source tube M bias added to the column line described above is operated in the subthreshold region with its gate voltage V bias set to 450mV, which can introduce a large nonlinearity for the entropy source of V out. Specifically, the I-V relationship for the MOS transistor operating in the subthreshold region can be expressed as shown in equation (5):
Fig. 5 is a schematic diagram of a strong PUF of a trusted image sensor provided by an embodiment of the present invention, where (m+n) bit excitation may be provided by a row scanner and a column scanner, two columns may be arbitrarily selected among N columns, and any X pixels may be selected from M pixels in each column as an entropy source. The total current I bias through tail current tube M bias can thus be calculated as shown in graph formula (6):
In formula (6), V bias、Vth,b、Vds,b、Wb、Lb、mb is the gate voltage, threshold voltage, drain-source voltage, effective channel width/length and sub-threshold slope coefficient of tail current source tube M bias respectively, From equation (6), it is known that V out is a nonlinear and highly complex function between the final output value and the input stimulus, given the unavoidable process-related parameter mismatch that exists in all selected pixels during fabrication.
For the strong PUF proposed in this embodiment, a mathematical model analysis is performed for the case of M photosensitive pixel cells in any two columns. Definition of the definitionA1×m eigenvector representing the input stimulus C; Is a1×m row vector of photosensitive pixel cells affected by process variations, modeled here as equivalent conductance. Under the same power supply voltage condition, the selected pixel units sharing the same column line can be regarded as a whole, so that the output response R of the two selected column entropy sources after being digitized by the comparator can be equivalently expressed as formula (7):
The final response R is determined jointly by the equivalent conductance values of the selected photosensitive pixel cells according to equation (7). Taking the I-th selected photosensitive pixel cell as an example, according to equation (5), I dsi is a nonlinear function of V ds (i.e., V DD-Vout), then the conductance value ρ i of M SF can be expressed as equation (8):
From equation (8), the conductance ρ i of M SF in each selected photosensitive pixel cell is a nonlinear function of V out, while V out is commonly affected by all other selected photosensitive pixel cells. With V DD constant, any change in V out affects not only V ds but also V gsi (i.e., V PDi-Vout), which in turn results in a further effect on conductance ρ i. Thus, the conductivity of M SF in each selected pixel dynamically varies with V ds, while the output voltage V out also dynamically varies with different selected photosensitive pixel cells. In this way, the overall parameters required to model the attack are greatly increased. Specifically, for M photosensitive pixel cells in a column, the conductance of any selected photosensitive pixel cell is affected by the other (M-1) pixel cells, and the maximum modeling parameter is m× (M-1 +1) in theory. In this embodiment, the total parameters required to be modeled by the machine learning algorithm are about 2.18×10 40, and the high-complexity model parameters can significantly enhance the robustness of the proposed strong physical unclonable function circuit and reduce the accuracy of accurate modeling by using the mainstream machine learning algorithm, so that it is difficult to crack the model with the scale parameters in a reasonable time even if the advanced artificial intelligence algorithm is adopted. Therefore, the strong physical unclonable function circuit has good attack resistance to advanced artificial intelligence algorithms from the perspective of a mathematical model.
In an embodiment, e.g. the present embodiment, in order to verify the proposed 4T-APS optically reconfigurable strong PUF based trusted image sensing chip, the design and fabrication is performed using a standard 65nm CMOS process in the present embodiment, where M and N are both designed to 128. The total chip area was measured to be 2.33×10 6μm2 (i.e. 5.52×10 8F2), the silicon area dedicated to the proposed strong PUF (i.e. added tail current supply tube M bias plus digital comparator) was 6174 μm 2 (i.e. 1.46×10 6F2). This means that more than 99.735% of the area of the whole chip can be multiplexed to the proposed strong PUF, i.e. only 0.265% of the extra small design overhead is added. Furthermore, with the FPGA development board (Xilinx Davinci), 256-bit (i.e., 128+128=256) input stimuli are provided for the proposed strong PUF by fully multiplexing the row and column scanners of the designed trusted image sensor. Ultra-low power of 14.15 mu W is achieved at a maximum throughput of 2.5Mb/s, and the energy consumption efficiency of the proposed strong PUF is 5.66pJ/bit.
1) Reliability of
Reliability is an important figure of merit that measures the repeatability of CRP of PUFs under various environmental factors (e.g., time domain noise, supply voltage, and temperature variations). First, the effect of time domain noise on its stability is evaluated by repeatedly reading the output response of the PUF at a fixed voltage and temperature. Specifically, under normal Voltage-Temperature (VT) conditions (25 ℃, 1.2V), 2000 different stimuli are input to 20 test chips, and the cycle is traversed 5000 times, and then the Bit Error Rate (BER) of the output response is counted. As shown in fig. 6 (a), at 20 test chips, the average worst raw error rates of DSNU and PRNU-based PUF were 2.26% and 1.54%, respectively, and the average worst raw error rates (Unstable Bit Rate, UBR) were 9.21% and 4.84%, respectively. As shown in fig. 6 (b), variations in supply voltage and temperature further reduce the reliability of the PUF, and the bit error rate is estimated by comparison with the output response under normal VT operating conditions. And testing error rates of 20 test chips under each condition under the conditions that the temperature change range is-20 ℃ to 100 ℃ and the power supply voltage change range is 1.08V to 1.32V, and taking an average value. Fig. 6 (C) shows the two-dimensional distribution of average bit error rates of DSNU-based PUFs over the above-mentioned VT variation range, showing that the worst bit error rate without any correction occurs at VT condition of (100 ℃, 1.08V) and this value is 13.3%, while the average bit error rate of PRNU-based PUF without any correction occurs at VT condition of (100 ℃, 1.08V) and this value is 8.4%, as shown in fig. 6 (d).
2) Randomness of
The randomness of the strong PUF proposed in this embodiment can be evaluated by means of an autocorrelation function (Autocorrelation Function, ACF) and NIST random test, which reflects well the unpredictability of the strong PUF to unknown responses. It is well known that ACF is an important indicator of the randomness of a bit stream, and for a bit stream generated by white noise, the ACF value is close to zero at any hysteresis value other than zero. For a strong PUF with exponential CRP space in a limited silicon area, the same PUF bit cell shared by different CPR may cause the output response to appear correlated. The correlation was first quantified using ACF, as shown in fig. 7, with 20 tens of thousands of stimulus-generated responses tested, the ACF values of DSNU and PRNU-based PUFs were equal to ± 0.01369 and ± 0.01104, respectively, with 95% confidence, indicating a strong randomness. In addition, 1000 ten thousand responses were collected and divided into 20 groups for the proposed strong PUF, and their randomness was further statistically assessed using the NIST pub.800-22 test suite. Based on statistical analysis results, it was shown that both DSNU and PRNU based PUFs passed all relevant NIST tests, with corresponding P-Val greater than 0.01.
3) Uniqueness of the product
Uniqueness is used to quantitatively describe the distinguishability between different PUF chips, also known as the inter-PUF hamming distance. 2000 identical excitations were applied at a reference temperature and voltage (25 ℃, 1.2V) and a total of 20 test chips could be calculatedThe hamming distances between the PUFs are normalized and plotted in fig. 8. Uniqueness is defined as the average of the best-fit gaussian curves of the above-mentioned inter-PUF hamming distance distribution, and the results show that the inter-chip hamming distances of DSNU and PRNU-based PUFs are 0.4969 and 0.5013, respectively, each close to the ideal value of 0.5. In addition, the experiment also measured and calculated the hamming distance within the PUF to evaluate its robustness. To evaluate the robustness of the PUF to time noise, a 500-reading of the 2000-bit output response of the PUF is repeated, and the hamming distance between the 2000-bit output responses of any two of the 500-reading is calculated. As shown in fig. 8, DSNU-based PUF has an intra-chip hamming distance distribution of μ=0.0097 and σ=0.0012, and a degree of separation from the inter-chip hamming distance distribution of 51.2 times, and PRNU-based PUF has an intra-chip hamming distance distribution of μ=0.0053 and σ=0.0016, and a degree of separation from the inter-chip hamming distance distribution of 94.6 times.
4) Optical reconfigurability
The reconfigurability is a fundamental property of a reconfigurable PUF, which can also be evaluated by the inter-chip hamming distance. The present embodiment can realize an optically reconfigurable CRP by changing the state of the external ambient light, i.e. by a transition from DSNU mode to PRNU mode. In the experiment, 50 5120 bit PUF samples were extracted from 10 test chips under dark conditions and under irradiation of a 550nm light source with a power of 0.545mW/cm 2, respectively. The results show that the 50 reconfigured hamming distances have a distribution mean of 0.4896 and a standard deviation of 0.0466. The pearson correlation coefficient (Pearson correlation coefficient, PCC) may show a correlation between two sequences. If each variable has N scalar observations, then the PCC definition is as shown in equation (9):
In formula (9), μ A and σ A are the average and standard deviation of a, respectively, and μ B and σ B are the average and standard deviation of B. To further analyze the correlation between the different reconstructed responses, PCC was calculated. From the 50 5120 bit PUF examples extracted from 10 test chips, the reported average PCC is 0.1866, verifying that the PUF bitstreams obtained from DSNU and PRNU are independent of each other, as shown in fig. 9. The results show that the reconfigurable PUF successfully achieves the generation of uncorrelated CRPs between DSNU and PRNU modes.
5) Resistance to machine learning attacks
Modeling attacks are tools that an attacker tries to break the identity authentication provided by a strong PUF, so the ability of a strong PUF to resist modeling attacks is considered as a final criterion for measuring its security. These attacks rely on the powerful functions of machine learning algorithms to accurately predict unknown CRPs by collecting a small part of CRPs to model the internal parameters of a strong PUF. For most existing strong PUFs, such as APUF, their corresponding model functions can be represented as linear superposition of internal delays, making them vulnerable to machine learning modeling attacks. The nonlinear strong PUF proposed in this embodiment exhibits a large number of unknown parameters, increasing the complexity of the machine learning modeling attack.
To evaluate the ability to resist machine learning attacks, we have adopted four mainstream machine learning algorithms to attack the proposed strong PUF, including ANN based on 80 x 80 multi-layer perceptions, LR using gradient descent optimizers, SVM using radial basis functions (Radial Basis Function, RBF), and CMA-ES. 4000 ten thousand CRP is randomly collected from a prototype chip in the experiment as a training set, 500 ten thousand CRP is collected as a test set, and the number of CRP in the training set is changed from 1000 to 4000 ten thousand, and training and prediction are carried out by using ANN, LR, SVM and CMA-ES algorithms respectively. FIG. 10 is a relationship between the prediction accuracy of various machine learning algorithms and the number of CRPs used to train the algorithms. It can be seen that the accuracy of predictions by DSNU and PRNU-based PUFs for all machine learning algorithms described above can be well kept around 50%, i.e. equivalent to random predictions.
6) Performance comparison
Comparing the trusted image sensor chip in this embodiment with the performance of the most advanced ASIC strong PUF ((in this embodiment, including 4 comparisons, where comparison 1 is the performance result disclosed in "Zhuang H,Xi X,Sun N,et al.A strong subthreshold current array PUF resilient to machine learning attacks[J].IEEE Transactions on Circuits and Systems I:RegularPapers,2019,67(1):135-144."; comparison 2 is the performance result disclosed in "VenkateshA,VenkatasubramaniyanA B,Xi X,et al.0.3pJ/bit machine learning resistant strong PUF using subthreshold voltage divider array[J].IEEE Transactions on Circuits and Systems II:Express Briefs,2019,67(8):1394-1398."; comparison 3 is the performance result disclosed in "Liu J,ZhuY,Chan C-H,et al.A 0.04％BER strong PUF with cell-bias-based CRPs filtering and background offset calibration[J].IEEE Transactions on Circuits and Systems I:RegularPapers,2020,67(11):3853-3865."; comparison 4 is the performance result disclosed in "Zhang J,Xu C,Law M-K,et al.A 4T/Cell Amplifier-Chain-Based XOR PUF With Strong Machine LearningAttack Resilience[J].IEEE Transactions on Circuits and Systems I:RegularPapers,2021,69(1):366-377."). The proposed strong PUF of this embodiment has an ultra high hardware multiplexing rate of 99.735% and the silicon area overhead dedicated to designing PUFs is as compact as only 1.46×10 6F2. Even in the case of a pixel array of digital imaging mode of operation as only 128×128, the strong CRP space is 2.77×10 42 and the CRP space can be further expanded by designing a larger digital imaging mode of operation pixel array. CRP space is normalized to an overall silicon area of 5.52×10 8F2, the calculated area efficiency is 5.01×10 33bit/F2, significantly exceeding the area efficiency of other ASIC strong PUFs by 19-22 orders of magnitude.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
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