CN118712131B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN118712131B CN118712131B CN202411204248.XA CN202411204248A CN118712131B CN 118712131 B CN118712131 B CN 118712131B CN 202411204248 A CN202411204248 A CN 202411204248A CN 118712131 B CN118712131 B CN 118712131B
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- 238000000034 method Methods 0.000 title claims abstract description 91
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 105
- 229920005591 polysilicon Polymers 0.000 claims abstract description 91
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 230000008569 process Effects 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 48
- 238000002955 isolation Methods 0.000 claims description 54
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 239000006117 anti-reflective coating Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 abstract description 12
- 230000007704 transition Effects 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 105
- 238000000576 coating method Methods 0.000 description 18
- 239000011248 coating agent Substances 0.000 description 17
- 239000011247 coating layer Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000002860 competitive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- -1 silicon gallium compounds Chemical class 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
The invention provides a semiconductor device and a preparation method thereof, wherein the preparation method of the semiconductor device comprises the steps of providing a substrate, forming a groove structure in the substrate of a first device region and extending into the substrate of a second device region, forming an oxide layer in the groove structure, etching the oxide layer in the first device region to form a recess, wherein the recess is adjacent to the second device region, the length of the recess is greater than or equal to one eighth of the length of the groove structure, and forming a polysilicon gate in the recess. The semiconductor device prepared by the preparation method can form the sunken polycrystalline silicon grid in the first device region, so that the step height of the transition region of the first device region and the second device region is reduced, polycrystalline silicon residues can be avoided after the subsequent etching process, and meanwhile, the problem of insufficient CD process window can be avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
With the rapid development of semiconductor manufacturing technology, the requirements on the density and the integration level of chip elements are continuously increasing, and multiple circuits are required to be integrated on one chip at the same time. These circuits need to rely on multiple MOS (Metal-Oxide-Semiconductor) transistors with different operating voltages to perform functions, such as integrating Low Voltage (LV), medium Voltage (MV) and High Voltage (HV) devices on the same chip, and as the operating Voltage of the MOS transistor is continuously increased, the thickness of the gate Oxide layer needs to be correspondingly increased in order to ensure that the MOS transistor is not broken down. Thus, for a typical manufacturing process, there will be a large height difference for different regions formed by MOS transistors with different operating voltages, which will cause insurmountable difficulties for the photolithography and etching of polysilicon gates (Poly) and the like. For example, the step height on STI (shallow trench isolation) in the transition region of high-voltage device and medium-voltage device is relatively large, resulting in thicker film stack at this point during polysilicon deposition, and subsequent etching processes, if a conventional OE (over etching) process is used, an over etching amount may be insufficient, which may easily result in the generation of polysilicon residues, and if the OE amount is increased, there may be a risk of insufficient CD (critical dimension) process window. Moreover, as the process node advances, the above phenomenon (polysilicon residues and insufficient CD process window) becomes more pronounced as the process node is smaller, for example, the film stack is thicker at the step of the 40nm process node than at the 55nm process node, and the phenomenon becomes more pronounced.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, which are used for solving the problems of polysilicon residue and insufficient CD process window in a transition region of a first device region and a second device region.
To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of:
providing a substrate, wherein the substrate comprises a first device region and a second device region adjacent to the first device region;
forming a groove structure in the substrate of the first device region and extending to the substrate of the second device region;
Forming an isolation oxide layer in the groove structure, and etching the isolation oxide layer in the first device region to form a recess, wherein the recess is adjacent to the second device region, and the length of the recess is greater than or equal to one eighth of the length of the groove structure;
and forming a polysilicon gate in the recess.
Optionally, in the method for manufacturing a semiconductor device, the forming process of the trench structure and the forming process of the recess are both dry etching processes.
Optionally, in the method for manufacturing a semiconductor device, the first device region is a high-voltage device region, and the second device region is a medium-voltage device region or a low-voltage device region.
Optionally, in the method for manufacturing a semiconductor device, a length of the trench structure is greater than or equal to 0.48 μm, and a depth of the trench structure is greater than or equal to 0.31 μm.
Optionally, in the method for manufacturing a semiconductor device, a thickness of the isolation oxide layer between the sidewall of the recess and the first device region is greater than or equal to 0.21 μm.
Optionally, in the method for manufacturing a semiconductor device, the length of the polysilicon gate is greater than or equal to 0.06 μm.
Optionally, in the method for manufacturing a semiconductor device, a thickness of the isolation oxide layer under the polysilicon gate is greater than or equal to a thickness required by a breakdown voltage of the first device region.
Optionally, in the method for manufacturing a semiconductor device, the step of forming a polysilicon gate in the recess includes:
Depositing a polysilicon layer in the recess, the polysilicon layer also being deposited on the substrate of the first and second device regions;
And removing the polysilicon layer on the substrate outside the recess through an etching process to form a polysilicon gate.
Optionally, in the method for manufacturing a semiconductor device, the step of removing the polysilicon layer on the substrate outside the recess through an etching process includes:
forming an anti-reflection coating layer, wherein the anti-reflection coating layer covers the polysilicon layer;
forming a patterned photoresist layer covering the anti-reflective coating over the recess;
And sequentially performing an etching process on the anti-reflection coating and the polycrystalline silicon layer by taking the patterned photoresist layer as a mask so as to remove the anti-reflection coating and the polycrystalline silicon layer on the substrate outside the recess.
To achieve the above and other related objects, the present invention also provides a semiconductor device manufactured by the above-described method for manufacturing a semiconductor device, comprising:
a substrate comprising a first device region and a second device region adjacent to the first device region;
A trench structure located in the substrate of the first device region and extending into the substrate of the second device region;
An isolation oxide layer located in the trench structure;
a recess in the isolation oxide layer of the first device region and adjacent to the second device region, the recess having a length greater than or equal to one eighth of a length of the trench structure;
And the polysilicon gate is positioned in the recess.
Compared with the prior art, the technical scheme of the invention has the following unexpected beneficial effects:
According to the preparation method of the semiconductor device, the sunken polycrystalline silicon grid is formed in the first device region, and the polycrystalline silicon grid is adjacent to the second device region, so that the thickness of the thin film stack in the transition region between the second device region and the first device region is reduced, namely the step height of the second device region and the first device region is reduced, and therefore, the polycrystalline silicon residue can be avoided without additionally increasing the over etching amount in the subsequent over etching process, and meanwhile, enough CD process window can be guaranteed, and excellent compatibility with the existing process is achieved. And the semiconductor device has the advantages of reduced device size and more competitive product.
In addition, compared with the prior art, the preparation method of the semiconductor device is easier to realize, can reduce the complexity of the process, and can realize obvious economic benefit.
Drawings
Fig. 1 is a schematic diagram of a product structure after step S01 is performed in a method for manufacturing a semiconductor device;
fig. 2 is a schematic diagram of a product structure after step S04 is performed in a method for manufacturing a semiconductor device;
fig. 3 is a schematic diagram of a product structure after depositing a polysilicon layer in a method of manufacturing a semiconductor device;
Fig. 4 is a schematic diagram of a product structure after performing step S052 in a method of manufacturing a semiconductor device;
Fig. 5 is a schematic diagram of a product structure after performing step S053 in a method of manufacturing a semiconductor device;
fig. 6 is a schematic view showing a product structure after performing step S1 in the method for manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 7 is a schematic view of a product structure after performing step S2 in the method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a product structure after forming an isolation oxide layer in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 9 is a schematic view showing a product structure after performing step S3 in the method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 10 is a schematic view of a product structure after performing step S41 in the method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 11 is a schematic view showing a product structure after step S42 is performed in the method for manufacturing a semiconductor device according to an embodiment of the present invention;
In fig. 1 to 5:
01-substrate, 02-substrate oxide layer, 03-shallow trench isolation structure, 04-gate oxide layer, 05-polysilicon layer, 051-polysilicon residue, 06-anti-reflection coating, 07-patterned photoresist layer;
in the figures 6 to 11 of the drawings,
10-Substrate, 20-substrate oxide layer, 30-trench structure, 40-isolation oxide layer, 50-recess, 60-polysilicon gate, 60 a-polysilicon layer.
Detailed Description
The semiconductor device and the method for manufacturing the same according to the present invention are described in further detail below with reference to the accompanying drawings and specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Referring to fig. 1 to 5, a method of manufacturing a semiconductor device may include:
step S01, providing a substrate 01, wherein the substrate 01 comprises a first device region and a second device region adjacent to the first device region;
step S02, forming a shallow trench isolation structure 03 in a transition region of the first device region and the second device region;
Step S03, forming a gate oxide layer 04 on the substrate 01 and the shallow trench isolation structure 03;
Step S04, performing a first etching process to remove the gate oxide layer 04 of the second device region and remove part of the thickness of the shallow trench isolation structure 03 of the second device region, so as to expose the substrate 01 and the shallow trench isolation structure 03 of the second device region;
step S05, depositing a polysilicon layer 05 on the gate oxide layer 04 and the exposed substrate 01 and shallow trench isolation structure 03, and performing a second etching process to remove the polysilicon layer 05 in the second device region.
In step S01, the first device region is an HV region (high voltage region), and the second device region is an MV region (medium voltage region).
In step S02, the upper surface of the shallow trench isolation structure 03 is slightly higher than the upper surface of the substrate 01.
The preparation method may further comprise forming a substrate oxide layer 02 on the substrate 01 before performing step S02.
In step S04, after removing the gate oxide layer 04 of the second device region, a portion of the thickness of the shallow trench isolation structure 03 is also removed, so that the second device region can meet the process requirements. After step S04, a height difference exists between the surface of the gate oxide layer 04 on the shallow trench isolation structure of the first device region and the surface of the shallow trench isolation structure 03 exposed by the second device region, that is, an initial step is formed, and the initial step height h1 is greater than 100nm, which results in thicker thin film stacks at the steps when the polysilicon layer 05 is deposited.
In step S05, the step of the second etching process may include:
step S051, forming an anti-reflection coating 06, wherein the anti-reflection coating 06 covers the polycrystalline silicon layer 05;
step S052, forming a patterned photoresist layer 07, wherein the patterned photoresist layer 07 covers the anti-reflection coating 06 of the first device region;
And step S053, using the patterned photoresist layer 07 as a mask, and sequentially executing an etching process on the anti-reflection coating 06 and the polycrystalline silicon layer 05 to remove the anti-reflection coating 06 and the polycrystalline silicon layer 05 of the second device region. The etching process of this step includes main etching and OE (over etching). Since the step height h1 is larger, the thin film stack at the step is thicker when the polysilicon layer 05 is deposited, and the problem of insufficient over-etching amount occurs by adopting conventional over-etching, the polysilicon residue 051 is easily generated, and if the over-etching amount is additionally increased, the risk of insufficient CD (critical dimension) process window may exist.
The invention provides a preparation method of a semiconductor device, which aims to solve the problems of polysilicon residue or insufficient process window caused by too high step height of a thin film in a transition region of a first device region and a second device region. Referring to fig. 6 to 11, the method of manufacturing the semiconductor device may include the steps of:
step S1, providing a substrate 10, wherein the substrate 10 comprises a first device region and a second device region adjacent to the first device region;
Step S2, forming a groove structure 30 in the substrate 10 of the first device region and extending into the substrate 10 of the second device region;
step S3, forming an isolation oxide layer 40 in the trench structure 30, and etching the isolation oxide layer 40 in the first device region to form a recess 50, wherein the recess 50 is adjacent to the second device region, and the length of the recess 50 is greater than or equal to one eighth of the length of the trench structure 30;
Step S4, a polysilicon gate is formed in the recess 50.
Referring to fig. 6, step S1 is performed to provide a substrate 10. In this embodiment, the substrate 10 may include a first device region and a second device region, the second device region being adjacent to the first device region. The first device region may be a high voltage device region (HV region) and the second device region may be a medium voltage device region (MV region) or a low voltage device region (LV region). For example, in fig. 6, the first device region is an HV region, and the second device region is an MV region. The substrate 10 may be one of monocrystalline silicon, polycrystalline silicon and amorphous silicon, the substrate 10 may also be gallium arsenide, silicon gallium compounds and the like, the substrate 10 may also have a silicon-on-insulator or epitaxial-on-silicon structure, and the substrate 10 may also be other semiconductor materials, which are not listed here. The first device region and the second device region are on the same wafer and are adjacent to each other.
In this embodiment, the method for manufacturing a semiconductor device may further include forming a substrate oxide layer 20 on the substrate 10 before performing the step S2. The substrate oxide layer 20 covers the entire upper surface of the substrate 10. The material of the substrate oxide layer 20 is preferably SiO 2, but is not limited thereto. The substrate oxide layer 20 plays a role of isolating and protecting the substrate 10, and the thickness of the substrate oxide layer 20 is a conventionally set thickness, for example, 100a to 120 a.
Referring to fig. 7, step S2 is performed to form a trench structure 30. In this embodiment, the number of the trench structures 30 is preferably one. The method of forming the trench structure 30 is preferably etching, and more preferably dry etching. The trench structure 30 is located in the substrate 10 of the first device region and extends into the substrate 10 of the second device region, preferably to a length of greater than or equal to 0.48 μm. Further, the length of the trench structure 30 in the first device region is preferably greater than or equal to 0.27 μm, and the length of the trench structure 30 extending into the second device region is preferably greater than or equal to 0.21 μm, so as to ensure that the isolation oxide layer 40 formed later has a sufficient width, thereby having a better isolation effect, and enabling the polysilicon gate 60 to meet the requirement of the first device region. The depth of the trench structure 30 is preferably greater than or equal to 0.31 μm to ensure that the isolation oxide layer 40 formed later has a sufficient thickness to provide a relatively good isolation effect, and also to function as a shallow trench isolation structure with the isolation oxide layer 40, and to reduce the step height of the transition region between the first device region and the second device region. Further, the depth of the trench structure 30 in this embodiment may be set according to the thickness of the isolation oxide layer 40 under the recess 50 and the thickness of the polysilicon gate 60, the length of the trench structure 30 in this embodiment may be set according to the length of the polysilicon gate 60 and the thickness of the isolation oxide layer 40 on the sidewall of the recess 50, and the function of the first device region and the second device region may not be affected by the setting of the trench structure 30.
Referring to fig. 8, step S3 is performed to form an isolation oxide layer 40 in the trench structure 30. The isolation oxide layer 40 may be formed by a thermal oxidation process or ALD (atomic layer deposition), but is not limited thereto. In this step, the isolation oxide layer 40 fills the trench structure 30. The isolation oxide layer 40 is preferably formed of SiO 2, but is not limited thereto. The morphology of SiO 2 in the trench structure 30 is preferably different from the morphology of SiO 2 of the substrate oxide layer 20.
Referring to fig. 9, after forming isolation oxide 40, isolation oxide 40 in the first device region is etched to form recess 50. The etching process of this step is preferably a dry etching process, but is not limited thereto. In this embodiment, the thickness of the isolation oxide layer 40 under the recess 50 (i.e. under the polysilicon gate) is preferably greater than or equal to the required thickness of the breakdown voltage of the first device region, and the thickness of the isolation oxide layer 40 between the sidewall of the recess 50 and the first device region is preferably greater than or equal to 0.21 μm, so as to ensure the isolation effect between the polysilicon gate and the first device region, and avoid breakdown. The thickness of the isolation oxide 40 between the sidewalls of the recess 50 and the second device region is preferably greater than or equal to 0.21 μm to ensure isolation between the polysilicon gate and the second device region. Further, the thickness of the isolation oxide layer 40 between the sidewall of the recess 50 and the second device region may be equal to the width of the shallow trench structure in the second device region in the prior art, the thickness of the isolation oxide layer 40 between the sidewall of the recess 50 and the first device region is equal to the thickness of the isolation oxide layer 40 between the sidewall of the recess 50 and the second device region, the thickness of the isolation oxide layer 40 under the recess 50 may be equal to the thickness required by the breakdown voltage of the first device region, and the length and depth of the recess 50 may be set according to the length and depth of the polysilicon gate required by the first device region. In this embodiment, the recess is located only in the first device region and adjoins the second device region, so that the polysilicon gate subsequently formed adjoins the second device region. I.e. the isolation oxide 40 in the second device region is not etched.
Step S4 is performed to form a polysilicon gate 60 in the recess 50, which may specifically include:
Step S41, depositing a polysilicon layer 60a in the recess 50, wherein the polysilicon layer 60a is also deposited on the substrate 10 of the first device region and the second device region;
Step S42 is to remove the polysilicon layer 60a on the substrate 10 outside the recess 50 by an etching process to form the polysilicon gate 60.
Referring to fig. 10, step S41 is performed to form a polysilicon layer 60a. In the present embodiment, the process of forming the polysilicon layer 60a may be a chemical deposition process, but is not limited thereto. The present embodiment forms the polysilicon layer 60a by depositing a polysilicon material, and the polysilicon layer 60a covers both the first device region and the second device region. Specifically, the polysilicon layer 60a covers the isolation oxide layer 40 and extends over the exposed substrate 10.
Referring to fig. 11, step S42 is performed to remove the polysilicon layer on the substrate outside the recess 50, specifically, to remove the polysilicon layer on the substrate of the second device region and a portion of the first device region. The step of removing the polysilicon layer on the substrate of the second device region by an etching process may include:
step S421, an anti-reflection coating is formed, and the anti-reflection coating covers the polycrystalline silicon layer;
step S422, forming a patterned photoresist layer covering the anti-reflective coating layer over the recesses 50;
step S423, using the patterned photoresist layer as a mask, sequentially performing an etching process on the anti-reflection coating and the polysilicon layer to remove the anti-reflection coating and the polysilicon layer outside the recess 50.
Step S421 is performed to form an anti-reflection coating. The anti-reflection coating completely covers the polysilicon layer. In advanced semiconductor manufacturing processes, a large number of anti-reflection coatings are applied to silicon-based polymers, and the silicon-based polymers are liquid and are formed by high-temperature curing after spin coating. The anti-reflection coating plays a certain role in anti-reflection, can reduce reflected light, is beneficial to the performance of an exposure process, and ensures that the size of a pattern in the photoresist layer is consistent with that of a mask.
Step S422 is performed to form a patterned photoresist layer. Specifically, photoresist material is spin-coated on the anti-reflection coating, soft baking, exposure, baking and development are carried out, a patterned photoresist layer is formed, and the pattern in the photoresist layer exposes the anti-reflection coating. In this embodiment, the patterned photoresist layer would cover the anti-reflective coating over the recesses 50, exposing the anti-reflective coating on the substrate outside of the recesses 50.
Step S423 is performed, where the patterned photoresist layer is used as a mask, and an etching process is sequentially performed on the anti-reflection coating layer and the polysilicon layer to remove the anti-reflection coating layer and the polysilicon layer outside the recess 50, so as to form the polysilicon gate 60. The specific process may be that the patterned photoresist layer is used as a mask to perform dry etching on the anti-reflection coating layer to form a patterned anti-reflection coating layer, and then the patterned anti-reflection coating layer is used as a mask to perform dry etching on the polysilicon layer to form the polysilicon gate 60. The etching of the polysilicon layer in this embodiment may include main etching and over etching. In the embodiment, the sunken polysilicon gate is formed in the first device region, so that the thickness of the film stack in the transition region of the first device region and the second device region is reduced, polysilicon residues can not occur by adopting conventional over etching in the subsequent over etching process, and the problem of insufficient CD process window caused by additionally increasing the over etching amount can be avoided.
In this embodiment, the polysilicon layer 60a outside the recess of the first device region may be removed at the same time as the polysilicon layer 60a of the second device region is removed.
In this embodiment, the polysilicon gate 60 is only located in the first device region, and the length of the polysilicon gate 60 is greater than or equal to one eighth of the length of the trench structure. Further, the length of the polysilicon gate 60 may be specifically set according to the gate length requirement of the first device region, and is preferably greater than or equal to 0.06 μm. The thickness of the polysilicon gate 60 may be set according to the gate thickness requirement of the first device region. The upper surface of the polysilicon gate 60 in this embodiment may be lower than the upper surface of the substrate of the second device region, may be higher than the upper surface of the substrate of the second device region, and may be flush with the upper surface of the substrate of the second device region, preferably the upper surface of the polysilicon gate 60 is flush with the upper surface of the substrate of the second device region, i.e. the polysilicon gate 60 just fills the recess 50.
In order to avoid the residual polysilicon in the prior art, the over-etching amount is generally increased, the problem of insufficient CD process window is unavoidable, and the larger the over-etching amount is, the larger the CD value becomes. Compared with the prior art, the over-etching amount of the over-etching in the embodiment is only the amount commonly used in the semiconductor preparation process, the occurrence of polysilicon residues can be avoided without additionally increasing the over-etching amount, and a sufficient CD process window can be ensured.
In this embodiment, the method for manufacturing the semiconductor device may further include removing the patterned photoresist layer and the patterned anti-reflection coating layer. The present embodiment may perform the step of removing the patterned photoresist layer and the patterned anti-reflective coating layer after the step of forming the polysilicon gate electrode 60, or may perform the step of removing the patterned photoresist layer after the step of forming the patterned anti-reflective coating layer, and then perform the step of removing the patterned anti-reflective coating layer after the step of forming the polysilicon gate electrode 60.
In summary, according to the method for manufacturing the semiconductor device provided by the invention, the sunken polysilicon gate is formed in the first device region, so that the thickness of the film stack of the transition region between the second device region and the first device region is reduced, namely the step height of the second device region and the first device region is reduced, therefore, the residual polysilicon can be avoided without additionally increasing the over-etching amount in the subsequent over-etching process, and meanwhile, the enough CD process window can be ensured. And the semiconductor device has the advantages of reduced device size and more competitive product.
Compared with the prior art, the preparation method of the semiconductor device is easier to realize, can reduce the complexity of the process, can realize obvious economic benefits, can effectively improve the device mismatch phenomenon caused by process program change, increases the manufacturing window of the process, and has excellent compatibility with the prior art.
In addition, the invention also provides a semiconductor device which is prepared by adopting the preparation method of the semiconductor device. Specifically, the semiconductor device may include:
a substrate 10, the substrate 10 comprising a first device region and a second device region adjacent to the first device region;
a trench structure 30, said trench structure 30 being located in the substrate 10 of the first device region and extending into the substrate 10 of the second device region;
an isolation oxide layer 40 located in the trench structure 30;
A recess 50 in the isolation oxide 40 of the first device region and adjacent to the second device region, the recess 50 having a length greater than or equal to one eighth the length of the trench structure 30;
a polysilicon gate 60 is located in the recess 50.
The semiconductor device of the present embodiment may further include a substrate oxide layer 20, where the substrate oxide layer 20 covers the upper surface of the substrate 10 to protect the substrate 10.
The semiconductor device of the present invention may be an LCD driver, but is not limited thereto. The semiconductor device provided by the invention forms the sunken polycrystalline silicon grid in the first device region, so that the thickness of the film stack of the transition region of the second device region and the first device region is reduced, namely the step height of the second device region and the first device region is reduced, therefore, the polycrystalline silicon residue can be avoided without additionally increasing the over etching amount in the subsequent over etching process, and meanwhile, the enough CD process window can be ensured. Meanwhile, the device size of the semiconductor device is reduced, and the product is more competitive.
In addition, it will be understood that while the invention has been described in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It is also to be understood that this invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may vary. It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means a reference to one or more steps, and may include sub-steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood as having the definition of a logical "or" rather than a logical exclusive or "unless the context clearly indicates the contrary. Structures described herein will be understood to also refer to the functional equivalents of such structures. Language that may be construed as approximate should be construed unless the context clearly indicates the contrary.
Claims (9)
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