CN118737823A - A method for thinning a semiconductor structure - Google Patents
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- CN118737823A CN118737823A CN202411205903.3A CN202411205903A CN118737823A CN 118737823 A CN118737823 A CN 118737823A CN 202411205903 A CN202411205903 A CN 202411205903A CN 118737823 A CN118737823 A CN 118737823A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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Abstract
本发明涉及一种半导体结构的减薄方法。半导体结构的减薄方法包括：提供半导体结构；半导体结构包括正面和待减薄的背面；提供第一基板；将半导体结构的正面与第一基板一侧键合，对半导体结构的背面进行减薄；提供第二基板，第二基板中具有第一吸附孔；在第二基板的一侧表面设置缓冲膜，缓冲膜中具有第二吸附孔；利用第二基板从缓冲膜一侧吸附半导体结构；吸附状态下，第一吸附孔与第二吸附孔至少部分贯通；将半导体结构的正面与第一基板解键合。本发明提供的半导体结构的减薄方法可以减少半导体结构在解键合过程中出现的缺陷和划痕。
The present invention relates to a method for thinning a semiconductor structure. The method for thinning a semiconductor structure comprises: providing a semiconductor structure; the semiconductor structure comprises a front side and a back side to be thinned; providing a first substrate; bonding the front side of the semiconductor structure to one side of the first substrate, and thinning the back side of the semiconductor structure; providing a second substrate, wherein the second substrate has a first adsorption hole; arranging a buffer film on one side surface of the second substrate, wherein the buffer film has a second adsorption hole; using the second substrate to adsorb the semiconductor structure from one side of the buffer film; in the adsorption state, the first adsorption hole and the second adsorption hole are at least partially connected; and debonding the front side of the semiconductor structure from the first substrate. The method for thinning a semiconductor structure provided by the present invention can reduce defects and scratches that occur in the semiconductor structure during the debonding process.
Description
技术领域Technical Field
本发明涉及半导体技术领域，具体涉及一种半导体结构的减薄方法。The present invention relates to the field of semiconductor technology, and in particular to a method for thinning a semiconductor structure.
背景技术Background Art
在芯片制造的晶圆工艺加工过程中，为了防止晶圆在加工过程中破损，需要晶圆具有较厚的厚度，来保持一定的机械强度，对于三五族化合物半导体晶圆，厚度一般在350μm~700μm。在晶圆的工艺加工完成后，为了方便切割或解理成小的单个芯片，需要将晶圆减薄到100μm左右，以降低其机械强度。但是较低的机械强度，容易导致晶圆在减薄过程中破裂。所以，通常三五族化合物半导体晶圆在减薄过程中需要将晶圆的正面贴附在硬质基板上，称为键合。然后将其放入工装夹具中，使用标准的研磨设备进行研磨，使用标准的抛光设备进行抛光。晶圆经过抛光后，其背面十分光滑，没有明显的缺陷和划痕。最后，需要将晶圆从硬质基板上分离，称为解键合。解键合的过程，是将晶圆背面吸附在另一个硬质基板上，该硬质基板具有多孔结构，比较粗糙。之后通过加热的方式，将键合的粘合层融化，然后用外力推拉晶圆正面的硬质基板，使之和正面的硬质基板脱离。在推拉过程中，光滑的晶圆背面难免会和粗糙的硬质基板发生摩擦。由于三五族晶圆质地较为柔软，该过程会更容易导致晶圆背面出现较多的划痕和缺陷，导致工艺良率降低。因此在硬质基板表面设置一层硬度较小缓冲膜，第二基板和缓冲膜的叠加孔隙率会影响真空系统对半导体结构的固定，同时也会影响缓冲膜的表面粗糙度，孔隙率过小导致真空系统无法对半导体结构实施有效固定，孔隙率太大又会导致缓冲膜表面粗糙度的增加，都会对半导体结构产生划伤。During the wafer processing process of chip manufacturing, in order to prevent the wafer from being damaged during processing, the wafer needs to have a thicker thickness to maintain a certain mechanical strength. For III-V compound semiconductor wafers, the thickness is generally 350μm~700μm. After the wafer processing is completed, in order to facilitate cutting or cleavage into small individual chips, the wafer needs to be thinned to about 100μm to reduce its mechanical strength. However, the lower mechanical strength can easily cause the wafer to break during the thinning process. Therefore, during the thinning process of III-V compound semiconductor wafers, the front side of the wafer needs to be attached to a hard substrate, which is called bonding. Then put it into a fixture, grind it with standard grinding equipment, and polish it with standard polishing equipment. After polishing, the back of the wafer is very smooth without obvious defects and scratches. Finally, the wafer needs to be separated from the hard substrate, which is called debonding. The debonding process is to adsorb the back of the wafer on another hard substrate, which has a porous structure and is relatively rough. After that, the bonded adhesive layer is melted by heating, and then the hard substrate on the front of the wafer is pushed and pulled by external force to separate it from the hard substrate on the front. During the pushing and pulling process, the smooth back of the wafer will inevitably rub against the rough hard substrate. Since III-V wafers are relatively soft, this process will more easily cause more scratches and defects on the back of the wafer, resulting in a reduction in process yield. Therefore, a layer of buffer film with lower hardness is set on the surface of the hard substrate. The superimposed porosity of the second substrate and the buffer film will affect the fixation of the semiconductor structure by the vacuum system, and will also affect the surface roughness of the buffer film. If the porosity is too small, the vacuum system will not be able to effectively fix the semiconductor structure. If the porosity is too large, the surface roughness of the buffer film will increase, which will cause scratches on the semiconductor structure.
因此需要一种半导体结构的减薄方法，在解键合过程中保护半导体结构的背面，从而减少半导体结构在解键合过程中出现的缺陷和划痕。Therefore, a method for thinning a semiconductor structure is needed to protect the back side of the semiconductor structure during the debonding process, thereby reducing defects and scratches on the semiconductor structure during the debonding process.
发明内容Summary of the invention
因此，本发明提供一种半导体结构的减薄方法，以解决现有技术中半导体结构在减薄过程中解键合后易产生缺陷和划痕的问题。Therefore, the present invention provides a method for thinning a semiconductor structure to solve the problem in the prior art that defects and scratches are easily generated in the semiconductor structure after debonding during the thinning process.
本发明提供一种半导体结构的减薄方法，包括：The present invention provides a method for thinning a semiconductor structure, comprising:
提供半导体结构；所述半导体结构包括正面和待减薄的背面；Providing a semiconductor structure; the semiconductor structure comprises a front side and a back side to be thinned;
提供第一基板；将所述半导体结构的正面与所述第一基板一侧键合，对所述半导体结构的背面进行减薄；Providing a first substrate; bonding the front surface of the semiconductor structure to one side of the first substrate, and thinning the back surface of the semiconductor structure;
提供第二基板，所述第二基板中具有第一吸附孔；在所述第二基板的一侧表面设置缓冲膜，所述缓冲膜中具有第二吸附孔；Providing a second substrate, wherein the second substrate has a first adsorption hole; disposing a buffer film on one side surface of the second substrate, wherein the buffer film has a second adsorption hole;
利用所述第二基板从所述缓冲膜一侧吸附所述半导体结构；吸附状态下，所述第一吸附孔与所述第二吸附孔至少部分贯通；Adsorbing the semiconductor structure from one side of the buffer film using the second substrate; in the adsorbed state, the first adsorption hole and the second adsorption hole are at least partially connected;
将所述半导体结构的正面与所述第一基板解键合。The front side of the semiconductor structure is debonded from the first substrate.
可选的，所述利用所述第二基板从所述缓冲膜一侧吸附所述半导体结构的步骤，包括：Optionally, the step of using the second substrate to absorb the semiconductor structure from one side of the buffer film includes:
在所述第二基板背向所述缓冲膜的一侧设置真空吸附单元，所述真空吸附单元通过所述第一吸附孔和所述第二吸附孔抽气，提供负压，使得所述半导体结构被所述第二基板吸附固定。A vacuum adsorption unit is disposed on a side of the second substrate facing away from the buffer film. The vacuum adsorption unit evacuates air through the first adsorption holes and the second adsorption holes to provide negative pressure, so that the semiconductor structure is adsorbed and fixed by the second substrate.
可选的，所述缓冲膜包括缓冲主体膜和支撑膜；Optionally, the buffer film includes a buffer main body film and a support film;
所述在所述第二基板的一侧表面设置缓冲膜的步骤中，所述支撑膜位于所述缓冲主体膜和所述第二基板之间；所述缓冲主体膜位于所述支撑膜背向所述第二基板的一侧。In the step of providing a buffer film on one side surface of the second substrate, the support film is located between the buffer main film and the second substrate; the buffer main film is located on a side of the support film facing away from the second substrate.
可选的，所述缓冲膜材料的熔点为150℃~400℃；Optionally, the melting point of the buffer film material is 150° C. to 400° C.;
所述缓冲膜的厚度为120μm~130μm；The thickness of the buffer film is 120 μm to 130 μm;
所述缓冲主体膜的厚度为15μm~20μm，所述支撑膜的厚度为105μm~110μm；The thickness of the buffer main film is 15 μm to 20 μm, and the thickness of the support film is 105 μm to 110 μm;
所述缓冲主体膜的材料包括聚四氟乙烯、聚醚砜或膨体聚四氟乙烯。The material of the buffer main body film includes polytetrafluoroethylene, polyethersulfone or expanded polytetrafluoroethylene.
可选的，所述第二基板与所述缓冲膜之间的叠加孔隙率大于21.5%。Optionally, the overlapping porosity between the second substrate and the buffer film is greater than 21.5%.
可选的，所述第二基板的孔隙率为34.6%~45.0%；Optionally, the porosity of the second substrate is 34.6% to 45.0%;
所述缓冲膜的孔隙率为62.0%~64.9%；The porosity of the buffer film is 62.0% to 64.9%;
所述第一吸附孔的孔径为10.7μm~15μm；所述第二吸附孔的孔径为1μm~3μm；The pore size of the first adsorption hole is 10.7 μm to 15 μm; the pore size of the second adsorption hole is 1 μm to 3 μm;
所述缓冲膜与所述半导体结构接触的一侧表面粗糙度小于478nm。The surface roughness of a side of the buffer film in contact with the semiconductor structure is less than 478 nm.
可选的，所述第二基板与所述缓冲膜之间的叠加孔隙率为28.1%；Optionally, the superposition porosity between the second substrate and the buffer film is 28.1%;
所述第二基板的孔隙率为45.1%；The porosity of the second substrate is 45.1%;
所述缓冲膜的孔隙率为62.3%；The porosity of the buffer film is 62.3%;
所述第一吸附孔的孔径为11.7μm；所述第二吸附孔的孔径为1μm；The pore size of the first adsorption hole is 11.7 μm; the pore size of the second adsorption hole is 1 μm;
所述缓冲膜与所述半导体结构接触的一侧表面粗糙度为396nm。The surface roughness of the side of the buffer film in contact with the semiconductor structure is 396 nm.
可选的，所述将所述半导体结构的正面与所述第一基板一侧键合的步骤之前，还包括：Optionally, before the step of bonding the front surface of the semiconductor structure to one side of the first substrate, the method further includes:
在所述半导体结构的正面形成粘合层，或在所述第一基板朝向所述半导体结构的一侧表面形成粘合层；forming an adhesive layer on the front surface of the semiconductor structure, or forming an adhesive layer on a surface of the first substrate facing the semiconductor structure;
将所述半导体结构的正面与所述第一基板一侧键合之后，所述粘合层位于第一基板和半导体结构的正面之间。After the front surface of the semiconductor structure is bonded to one side of the first substrate, the adhesive layer is located between the first substrate and the front surface of the semiconductor structure.
可选的，所述将所述半导体结构的正面与所述第一基板解键合的步骤包括：Optionally, the step of debonding the front surface of the semiconductor structure from the first substrate includes:
加热所述粘合层并施加外力以使所述半导体结构的正面与所述第一基板分离。The adhesive layer is heated and an external force is applied to separate the front surface of the semiconductor structure from the first substrate.
可选的，所述将所述半导体结构的正面与所述第一基板解键合的步骤之后，还包括：Optionally, after the step of debonding the front surface of the semiconductor structure from the first substrate, the method further includes:
将所述第二基板与所述缓冲膜分离，去除所述第二基板；separating the second substrate from the buffer film, and removing the second substrate;
采用溶液浸泡工艺去除所述缓冲膜；Removing the buffer film by a solution immersion process;
采用溶液浸泡工艺去除所述粘合层。The adhesive layer is removed by a solution soaking process.
本发明的技术方案，具有如下优点：The technical solution of the present invention has the following advantages:
（1）本发明提供的半导体结构的减薄方法，对半导体结构的背面进行减薄之后，将半导体结构放置在缓冲膜表面且被第二基板吸附，再将半导体结构的正面与第一基板解键合，避免了在解键合的过程中半导体背面与第二基板的直接接触；在推拉第一基板的过程中，缓冲膜对半导体结构的背面起到了保护作用，减少了半导体结构在解键合过程中出现的缺陷和划痕。(1) The semiconductor structure thinning method provided by the present invention, after thinning the back side of the semiconductor structure, places the semiconductor structure on the surface of the buffer film and is adsorbed by the second substrate, and then debonds the front side of the semiconductor structure from the first substrate, thereby avoiding direct contact between the back side of the semiconductor and the second substrate during the debonding process; in the process of pushing and pulling the first substrate, the buffer film protects the back side of the semiconductor structure, thereby reducing defects and scratches on the semiconductor structure during the debonding process.
（2）本发明提供的半导体结构的减薄方法中，由于缓冲膜的第二吸附孔与第二基板的第一吸附孔之间具有很好的贯通性，提供充足的负压吸附半导体结构，避免解键合过程中产生相对滑动造成半导体结构损伤。(2) In the semiconductor structure thinning method provided by the present invention, since the second adsorption holes of the buffer film and the first adsorption holes of the second substrate have good connectivity, sufficient negative pressure is provided to adsorb the semiconductor structure, thereby avoiding relative sliding during the debonding process that may cause damage to the semiconductor structure.
（3）本发明提供的半导体结构的减薄方法中，规定了解键合工艺中的技术参数值的最优范围，包括缓冲膜与第二基板之间的叠加孔隙率大于21.5%，缓冲膜的表面粗糙度小于478nm，缓冲膜的第二吸附孔的孔径为1μm~3μm。在这些范围内，可以提高半导体结构吸附真空的能力，减小半导体结构和缓冲膜之间相互摩擦力，使得第二基板紧固地吸附半导体结构，从而在半导体结构与第一基板的解键合过程中保护半导体结构不受损伤。(3) In the semiconductor structure thinning method provided by the present invention, the optimal range of technical parameter values in the debonding process is specified, including the stacking porosity between the buffer film and the second substrate being greater than 21.5%, the surface roughness of the buffer film being less than 478nm, and the aperture of the second adsorption hole of the buffer film being 1μm~3μm. Within these ranges, the vacuum adsorption capability of the semiconductor structure can be improved, the mutual friction between the semiconductor structure and the buffer film can be reduced, and the second substrate can firmly adsorb the semiconductor structure, thereby protecting the semiconductor structure from damage during the debonding process between the semiconductor structure and the first substrate.
（4）本发明提供的半导体结构的减薄方法中，缓冲膜材料可以耐受150℃~400℃高温，基本上覆盖市场上常用的键合胶或键合蜡的熔点温度，在解键合过程中，避免了缓冲膜本身的分解或变性对半导体结构的污染。(4) In the semiconductor structure thinning method provided by the present invention, the buffer film material can withstand high temperatures of 150°C to 400°C, which basically covers the melting point temperature of the bonding glue or bonding wax commonly used in the market. During the debonding process, the decomposition or denaturation of the buffer film itself is avoided to contaminate the semiconductor structure.
（5）本发明提供的半导体结构的减薄方法中，缓冲膜为聚四氟乙烯、聚醚砜或膨体聚四氟乙烯有机材料。由于半导体结构的背面相对较软，而聚四氟乙烯、聚醚砜或膨体聚四氟乙烯作为高分子聚合物材料，具有低硬度、强塑性、高延展性的特点，在第二基板和半导体结构间增加一层缓冲膜，可以减小对金属表面的划伤。(5) In the semiconductor structure thinning method provided by the present invention, the buffer film is an organic material of polytetrafluoroethylene, polyethersulfone or expanded polytetrafluoroethylene. Since the back side of the semiconductor structure is relatively soft, and polytetrafluoroethylene, polyethersulfone or expanded polytetrafluoroethylene, as a high molecular polymer material, has the characteristics of low hardness, strong plasticity and high ductility, adding a buffer film between the second substrate and the semiconductor structure can reduce scratches on the metal surface.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本发明具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
图1为本发明一实施例的一种半导体结构的减薄方法的流程示意图；FIG1 is a schematic flow chart of a method for thinning a semiconductor structure according to an embodiment of the present invention;
图2为本发明一实施例的一种半导体结构的减薄方法的具体流程示意图；FIG2 is a schematic diagram of a specific process of a semiconductor structure thinning method according to an embodiment of the present invention;
图3-图9为本发明一实施例的一种半导体结构的减薄方法的各步骤的结构示意图；3 to 9 are schematic structural diagrams of various steps of a method for thinning a semiconductor structure according to an embodiment of the present invention;
图10和图11为本发明对比例1提供的相关实验数据；Figures 10 and 11 are relevant experimental data provided by Comparative Example 1 of the present invention;
图12为本发明对比例2中叠加孔隙率为27.9%条件下减薄后半导体结构的表面形貌图；FIG12 is a surface morphology of a semiconductor structure after thinning under the condition of a superimposed porosity of 27.9% in Comparative Example 2 of the present invention;
图13和图14为本发明对比例3中缓冲膜表面粗糙度为843nm和1429nm条件下减薄后半导体结构的表面形貌图。13 and 14 are surface morphology images of the semiconductor structure after thinning under the condition that the surface roughness of the buffer film is 843 nm and 1429 nm in Comparative Example 3 of the present invention.
附图标记说明：Description of reference numerals:
1-半导体结构；2-粘合层；3-第一基板；4-支撑膜；5-缓冲主体膜；6-缓冲膜；7-第二基板。1-semiconductor structure; 2-adhesive layer; 3-first substrate; 4-support film; 5-buffer main film; 6-buffer film; 7-second substrate.
具体实施方式DETAILED DESCRIPTION
为解决现有技术中半导体结构在减薄过程中解键合后易产生缺陷和划痕的问题，本发明提供一种半导体结构的减薄方法，包括：提供半导体结构；所述半导体结构包括正面和待减薄的背面；提供第一基板；将所述半导体结构的正面与所述第一基板一侧键合，对所述半导体结构的背面进行减薄；提供第二基板，所述第二基板中具有第一吸附孔；在所述第二基板的一侧表面设置缓冲膜，所述缓冲膜中具有第二吸附孔；利用所述第二基板从所述缓冲膜一侧吸附所述半导体结构；吸附状态下，所述第一吸附孔与所述第二吸附孔至少部分贯通；将所述半导体结构的正面与所述第一基板解键合。In order to solve the problem in the prior art that semiconductor structures are prone to defects and scratches after debonding during the thinning process, the present invention provides a method for thinning a semiconductor structure, comprising: providing a semiconductor structure; the semiconductor structure comprising a front side and a back side to be thinned; providing a first substrate; bonding the front side of the semiconductor structure to one side of the first substrate, and thinning the back side of the semiconductor structure; providing a second substrate, wherein the second substrate has a first adsorption hole; providing a buffer film on one side surface of the second substrate, wherein the buffer film has a second adsorption hole; using the second substrate to adsorb the semiconductor structure from one side of the buffer film; in the adsorption state, the first adsorption hole and the second adsorption hole are at least partially connected; and debonding the front side of the semiconductor structure from the first substrate.
下面将结合附图对本发明的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。在本发明的描述中，需要说明的是，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
实施例1Example 1
如图1所示，本实施例提供一种半导体结构的减薄方法，包括步骤S101-S105。As shown in FIG. 1 , this embodiment provides a method for thinning a semiconductor structure, including steps S101 - S105 .
S101，提供半导体结构；所述半导体结构包括正面和待减薄的背面。S101, providing a semiconductor structure; the semiconductor structure comprises a front side and a back side to be thinned.
具体实施时，半导体结构可以为晶圆，例如三五族化合物半导体晶圆。半导体结构的厚度为350μm~700μm，例如350μm、500μm、600μm、700μm等。半导体结构在减薄之前的厚度较厚，以保持一定的机械强度。In a specific implementation, the semiconductor structure may be a wafer, such as a III-V compound semiconductor wafer. The thickness of the semiconductor structure is 350 μm to 700 μm, such as 350 μm, 500 μm, 600 μm, 700 μm, etc. The semiconductor structure is thicker before thinning to maintain a certain mechanical strength.
S102，提供第一基板；将所述半导体结构的正面与所述第一基板一侧键合，对所述半导体结构的背面进行减薄。S102, providing a first substrate; bonding the front side of the semiconductor structure to one side of the first substrate, and thinning the back side of the semiconductor structure.
具体实施时，第一基板可以为蓝宝石、碳化硅等。在一个实施例中，所述半导体结构减薄至90μm~110μm，例如90μm、95μm、100μm等。对所述半导体结构的背面进行减薄的工艺包括机械研磨和化学抛光工艺。In specific implementation, the first substrate may be sapphire, silicon carbide, etc. In one embodiment, the semiconductor structure is thinned to 90 μm to 110 μm, such as 90 μm, 95 μm, 100 μm, etc. The process of thinning the back side of the semiconductor structure includes mechanical grinding and chemical polishing.
S103，提供第二基板，所述第二基板中具有第一吸附孔；在所述第二基板的一侧表面设置缓冲膜，所述缓冲膜中具有第二吸附孔。S103, providing a second substrate, wherein the second substrate has first adsorption holes; and disposing a buffer film on one side surface of the second substrate, wherein the buffer film has second adsorption holes.
S104，利用所述第二基板从所述缓冲膜一侧吸附所述半导体结构；吸附状态下，所述第一吸附孔与所述第二吸附孔至少部分贯通。S104, using the second substrate to adsorb the semiconductor structure from one side of the buffer film; in the adsorbed state, the first adsorption hole and the second adsorption hole are at least partially connected.
S105，将所述半导体结构的正面与所述第一基板解键合。S105 , debonding the front side of the semiconductor structure from the first substrate.
具体实施时，将所述半导体结构放置在所述缓冲膜背向所述第二基板的一侧表面且被所述第二基板吸附之后，将所述半导体结构的正面与所述第一基板解键合。In a specific implementation, after the semiconductor structure is placed on a surface of the buffer film facing away from the second substrate and adsorbed by the second substrate, the front surface of the semiconductor structure is debonded from the first substrate.
本发明实施例提供的半导体结构的减薄方法，对半导体结构的背面进行减薄之后，将半导体结构放置在缓冲膜表面且被第二基板吸附，再将半导体结构的正面与第一基板解键合，避免了在解键合的过程中半导体背面与第二基板的直接接触；在推拉第一基板的过程中，缓冲膜对半导体结构的背面起到了保护作用，减少了半导体结构在解键合过程中出现的缺陷和划痕。The semiconductor structure thinning method provided in an embodiment of the present invention thins the back side of the semiconductor structure, places the semiconductor structure on the surface of a buffer film and is adsorbed by a second substrate, and then debonds the front side of the semiconductor structure from the first substrate, thereby avoiding direct contact between the back side of the semiconductor and the second substrate during the debonding process; in the process of pushing and pulling the first substrate, the buffer film protects the back side of the semiconductor structure, thereby reducing defects and scratches on the semiconductor structure during the debonding process.
进一步的，在一些实施例中，所述利用所述第二基板从所述缓冲膜一侧吸附所述半导体结构的步骤，包括：Furthermore, in some embodiments, the step of using the second substrate to absorb the semiconductor structure from one side of the buffer film includes:
在所述第二基板背向所述缓冲膜的一侧设置真空吸附单元，所述真空吸附单元通过所述第一吸附孔和所述第二吸附孔抽气，提供负压，使得所述半导体结构被所述第二基板吸附固定。A vacuum adsorption unit is disposed on a side of the second substrate facing away from the buffer film. The vacuum adsorption unit evacuates air through the first adsorption holes and the second adsorption holes to provide negative pressure, so that the semiconductor structure is adsorbed and fixed by the second substrate.
具体实施时，由于缓冲膜的第二吸附孔与第二基板的第一吸附孔之间具有很好的贯通性，真空吸附单元提供充足的负压可以紧固地吸附半导体结构，避免解键合过程中产生相对滑动造成半导体结构损伤。In specific implementation, since the second adsorption holes of the buffer film and the first adsorption holes of the second substrate have good connectivity, the vacuum adsorption unit provides sufficient negative pressure to firmly adsorb the semiconductor structure, thereby avoiding damage to the semiconductor structure caused by relative sliding during the debonding process.
进一步的，在一些实施例中，所述缓冲膜包括缓冲主体膜和支撑膜；Further, in some embodiments, the buffer film includes a buffer body film and a support film;
所述在所述第二基板的一侧表面设置缓冲膜的步骤中，所述支撑膜位于所述缓冲主体膜和所述第二基板之间；所述缓冲主体膜位于所述支撑膜背向所述第二基板的一侧。In the step of providing a buffer film on one side surface of the second substrate, the support film is located between the buffer main film and the second substrate; the buffer main film is located on a side of the support film facing away from the second substrate.
具体实施时，缓冲膜包括缓冲主体膜和支撑膜，缓冲主体膜覆盖在支撑膜表面，其中，主体膜较薄，厚度为15μm~20μm，例如15μm、18μm、20μm等；支撑膜较厚，厚度为105μm~110μm，例如105μm、108μm、110μm等。第二吸附孔同时贯通缓冲主体膜和支撑膜两层，解键合过程中直接和晶圆背面接触的是主体膜的表面。In a specific implementation, the buffer film includes a buffer main film and a support film, wherein the buffer main film covers the surface of the support film, wherein the main film is relatively thin, with a thickness of 15μm to 20μm, such as 15μm, 18μm, 20μm, etc.; the support film is relatively thick, with a thickness of 105μm to 110μm, such as 105μm, 108μm, 110μm, etc. The second adsorption hole penetrates both the buffer main film and the support film, and the surface of the main film directly contacts the back of the wafer during the debonding process.
进一步的，在一些实施例中，所述缓冲膜材料的熔点为150℃~400℃；Further, in some embodiments, the melting point of the buffer film material is 150°C to 400°C;
所述缓冲膜的厚度为120μm~130μm，例如120μm、125μm、130μm；The thickness of the buffer film is 120 μm to 130 μm, for example, 120 μm, 125 μm, 130 μm;
所述缓冲主体膜的厚度为15μm~20μm，例如15μm、18μm、20μm；所述支撑膜的厚度为105μm~110μm，例如105μm、107μm、110μm；The thickness of the buffer main film is 15 μm to 20 μm, for example, 15 μm, 18 μm, 20 μm; the thickness of the support film is 105 μm to 110 μm, for example, 105 μm, 107 μm, 110 μm;
所述缓冲主体膜的材料包括聚四氟乙烯、聚醚砜或膨体聚四氟乙烯。The material of the buffer main body film includes polytetrafluoroethylene, polyethersulfone or expanded polytetrafluoroethylene.
具体实施时，由于缓冲膜材料可以耐受150℃~400℃的高温，基本上覆盖市场上常用的键合胶或键合蜡的熔点温度，在解键合过程中，避免了缓冲膜本身的分解或变性对半导体结构的污染。In specific implementation, since the buffer film material can withstand high temperatures of 150°C to 400°C, which basically covers the melting point temperature of commonly used bonding glues or bonding waxes on the market, the decomposition or denaturation of the buffer film itself is avoided to contaminate the semiconductor structure during the debonding process.
在一些实施例中，缓冲主体膜的材料包括聚四氟乙烯、聚醚砜或膨体聚四氟乙烯。由于半导体结构的背面一般为Ti-Pt-Au合金，相对较软（莫氏硬度仅有2.5级—3级）。而聚四氟乙烯、聚醚砜或膨体聚四氟乙烯作为高分子聚合物材料，具有低硬度、强塑性、高延展性的特点，在第二基板和半导体结构间增加一层缓冲膜，可以减小对金属表面的划伤。In some embodiments, the material of the buffer main film includes polytetrafluoroethylene, polyethersulfone or expanded polytetrafluoroethylene. Since the back of the semiconductor structure is generally Ti-Pt-Au alloy, it is relatively soft (Mohs hardness is only 2.5-3). Polytetrafluoroethylene, polyethersulfone or expanded polytetrafluoroethylene, as a high molecular polymer material, has the characteristics of low hardness, strong plasticity and high ductility. Adding a buffer film between the second substrate and the semiconductor structure can reduce scratches on the metal surface.
在一个示例中，所述缓冲膜的厚度为130μm，所述缓冲主体膜的厚度为20μm，所述支撑膜的厚度为110μm。In one example, the buffer film has a thickness of 130 μm, the buffer main film has a thickness of 20 μm, and the support film has a thickness of 110 μm.
此外，缓冲膜的直径一般根据半导体结构的大小选择，例如半导体结构的直径为6英寸，缓冲膜的直径为150mm。In addition, the diameter of the buffer film is generally selected according to the size of the semiconductor structure. For example, if the diameter of the semiconductor structure is 6 inches, the diameter of the buffer film is 150 mm.
进一步的，在一些实施例中，所述第一吸附孔与所述第二吸附孔之间的叠加孔隙率大于21.5%。Furthermore, in some embodiments, the superimposed porosity between the first adsorption pores and the second adsorption pores is greater than 21.5%.
具体实施时，所述第二基板与所述缓冲膜之间的叠加孔隙率=缓冲膜孔隙率×第二基板孔隙率。当叠加孔隙率大于21.5%时，第二吸附孔与第一吸附孔之间具有很好的贯通性，可以提高半导体结构吸附真空的能力，使得第二基板紧固地吸附半导体结构，避免解键合过程中产生相对滑动造成半导体结构损伤。In a specific implementation, the superposition porosity between the second substrate and the buffer film = the buffer film porosity × the second substrate porosity. When the superposition porosity is greater than 21.5%, the second adsorption hole and the first adsorption hole have good connectivity, which can improve the ability of the semiconductor structure to adsorb vacuum, so that the second substrate can firmly adsorb the semiconductor structure, avoiding relative sliding during the debonding process and causing damage to the semiconductor structure.
进一步的，在一些实施例中，所述第二基板的孔隙率为34.6%~45.0%；Further, in some embodiments, the porosity of the second substrate is 34.6% to 45.0%;
所述缓冲膜的孔隙率为62.0%~64.9%；The porosity of the buffer film is 62.0% to 64.9%;
所述第一吸附孔的孔径为10.7μm~15μm；所述第二吸附孔的孔径为1μm~3μm；The pore size of the first adsorption hole is 10.7 μm to 15 μm; the pore size of the second adsorption hole is 1 μm to 3 μm;
所述缓冲膜与所述半导体结构接触的一侧表面粗糙度小于478nm。The surface roughness of a side of the buffer film in contact with the semiconductor structure is less than 478 nm.
具体实施时，当缓冲膜的表面粗糙度小于478nm，缓冲膜的第二吸附孔的孔径为1μm~3μm时，可以减小半导体结构和缓冲膜之间相互摩擦力，使得第二基板紧固地吸附半导体结构，从而在半导体结构与第一基板的解键合过程中保护半导体结构不受损伤。In a specific implementation, when the surface roughness of the buffer film is less than 478 nm and the pore size of the second adsorption hole of the buffer film is 1 μm to 3 μm, the mutual friction between the semiconductor structure and the buffer film can be reduced, so that the second substrate can firmly adsorb the semiconductor structure, thereby protecting the semiconductor structure from damage during the debonding process of the semiconductor structure and the first substrate.
进一步的，在一些实施例中，所述第二基板与所述缓冲膜之间的叠加孔隙率为28.1%；Further, in some embodiments, the stacking porosity between the second substrate and the buffer film is 28.1%;
所述第二基板的孔隙率为45.1%；The porosity of the second substrate is 45.1%;
所述缓冲膜的孔隙率为62.3%；The porosity of the buffer film is 62.3%;
所述第一吸附孔的孔径为11.7μm；所述第二吸附孔的孔径为1μm；The pore size of the first adsorption hole is 11.7 μm; the pore size of the second adsorption hole is 1 μm;
所述缓冲膜与所述半导体结构接触的一侧表面粗糙度为396nm。The surface roughness of the side of the buffer film in contact with the semiconductor structure is 396 nm.
进一步的，在一些实施例中，所述将所述半导体结构的正面与所述第一基板一侧键合的步骤之前，还包括：Furthermore, in some embodiments, before the step of bonding the front surface of the semiconductor structure to one side of the first substrate, the step further includes:
在所述半导体结构的正面形成粘合层，或在所述第一基板朝向所述半导体结构的一侧表面形成粘合层；forming an adhesive layer on the front surface of the semiconductor structure, or forming an adhesive layer on a surface of the first substrate facing the semiconductor structure;
将所述半导体结构的正面与所述第一基板一侧键合之后，所述粘合层位于第一基板和半导体结构的正面之间。After the front surface of the semiconductor structure is bonded to one side of the first substrate, the adhesive layer is located between the first substrate and the front surface of the semiconductor structure.
进一步的，在一些实施例中，所述将所述半导体结构的正面与所述第一基板解键合的步骤包括：Furthermore, in some embodiments, the step of debonding the front surface of the semiconductor structure from the first substrate includes:
加热所述粘合层并施加外力以使所述半导体结构的正面与所述第一基板分离。The adhesive layer is heated and an external force is applied to separate the front surface of the semiconductor structure from the first substrate.
具体实施时，在推拉所述第一基板的过程中，所述缓冲膜对所述半导体结构的背面起到了保护作用，减少了半导体结构在解键合过程中出现的缺陷和划痕。In a specific implementation, during the process of pushing and pulling the first substrate, the buffer film protects the back surface of the semiconductor structure, thereby reducing defects and scratches on the semiconductor structure during the debonding process.
在一个实施例中，将所述半导体结构的正面与所述第一基板解键合的过程中，加热所述粘合层至150±3℃，采用推片手臂施加外力，水平推动第一基板，以使所述半导体结构与所述第一基板分离。In one embodiment, during the process of debonding the front side of the semiconductor structure from the first substrate, the adhesive layer is heated to 150±3° C., and an external force is applied by a push arm to horizontally push the first substrate to separate the semiconductor structure from the first substrate.
进一步的，在一些实施例中，所述将所述半导体结构的正面与所述第一基板解键合的步骤之后，还包括：Furthermore, in some embodiments, after the step of debonding the front surface of the semiconductor structure from the first substrate, the method further includes:
将所述第二基板与所述缓冲膜分离，去除所述第二基板；separating the second substrate from the buffer film, and removing the second substrate;
采用溶液浸泡工艺去除所述缓冲膜；Removing the buffer film by a solution immersion process;
采用溶液浸泡工艺去除所述粘合层。The adhesive layer is removed by a solution soaking process.
具体实施时，通过关闭真空吸附单元，关闭负压，所述第二基板不再吸附所述半导体结构，可以使所述半导体结构能与所述第二基板分离。In a specific implementation, by closing the vacuum adsorption unit and the negative pressure, the second substrate no longer adsorbs the semiconductor structure, so that the semiconductor structure can be separated from the second substrate.
在一些实施例中，采用溶液浸泡工艺去除所述缓冲膜的步骤中，可以将所述缓冲膜与所述半导体结构放入具有有机溶液的标准花篮中进行加热浸泡使所述缓冲膜与所述半导体结构分离。所述有机溶液的温度在20℃~26℃，所述有机溶液可以是丙酮溶液。In some embodiments, in the step of removing the buffer film by a solution immersion process, the buffer film and the semiconductor structure can be placed in a standard basket with an organic solution for heating and immersion to separate the buffer film from the semiconductor structure. The temperature of the organic solution is 20° C. to 26° C., and the organic solution can be an acetone solution.
采用溶液浸泡工艺去除所述粘合层的步骤中，可以先用45℃~50℃丙酮溶液浸泡30min，其次用35~40℃异丙醇浸泡15min，最后用纯水溢流浸泡5min，去除所属粘合层。In the step of removing the adhesive layer by solution immersion process, the adhesive layer can be removed by first immersing in 45°C~50°C acetone solution for 30 minutes, then immersing in 35~40°C isopropanol for 15 minutes, and finally immersing in pure water overflow for 5 minutes.
实施例2Example 2
参考图2，本实施例提供一种半导体结构的减薄方法的具体流程，包括步骤S201-S209。2 , this embodiment provides a specific process of a semiconductor structure thinning method, including steps S201 - S209 .
S201，提供半导体结构1；所述半导体结构1包括正面和待减薄的背面。减薄前的半导体结构的厚度为700μm。S201, providing a semiconductor structure 1; the semiconductor structure 1 comprises a front surface and a back surface to be thinned. The thickness of the semiconductor structure before thinning is 700 μm.
S202，提供第一基板3；在所述半导体结构1的正面形成粘合层2，或在所述第一基板朝向所述半导体结构1的一侧表面形成粘合层2。S202 , providing a first substrate 3 ; forming an adhesive layer 2 on the front surface of the semiconductor structure 1 , or forming an adhesive layer 2 on a surface of the first substrate facing the semiconductor structure 1 .
S203，将所述半导体结构1的正面与所述第一基板3一侧键合，对所述半导体结构1的背面进行减薄，所述粘合层2位于第一基板3和半导体结构1的正面之间，如图3所示。通过机械研磨和化学抛光工艺对半导体结构1进行减薄，减薄后的半导体结构1的厚度为100μm，如图4所示。S203, bonding the front side of the semiconductor structure 1 to one side of the first substrate 3, thinning the back side of the semiconductor structure 1, and the adhesive layer 2 is located between the first substrate 3 and the front side of the semiconductor structure 1, as shown in Figure 3. The semiconductor structure 1 is thinned by mechanical grinding and chemical polishing processes, and the thickness of the semiconductor structure 1 after thinning is 100 μm, as shown in Figure 4.
S204，提供第二基板7，所述第二基板7中具有第一吸附孔；在所述第二基板7的一侧表面设置缓冲膜6，所述缓冲膜6中具有第二吸附孔；所述缓冲膜6包括缓冲主体膜5和支撑膜4，所述支撑膜4位于所述缓冲主体膜5和所述第二基板7之间，所述缓冲主体膜5位于所述支撑膜4背向所述第二基板7的一侧，如图5所示。S204, providing a second substrate 7, wherein the second substrate 7 has a first adsorption hole; setting a buffer film 6 on one side surface of the second substrate 7, wherein the buffer film 6 has a second adsorption hole; the buffer film 6 includes a buffer main body film 5 and a support film 4, wherein the support film 4 is located between the buffer main body film 5 and the second substrate 7, and the buffer main body film 5 is located on the side of the support film 4 facing away from the second substrate 7, as shown in FIG5 .
其中，第二基板7的材料为微孔SiC材料，第二基板7的孔隙率为45.1%，第一吸附孔的孔径为11.7μm，第二基板7的直径为156mm，厚度950μm。所述缓冲主体膜5的材料为聚四氟乙烯，所述缓冲膜6的厚度为0.13mm，所述缓冲膜6的孔隙率为62.3%，第二吸附孔的孔径为1μm，所述缓冲膜6与半导体结构1接触的一侧表面粗糙度为396nm。Among them, the material of the second substrate 7 is microporous SiC material, the porosity of the second substrate 7 is 45.1%, the aperture of the first adsorption hole is 11.7μm, the diameter of the second substrate 7 is 156mm, and the thickness is 950μm. The material of the buffer main film 5 is polytetrafluoroethylene, the thickness of the buffer film 6 is 0.13mm, the porosity of the buffer film 6 is 62.3%, the aperture of the second adsorption hole is 1μm, and the surface roughness of the side of the buffer film 6 in contact with the semiconductor structure 1 is 396nm.
S205，在所述第二基板7背向所述缓冲膜6的一侧设置真空吸附单元，所述真空吸附单元通过所述第一吸附孔和所述第二吸附孔抽气，提供负压，使得所述半导体结构1被所述第二基板7吸附固定，如图6所示；吸附状态下，所述第一吸附孔与所述第二吸附孔至少部分贯通。S205, a vacuum adsorption unit is provided on the side of the second substrate 7 facing away from the buffer film 6, and the vacuum adsorption unit draws air through the first adsorption hole and the second adsorption hole to provide negative pressure, so that the semiconductor structure 1 is adsorbed and fixed by the second substrate 7, as shown in FIG6 ; in the adsorption state, the first adsorption hole and the second adsorption hole are at least partially connected.
S206，加热所述粘合层2并施加外力以使所述半导体结构1的正面与所述第一基板3分离。将所述半导体结构1的正面与所述第一基板3解键合的过程中，加热所述粘合层2至150±3℃，采用推片手臂施加外力，水平推动第一基板3，以使所述半导体结构1与所述第一基板3分离，如图7所示。所述半导体结构1与所述第一基板3分离的过程中，所述缓冲膜6对所述半导体结构1的背面进行保护，减少了半导体结构1在解键合过程中出现的缺陷和划痕。S206, heating the adhesive layer 2 and applying external force to separate the front side of the semiconductor structure 1 from the first substrate 3. In the process of debonding the front side of the semiconductor structure 1 from the first substrate 3, the adhesive layer 2 is heated to 150±3°C, and an external force is applied by a film pusher arm to horizontally push the first substrate 3 to separate the semiconductor structure 1 from the first substrate 3, as shown in FIG7. In the process of separating the semiconductor structure 1 from the first substrate 3, the buffer film 6 protects the back side of the semiconductor structure 1, thereby reducing defects and scratches of the semiconductor structure 1 during the debonding process.
S207，将所述第二基板7与所述缓冲膜6分离，去除所述第二基板7。如图8所示，关闭真空吸附单元，关闭负压，所述第二基板7不再吸附所述半导体结构1，可以使所述半导体结构1能与所述第二基板7分离。S207, separating the second substrate 7 from the buffer film 6, and removing the second substrate 7. As shown in FIG8, the vacuum adsorption unit is turned off, the negative pressure is turned off, and the second substrate 7 no longer adsorbs the semiconductor structure 1, so that the semiconductor structure 1 can be separated from the second substrate 7.
S208，采用溶液浸泡工艺去除所述缓冲膜6。将所述缓冲膜6与所述半导体结构1放入具有丙酮溶液的标准花篮中进行加热浸泡使所述缓冲膜6与所述半导体结构1分离。所述丙酮溶液的温度在20℃~26℃。S208, removing the buffer film 6 by using a solution immersion process. The buffer film 6 and the semiconductor structure 1 are placed in a standard basket with acetone solution for heating and immersion to separate the buffer film 6 from the semiconductor structure 1. The temperature of the acetone solution is 20°C to 26°C.
S209，采用溶液浸泡工艺去除所述粘合层2。首先用45℃~50℃丙酮溶液浸泡30min，其次用35℃~40℃异丙醇浸泡15min，最后用纯水溢流浸泡5min去除所属粘合层2。S209, removing the adhesive layer 2 by using a solution soaking process: first soaking in 45°C-50°C acetone solution for 30 minutes, then soaking in 35°C-40°C isopropanol for 15 minutes, and finally soaking in pure water overflow for 5 minutes to remove the adhesive layer 2.
此外，本发明还提供了对比例1-对比例3。通过对比例1，对比不设置缓冲膜的情况下硬质基板的孔隙率和粗糙度对半导体结构划伤情况；通过对比例2，确定能对半导体实施有效固定的叠加孔隙率的最优范围；通过对比例3，确定合适的缓冲膜粗糙度以减小对解键合划伤的影响。In addition, the present invention also provides comparative examples 1 to 3. Comparative example 1 compares the scratching of the semiconductor structure by the porosity and roughness of the hard substrate without a buffer film; comparative example 2 determines the optimal range of the stacking porosity that can effectively fix the semiconductor; and comparative example 3 determines the appropriate roughness of the buffer film to reduce the impact on the debonding scratch.
对比例1Comparative Example 1
对比例1与实施例2的区别在于实施过程中不设置缓冲膜，其他步骤均相同。对比例1了选择六种不同孔隙率的SIC基板解键合，目的在于观察硬质基板的孔隙率和粗糙度对半导体结构划伤情况。The difference between Comparative Example 1 and Example 2 is that no buffer film is provided during the implementation process, and the other steps are the same. Comparative Example 1 selects six SIC substrates with different porosities for debonding, in order to observe the effect of the porosity and roughness of the hard substrate on the scratching of the semiconductor structure.
参考图9，与实施例2不同的是对比例1不提供缓冲膜6，半导体结构背面直接和第二基板接触，第二基板选用微孔SIC材料，分别选取不同孔隙率的六片SIC基板，所用的SIC基板均经过双面抛光处理，孔隙率分别为13.3%、18.0%、22.5%、34.7%、41.2%、45.0%。从左到右依次统计半导体结构九点处的划伤尺寸并计算平均值，参考图10，半导体结构平均划伤尺寸随着SIC基板孔隙率的增加呈现出先减小后增加的趋势，孔隙率为13.3%相应的半导体划伤宽度为17.6μm，孔隙率增加至22.5%，半导体结构的平均划伤宽度减小至5.6μm，随着孔隙率增加到45.0%，划伤宽度重新上升到22.5μm。Referring to FIG9 , the difference from Example 2 is that the buffer film 6 is not provided in Example 1, and the back of the semiconductor structure is directly in contact with the second substrate. The second substrate is made of microporous SIC material, and six SIC substrates with different porosities are selected respectively. The SIC substrates used are double-sided polished, and the porosities are 13.3%, 18.0%, 22.5%, 34.7%, 41.2%, and 45.0%, respectively. The scratch sizes at nine points of the semiconductor structure are counted from left to right and the average value is calculated. Referring to FIG10 , the average scratch size of the semiconductor structure shows a trend of first decreasing and then increasing with the increase of the porosity of the SIC substrate. The corresponding semiconductor scratch width with a porosity of 13.3% is 17.6μm. When the porosity increases to 22.5%, the average scratch width of the semiconductor structure decreases to 5.6μm. As the porosity increases to 45.0%, the scratch width rises again to 22.5μm.
根据实验结果可以看出，第二基板的孔隙率会严重影响真空系统对半导体的吸附，孔隙率降低导致第二基板的贯通性变差，真空系统无法透过SiC基板的微孔对半导体结构实施有效固定，加热解键合的外力推动使第二基板和半导体结构间产生相对移动，第二基板和半导体结构间的摩擦对半导体结构背面产生划伤。According to the experimental results, the porosity of the second substrate will seriously affect the adsorption of the vacuum system on the semiconductor. The reduced porosity leads to the deterioration of the penetration of the second substrate. The vacuum system cannot effectively fix the semiconductor structure through the micropores of the SiC substrate. The external force of heating and debonding causes relative movement between the second substrate and the semiconductor structure. The friction between the second substrate and the semiconductor structure scratches the back of the semiconductor structure.
增加第二基板的孔隙率利于真空系统对半导体结构的固定，但孔隙率的增加会导致第二基板表面的粗糙度变大，参考图11，第二基板的表面粗糙度随着孔隙率的增加呈现上升趋势。从而对相接触的半导体结构产生更严重的划伤。参考图10，通过调控第二基板的孔隙率，可以减少对半导体结构的损伤但不能达到完全消除的效果。Increasing the porosity of the second substrate is beneficial to the fixation of the semiconductor structure by the vacuum system, but the increase in porosity will cause the roughness of the surface of the second substrate to increase. Referring to FIG11, the surface roughness of the second substrate shows an upward trend with the increase in porosity. As a result, more serious scratches are caused to the contacting semiconductor structure. Referring to FIG10, by adjusting the porosity of the second substrate, the damage to the semiconductor structure can be reduced but cannot be completely eliminated.
对比例2Comparative Example 2
对比例2与实施例2的区别在于设置粗糙度最小的缓冲膜，缓冲膜的孔隙率为62.3%，孔径大小为1μm，对比例2选择六种不同孔隙率的SIC基板解键合，目的在于确定能对半导体实施有效固定的叠加孔隙率的最优范围。其他步骤均相同。The difference between Comparative Example 2 and Example 2 is that a buffer film with the smallest roughness is provided, the porosity of the buffer film is 62.3%, and the pore size is 1 μm. Comparative Example 2 selects six SIC substrates with different porosities for debonding, in order to determine the optimal range of superimposed porosities that can effectively fix the semiconductor. The other steps are the same.
分别选取不同孔隙率的六片SIC基板，所用的SIC基板均经过双面抛光处理，孔隙率分别为13.3%、18.0%、22.5%、34.7%、41.2%、45.0%，在第二基板上设置缓冲膜，缓冲膜的孔径为1.00μm，孔隙率62.3%，与六片SiC基板叠加后的孔隙率分别为8.2%、11.2%、14.0%、21.5%、25.5%、27.9%。叠加孔隙率=第二基板孔隙率×缓冲膜孔隙率。叠加孔隙率为8.2%、11.2%、14%的条件下，平均划伤尺寸分别6.6μm、6.4μm、4.8μm，但是叠加孔隙率达到21.5%以上划伤完全消失。例如，图12为叠加孔隙率为27.9%条件下表面形貌。根据实验结果，在解键合过程中第二基板与缓冲膜的叠加孔隙率大于21.5%时可以完全避免对半导体结构产生划伤。Six SIC substrates with different porosities were selected. The SIC substrates used were double-sided polished, with porosities of 13.3%, 18.0%, 22.5%, 34.7%, 41.2%, and 45.0%, respectively. A buffer film was set on the second substrate, with a pore size of 1.00 μm and a porosity of 62.3%. The porosities after superposition with the six SiC substrates were 8.2%, 11.2%, 14.0%, 21.5%, 25.5%, and 27.9%, respectively. Superposition porosity = second substrate porosity × buffer film porosity. Under the conditions of superposition porosity of 8.2%, 11.2%, and 14%, the average scratch sizes were 6.6 μm, 6.4 μm, and 4.8 μm, respectively, but the scratches completely disappeared when the superposition porosity reached more than 21.5%. For example, Figure 12 shows the surface morphology under the condition of superposition porosity of 27.9%. According to experimental results, when the overlapping porosity of the second substrate and the buffer film is greater than 21.5% during the debonding process, scratches on the semiconductor structure can be completely avoided.
对比例3Comparative Example 3
对比例3与实施例2的区别在于选择孔隙率为45.0%的SiC基板作第二基板，选择六种不同粗糙度的缓冲膜，目的在于选择合适的粗糙度以减小对解键合划伤的影响。其他步骤均相同。The difference between Comparative Example 3 and Example 2 is that a SiC substrate with a porosity of 45.0% is selected as the second substrate, and six buffer films with different roughness are selected, in order to select a suitable roughness to reduce the impact on debonding scratches. The other steps are the same.
选择和实施例2相同的半导体结构和减薄抛光方法，选择选择孔隙率为45.0%的SiC基板作第二基板，保证叠加后的孔隙率足够大，确保能对半导体结构实施有效固定，分别选择孔经大小为1.00μm、3.00μm、5.00μm、10.00μm的缓冲膜，表面粗糙度分别为396nm、478nm、843nm、1429nm，通过对比研究粗糙度对解键合划伤的影响。叠加后的孔隙率分别为27.9%、29.2%、31.2%、33.2%，结果显示，粗糙度为396nm和478nm的缓冲膜解键合后未对半导体结构产生划伤，在缓冲膜粗糙度843nm和1429nm的条件下，解键合后对半导体结构表面划伤的尺寸分别为4.5μm和6.4μm，参考图13和图14分别为粗糙度843nm、1429nm的缓冲膜解键合后的表面形貌。根据图13，缓冲膜粗糙度为843nm时解键合后半导体结构表面产生了宽度为4.5μm的划伤；根据图14，缓冲膜粗糙度为1429nm时解键合后半导体结构表面产生了宽度为6.4μm的划伤。根据实验结果，在解键合过程中缓冲膜的表面粗糙度≤478nm，缓冲膜的孔径为1μm~3μm，缓冲膜的孔隙率为62.0%~64.9%时才能完全避免对半导体结构产生划伤。The same semiconductor structure and thinning and polishing method as in Example 2 were selected, and a SiC substrate with a porosity of 45.0% was selected as the second substrate to ensure that the porosity after stacking was large enough to ensure that the semiconductor structure could be effectively fixed. Buffer films with pore sizes of 1.00 μm, 3.00 μm, 5.00 μm, and 10.00 μm were selected respectively, and the surface roughnesses were 396 nm, 478 nm, 843 nm, and 1429 nm, respectively. The effect of roughness on debonding scratches was studied by comparison. The porosity after superposition is 27.9%, 29.2%, 31.2% and 33.2% respectively. The results show that the buffer films with roughness of 396nm and 478nm did not scratch the semiconductor structure after debonding. Under the conditions of buffer film roughness of 843nm and 1429nm, the sizes of scratches on the surface of the semiconductor structure after debonding were 4.5μm and 6.4μm respectively. Reference Figures 13 and 14 are the surface morphologies of buffer films with roughness of 843nm and 1429nm after debonding. According to Figure 13, when the buffer film roughness is 843nm, scratches with a width of 4.5μm are generated on the surface of the semiconductor structure after debonding; according to Figure 14, when the buffer film roughness is 1429nm, scratches with a width of 6.4μm are generated on the surface of the semiconductor structure after debonding. According to experimental results, during the debonding process, scratches on the semiconductor structure can be completely avoided when the surface roughness of the buffer film is ≤478nm, the pore size of the buffer film is 1μm~3μm, and the porosity of the buffer film is 62.0%~64.9%.
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之中。Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.
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