CN118738109B - Gate commutated thyristor unit, preparation method thereof and semiconductor device - Google Patents
Gate commutated thyristor unit, preparation method thereof and semiconductor device Download PDFInfo
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Abstract
本公开涉及一种门极换流晶闸管单元及其制备方法、半导体器件，包括：从阳极金属到阴极金属依次排列的阳极区、缓冲区、第一初始基区、第二初始基区、阴极区；第一掺杂基区和第二掺杂基区，分别位于第二初始基区顶部的两侧；第一门极金属，至少部分位于第一掺杂基区的沟槽内；第二门极金属，至少部分位于第二掺杂基区的沟槽内，其中，阳极区、基区、第一掺杂基区、第二掺杂基区的导电类型相同，第一初始基区、阴极区的导电类型相同且与阳极区的导电类型不同；第一掺杂基区和第二掺杂基区中的离子浓度大于第二初始基区的离子浓度。至少能够有效降低门极换流晶闸管单元在关断过程中动态雪崩重触发的风险，提升IGCT芯片的关断能力。
The present disclosure relates to a gate-commutated thyristor unit and a preparation method thereof, and a semiconductor device, comprising: an anode region, a buffer region, a first initial base region, a second initial base region, and a cathode region arranged in sequence from an anode metal to a cathode metal; a first doped base region and a second doped base region, respectively located on both sides of the top of the second initial base region; a first gate metal, at least partially located in a groove of the first doped base region; a second gate metal, at least partially located in a groove of the second doped base region, wherein the anode region, the base region, the first doped base region, and the second doped base region have the same conductivity type, the first initial base region and the cathode region have the same conductivity type and are different from the conductivity type of the anode region; and the ion concentration in the first doped base region and the second doped base region is greater than the ion concentration in the second initial base region. At least it can effectively reduce the risk of dynamic avalanche re-triggering of the gate-commutated thyristor unit during the shutdown process, and improve the shutdown capability of the IGCT chip.
Description
Technical Field
The disclosure relates to the technical field of integrated circuit manufacturing, in particular to a gate commutated thyristor unit, a preparation method thereof and a semiconductor device.
Background
An integrated gate commutated thyristor unit (IGCT: INTEGRATED GATE Commutated Thyristor) is a new type of power semiconductor device used in high-capacity power electronics. It was first in 1957, the first Thyristor (Silicon Controlled Rectifier, SCR; also known as Thyristor) invented by the american GE company for industrial power conversion and control, and the device was turned on by applying a certain positive voltage between the gate and the cathode. Thyristors can control larger power with small current, and the transformation, transmission and application of the electric energy are marked to enter a new technology development era. The power electronic conversion device is widely applied to various fields of industry, traffic, energy sources and the like, achieves the purposes of weak current control and high-power electric energy control, and rapidly develops a power electronic technology, wherein a 4kA/8 kV-class thyristor is applied in a large scale in the beginning of the century.
In order to overcome the defect that the Thyristor cannot be turned off by the Gate, a Gate Turn-off Thyristor (GTO) is pushed out in 1960, and the Gate Turn-off control is realized by the parallel connection of the Gate around the discrete cathode, the structure and process optimization of the saturation depth during the conduction and the like, so that the complex supporting circuit is greatly simplified, and the reliability is improved. However, since the gate driving power of the GTO is large, the driving circuit is complex, and the current of the turn-off device is uneven, a huge buffer circuit is required, and these disadvantages limit the application of the GTO.
The integrated gate commutated thyristor unit (INTEGRATED GATE-Commutated Thyristor, IGCT) is a device integrating the improved GTO chip and gate drive circuit together, which essentially belongs to a thyristor device, and has strong conductance modulation effect when conducting to ensure low-state voltage drop and high-current capacity. Meanwhile, due to the introduction of the transparent anode, the field blocking layer and the hard drive technology, the transparent anode has quick and reliable switching characteristics, and a buffer circuit can be omitted when the transparent anode is applied. The design concept of IGCT was first proposed by swiss ABB in 1996, and was called hard-drive transparent anode GTO (HD-GTO) in 1997 formally named IGCT. Compared to insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBTs), IGCTs have lower switching frequencies (< 1 kHz), but have the advantages of higher withstand voltage, greater current capability, lower turn-on voltage drop, higher reliability, and lower manufacturing cost. In fact, compared with AC power grid applications, key devices such as medium-high voltage high capacity AC-DC converters, DC transformers and DC breakers in DC power grids have many new characteristics, such as very low switching frequency of modular multilevel AC-DC converters, soft switching capability of double active full-bridge DC transformers, single operation of DC breakers, etc. The characteristics avoid the disadvantage of low IGCT operation frequency to a great extent, and bring a opportunity for the application of the IGCT in a direct current power grid.
IGCT has excellent performance, but in practical application, there are many factors that restrict further expansion of the safe operating area (Safe Operating Area, SOA) of IGCT, and IGCT reliability is still to be improved, especially if the turn-off process of IGCT is often accompanied by turn-off failure or even device damage. When the IGCT is turned off under the conditions of high voltage and high current, the device is easy to dynamically avalanche under the voltage which is much smaller than the static blocking voltage because of the influence of excessive carriers in the base region, so that the device fails to turn off and even generates unrecoverable electrothermal breakdown.
In 2013, the ABB corporation research literature indicates that two main failure mechanisms of IGCT turn-off are that hard drive failure is the main failure mechanism when the direct current side voltage is low, and dynamic avalanche is the main failure mechanism when the direct current side voltage is high. Intensive research is conducted on the three-dimensional simulation model of the IGCT established before, and the failure mechanism of the IGCT is explained. It is pointed out that in the initial phase of shutdown, the region under the IGCT cathode is rapidly depleted of mobile charges and the injection is discontinued. In the next stage of turn-off, the depletion of excess carriers goes deep into the P-base and N-base regions, and the dynamic avalanche maintains the concentration of free carriers at a high level. The carrier density under the cathode is greater, which in turn causes the conduction current to concentrate near this point, and this increased lateral current density strongly increases the quasi-fermi potential difference in the middle of the cathode, P-base junction. At the start of the fault, the flowing current becomes large enough to locally compensate the junction barrier and cause the thyristor to re-trigger, which fills the nearby region with plasma, the depletion layer completely collapses, the highly conductive region takes over the entire load current and causes the final failure of the device.
For the hard drive failure mechanism when the IGCT is turned off, the main reason is that the working principle of the IGCT requires that the gate drive unit totally commutates anode current to the gate unit in a very short time, so the inductance and impedance requirements on the IGCT gate drive circuit are very high, namely the gate resistance R G and the parasitic inductance L G must be very small to ensure the hard drive operation of the IGCT.
For a dynamic avalanche failure mechanism in the turn-off process of the IGCT, the risk of cathode re-triggering caused by dynamic avalanche of the IGCT is reduced mainly through optimized structures such as a wave junction P base region structure, a strip enhancement structure, a gate electrode carrier extraction enhancement structure and the like, and the turn-off capability of an IGCT device is improved.
In 2007, the ABB company first proposes a concept of a waved P-base IGCT (corugated P-base IGCT), and as shown in fig. 1, test results show that the waved P-base IGCT can effectively improve the current turn-off capability of the device, especially at normal temperature. At 25 ℃, the current turn-off capability of the wave junction P base region IGCT is improved from 5kA to 7.2kA, but at 125 ℃, the current turn-off capability of the wave junction P base region IGCT is not obviously improved from 6kA to about 6.7 kA.
Researchers at university of cambridge and ABB in the united kingdom compared the turn-off capability of the conventional structure IGCT (structure (b) in fig. 2) and the wavy junction P base region IGCT (structure (a) in fig. 2) and analyzed the reason why the wavy junction P base region IGCT structure has excellent turn-off capability because the lateral electric field component in the wavy junction P base region IGCT design diverted the hole current to the gate metal contact point, preventing holes from reaching the vicinity of the cathode junction, this more preferred current path could prevent the dynamic avalanche current from triggering the transistor-transistor current gain mechanism.
In 2014, ABB corporation proposed a strip-enhanced IGCT chip structure (StriPe Fortified GCT). The design concept of the structure is that the P base region is low doped to realize high gate-cathode breakdown voltage, and a P+ buried layer arranged in the P base region aims to restore the transverse resistance of the region, so that the risk of latch-up of a thyristor when the device is turned off is reduced, and the current turn-off capability of the device is improved. Three bar enhancement structures are designed, namely a structure below a gate electrode, a structure below a cathode electrode and a whole cell coverage structure, and the simulation result shows that the whole cell coverage bar enhancement chip structure has the strongest current turn-off capability, the distance between a P+ region and the chip surface has an optimal value (30 mu m), and the maximum current turn-off capability can be improved from 4000A to 5200A.
In 2015, the university of Qinghua proposes to adopt a double-P-base-region gate cathode structure (patent number CN 105590959B) to improve the current turn-off capability of the IGCT. As shown in fig. 3, the concentration of the P base region 2 in the patent structure can be set lower than that of the P base region by adopting an epitaxial method so as to improve the gate-cathode breakdown voltage and increase the current conversion speed, the P+ short base region cannot influence the gate-cathode breakdown voltage, the peak concentration of the P+ short base region can be improved, a low-resistance channel for current transfer is formed, and the rapid current conversion is realized. The design concept of this patent is similar to the strip-enhanced IGCT structure proposed by ABB.
In addition, the middle vehicle proposed a gate electrode carrier extraction enhancement structure (CEET) in 2016, as shown in fig. 4, the P2+ base region doping concentration is greater than the P1+ base region doping concentration mainly by optimizing the P base region doping concentration distribution under the gate electrode, so as to form a lateral barrier, and the high concentration P2+ base region enables carriers to be rapidly extracted to the gate electrode in the turn-off process, so that the turn-off capability of the gate electrode converter thyristor unit is improved. In a specific embodiment, the width of the p2+ base region may increase with the distance between the cathode comb strip and the gate ring.
In the traditional IGCT chip design, the ion doping concentration distribution of the second initial base region (P base region) below the gate electrode metal is optimized to improve the turn-off capability of the gate electrode commutated thyristor unit, but the maximum current turn-off capability of the gate electrode commutated thyristor unit is improved slightly due to the limited ion doping concentration which can be increased in the whole P base region, and the risk of heavy triggering of dynamic avalanche exists in the turn-off process.
Disclosure of Invention
Based on the above, it is necessary to provide a gate commutated thyristor unit, a manufacturing method thereof and a semiconductor device for the gate commutated thyristor unit, so that at least the risk of dynamic avalanche re-triggering of the gate commutated thyristor unit in the turn-off process can be effectively reduced, and the turn-off capability of an IGCT chip is improved.
To achieve the above and other objects, in a first aspect, the present disclosure provides a gate-commutated thyristor unit, which includes an anode region, a first initial base region, a second initial base region, and a cathode region sequentially arranged from an anode metal to a cathode metal, a first doped base region and a second doped base region respectively located on two sides of a top of the second initial base region, a first gate metal at least partially located in a trench of the first doped base region, and a second gate metal at least partially located in a trench of the second doped base region, wherein conductivity types of the anode region, the second initial base region, the first doped base region, and the second doped base region are the same, conductivity types of the first initial base region and the cathode region are the same and different from those of the anode region, and ion concentrations in the first doped base region and the second doped base region are greater than those of the second initial base region.
In the gate-commutated thyristor unit in the above embodiment, the first doped base region and the second doped base region with the ion concentration greater than that of the second initial base region are disposed on both sides of the top of the second initial base region, and the first gate metal is at least partially located in the trench of the first doped base region, and the second gate metal is at least partially located in the trench of the second doped base region.
In addition, the first gate metal and the second gate metal are at least partially positioned in the grooves of the first doping base region and the second doping base region, so that the height difference between the cathode metal and the gate metal in the gate commutated thyristor unit can be increased, and the crimping type packaging of the gate commutated thyristor unit is facilitated.
In one embodiment, the thickness of the first gate metal is greater than the depth of the trench of the first doped base region, the thickness of the second gate metal is greater than the depth of the trench of the second doped base region, and by limiting the depths of the trenches of the first doped base region and the second doped base region, the gate commutated thyristor unit is prevented from generating larger stress, and meanwhile, the first gate metal and the second gate metal are ensured to completely cover the trenches of the first doped base region and the second doped base region.
In one embodiment, the depth of the trench of the first doped base region and the depth of the trench of the second doped base region are both in the range of 0.5 μm to 6 μm, and the junction depth of the first doped base region and the second doped base region is in the range of 5 μm to 20 μm, so that the gate converter thyristor unit is more beneficial to avoiding larger stress by limiting the depth of the trench and the junction depth.
In one embodiment, the doping concentration peak values of the first doping base region and the second doping base region are that the ion doping concentration of the first doping base region and the second doping base region is prevented from influencing the performance such as the gate-cathode breakdown voltage, the conduction voltage drop, the parasitic capacitance and the stability of the IGCT by limiting the doping concentration of the first doping base region and the second doping base region.
In one embodiment, the second initial base region includes a first sub-initial base region and a second sub-initial base region, the first sub-initial base region being located on top of the second sub-initial base region, the ion concentration in the first initial base region being greater than the ion concentration in the second initial base region.
In one embodiment, the second initial base region comprises a planar junction or a waved junction. The turn-off performance of the gate commutated thyristor unit is further improved by arranging the second initial base region with the wavy junction.
In one embodiment, the thickness of the first gate metal and the thickness of the second gate metal are both in a range of 8 μm to 15 μm, and by setting the thickness ranges of the first gate metal and the second gate metal, the first gate metal and the second gate metal are ensured to be at least partially positioned in the grooves of the first doping base region and the second doping base region, and meanwhile, the height difference between the cathode metal and the gate metal in the gate converter thyristor unit can be ensured, so that the crimping type packaging of the gate converter thyristor unit is facilitated.
In a second aspect, the embodiment of the disclosure further provides a semiconductor device, which includes the gate commutated thyristor unit in any embodiment, so that the risk of dynamic avalanche re-triggering of the IGCT in the turn-off process can be effectively reduced, and the turn-off capability of the IGCT is improved.
In a third aspect, the disclosed embodiment of the application also provides an electronic device, which comprises the gate commutated thyristor unit in any embodiment, or the semiconductor device, so that the risk of dynamic avalanche re-triggering of the IGCT in the turn-off process can be effectively reduced, and the turn-off capability of the IGCT is improved.
The embodiment of the disclosure also provides a method for manufacturing the gate-electrode converter thyristor unit, which comprises the steps of sequentially forming an anode region, a first initial base region, a second initial base region and a cathode region from anode metal to cathode metal, forming the first gate metal and the second gate metal in a groove of a first doped base region and a groove of a second doped base region respectively, wherein the conductivity types of the anode region, the second initial base region, the first doped base region and the second doped base region are the same, the conductivity types of the first initial base region and the cathode region are the same and are different from the conductivity types of the anode region, grooves are formed on two sides of the top of the second initial base region respectively, and forming the first doped base region and the second doped base region at the connection positions of the grooves on two sides of the top of the second initial base region and the second initial base region respectively, wherein the ion concentration in the first doped base region and the second doped base region is greater than that in the second initial base region.
In the method for manufacturing the gate-commutated thyristor unit in the embodiment, the first doped base region and the second doped base region with the ion concentration larger than that of the second initial base region are formed on the two sides of the top of the second initial base region, the first gate metal is at least partially formed in the groove of the first doped base region, the second gate metal is at least partially formed in the groove of the second doped base region, and the ion concentrations of the first doped base region and the second doped base region which are in contact with the first gate metal and the second gate metal are enhanced, so that a path of a current carrier generated by dynamic avalanche below an IGCT cathode flowing to the first gate metal and/or the second gate metal is shortened, meanwhile, the high-concentration ion doping is beneficial to reducing the sheet resistance of the second initial base region nearby the gate electrode, the risk of dynamic avalanche heavy triggering of the IGCT in the turn-off process is effectively reduced, and the turn-off capability of the IGCT is improved.
In addition, the first gate metal and the second gate metal are at least partially positioned in the grooves of the first doping base region and the second doping base region, so that the height difference between the cathode metal and the gate metal in the gate commutated thyristor unit can be increased, and the crimping type packaging of the gate commutated thyristor unit is facilitated.
In one embodiment, forming trenches on two sides of the top of the second initial base region respectively includes forming a mask layer on the second initial base region, the mask layer including a first opening pattern and a second opening pattern on two sides, and etching and removing the second initial base region with a target thickness in the first opening pattern and the second opening pattern to form trenches on two sides of the top of the second initial base region respectively.
In the method for manufacturing the gate commutated thyristor unit in the embodiment, a mask layer is formed on the second initial base region, and a trench is formed on the second initial base region through etching based on a mask plate, so that a basic structure is provided for subsequent ion implantation.
In one embodiment, a dry etching process is used to etch and remove the second initial base region of the target thickness within the first and second opening patterns.
In the method for manufacturing the gate commutated thyristor unit, the dry etching process is used, so that the trench morphology is optimized, and the etching deviation is reduced.
In one embodiment, a first doped base region and a second doped base region are respectively formed at the connection positions of the grooves on the two sides of the top of the second initial base region and the second initial base region, wherein the first doped base region and the second doped base region are respectively formed at the connection positions of the grooves on the two sides of the top of the second initial base region and the second initial base region by adopting an annealing process, and the high-concentration doped ion implantation is performed on the connection positions of the grooves on the two sides of the top of the second initial base region and the second initial base region based on a mask layer formed on the second initial base region.
In the method for manufacturing the gate commutated thyristor unit, the first doped base region and the second doped base region formed after high-concentration doping ion implantation and annealing are performed by using the mask layer etched by the groove, so that consumption of the mask layer is reduced, and the first doped base region and the second doped base region can be formed quickly and stably.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a schematic cross-sectional view of a first prior art gate commutated thyristor cell;
FIG. 2 is a schematic cross-sectional view of a second prior art gate commutated thyristor cell;
FIG. 3 is a schematic cross-sectional view of a third prior art gate commutated thyristor cell;
FIG. 4 is a schematic cross-sectional view of a fourth prior art gate commutated thyristor cell;
FIG. 5 is a flowchart of a method for manufacturing a gate commutated thyristor unit according to an embodiment of the present application;
FIG. 6 is a schematic cross-sectional view of a fifth prior art gate commutated thyristor cell;
FIG. 7 is a schematic cross-sectional view of a gate commutated thyristor unit according to an embodiment of the application;
FIG. 8 is a schematic cross-sectional view of a gate commutated thyristor cell according to another embodiment of the application;
FIG. 9 is a graph comparing the cathode current during turn-off of a gate commutated thyristor unit of the application with the cathode current during turn-off of a conventional gate commutated thyristor unit;
FIG. 10 is a graph comparing the current distribution of a gate commutated thyristor unit of the application at turn-off time with that of a conventional gate commutated thyristor unit;
Fig. 11 is a graph comparing the potential distribution of the gate commutated thyristor unit of the application at the turn-off time with that of a conventional gate commutated thyristor unit.
Reference numerals illustrate:
701. the semiconductor device comprises a first initial base region, 702, a third doped region, 703, an anode region, 704, a second sub-initial base region, 705, a first sub-initial base region, 707, a cathode region, 708, a first gate electrode metal, 709, a cathode metal, 710, an anode metal, 711, a second gate electrode metal, 801, a first doped base region, 802, a second doped base region, 901 and a waved junction P base region.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section, for example, a first doping type could be termed a second doping type, and, similarly, a second doping type could be termed a first doping type, a doping type different from the second doping type, such as, for example, the first doping type could be P-type and the second doping type could be N-type, or the first doping type could be N-type and the second doping type could be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
Referring to fig. 7, in some embodiments, a gate-commutated thyristor cell is provided that includes an anode region 703, a first initial base region 701, a second initial base region, and a cathode region 707 sequentially arranged from an anode metal 710 to a cathode metal 709, a first doped base region 801 and a second doped base region 802 respectively located on both sides of the top of the second initial base region, a first gate metal 708 at least partially located in a trench of the first doped base region 801, and a second gate metal 711 at least partially located in a trench of the second doped base region 802.
The conductivity types of the anode region 703, the second initial base region, the first doped base region 801 and the second doped base region 802 are the same, the conductivity types of the first initial base region 701 and the cathode region 707 are the same and different from the conductivity type of the anode region 703, and the ion concentration in the first doped base region 801 and the second doped base region 802 is greater than that of the second initial base region.
In some embodiments, a third doped region 702 is formed between the anode region 703 and the first initial base region 701.
The gate commutated thyristor unit provided by the application can be applied to various GCT devices such as reverse resistance type, asymmetric and reverse conduction type.
As an example, the anode region 703 may be a p+ anode region 703, the third doped region 702 may be an N-type buffer region, the first initial base region 701 may be an N-base region, the second initial base region includes a second sub-initial base region 704 and a first sub-initial base region 705, the first sub-initial base region 705 is located on top of the second sub-initial base region 704, the cathode region 707 may be an n+ cathode region 707, and the first doped base region 801 and the second doped base region 802 may be p++ base regions.
As an example, the anode region 703 may be a p+ anode region 703, the third doped region 702 may be a P-type anode region, the first initial base region 701 may be an N base region, the second initial base region includes a second sub-initial base region 704 and a first sub-initial base region 705, the first sub-initial base region 705 is located on top of the second sub-initial base region 704, the cathode region 707 may be an n+ cathode region 707, and the first doped base region 801 and the second doped base region 802 may be p++ base regions.
As an example, the first sub-initial base region may be a p+ base region, the second initial base region may be a P base region, and the doping elements of the first doping base region 801 and the second doping base region 802 may be boron.
Referring to fig. 6-7, compared with the existing gate-commutated thyristor unit, the present application sets the first doped base region 801 and the second doped base region 802 with the ion concentration greater than that of the second initial base region on both sides of the top of the second initial base region, and makes the first gate metal 708 at least partially located in the trench of the first doped base region 801, and the second gate metal 711 at least partially located in the trench of the second doped base region 802.
In addition, the first gate metal 708 and the second gate metal 711 are at least partially located in the trenches of the first doped base region 801 and the second doped base region 802, so that the height difference between the cathode metal 709 and the gate metal in the gate commutated thyristor unit can be increased, and the crimping type packaging of the gate commutated thyristor unit is facilitated.
As an example, with continued reference to fig. 7, the thickness of the first gate metal 708 is greater than the depth of the trench of the first doped base region 801, and the thickness of the second gate metal 711 is greater than the depth of the trench of the second doped base region 802, so that by limiting the depth of the trenches of the first doped base region 801 and the second doped base region 802, the gate-commutated thyristor cell is prevented from generating larger stress, and at the same time, the complete coverage of the trenches of the first doped base region 801 and the second doped base region 802 by the first gate metal 708 and the second gate metal 711 is ensured.
In some embodiments, the depth of the trench of the first doped base region 801 and the depth of the trench of the second doped base region 802 are both in the range of 0.5 μm to 6 μm, and the junction depth of the first doped base region 801 and the second doped base region 802 is in the range of 5 μm to 20 μm, so that the limitation of the depth of the trench and the junction depth is more beneficial to avoiding the generation of larger stress of the gate converter thyristor unit.
In some embodiments, the doping concentration peaks of the first doped base region 801 and the second doped base region 802 areBy limiting the doping concentration of the first doping base region 801 and the second doping base region 802, the influence of the too high ion doping concentration of the first doping base region 801 and the second doping base region 802 on the performances of gate-cathode breakdown voltage, conduction voltage drop, parasitic capacitance, stability and the like of the IGCT is avoided.
In some embodiments, the thickness of the first gate metal 708 and the thickness of the second gate metal 711 are both in the range of 8 μm to 15 μm, and by setting the thickness ranges of the first gate metal 708 and the second gate metal 711, it is ensured that the first gate metal 708 and the second gate metal 711 are at least partially located in the trenches of the first doped base region 801 and the second doped base region 802, and at the same time, the height difference between the cathode metal 709 and the gate metal in the gate converter thyristor unit can be ensured, which is more beneficial to the compression-bonding type packaging of the gate converter thyristor unit.
In some embodiments, referring to fig. 8, the second initial base region includes a first sub-initial base region and a second sub-initial base region, the first sub-initial base region is located on top of the second sub-initial base region, and an ion concentration in the first initial base region 701 is greater than an ion concentration in the second initial base region, wherein the second initial base region includes a waved junction. The turn-off performance of the gate commutated thyristor unit is further improved by arranging the second initial base region with the wavy junction.
Wherein the second initial base region comprises a planar junction or a waved junction.
In some embodiments, referring to fig. 8, the second initiation base region with the waved junction includes a first sub-initiation base region 705 and a waved junction P base region 901.
As an example, the anode region 703 may be a p+ anode region 703, the third doped region 702 may be an N-type buffer region, the first initial base region 701 may be an N-base region, the second initial base region includes a wavy junction P base region 901 and a first sub-initial base region 705, the first sub-initial base region 705 is located on top of the wavy junction P base region 901, the cathode region 707 may be an n+ cathode region 707, and the first doped base region 801 and the second doped base region 802 may be p++ base regions.
As an example, the anode region 703 may be a p+ anode region 703, the third doped region 702 may be a p+ anode region, the first initial base region 701 may be an N base region, the second initial base region includes a wavy junction P base region 901 and a first sub-initial base region 705, the first sub-initial base region 705 is located on top of the wavy junction P base region 901, the cathode region 707 may be an n+ cathode region 707, and the first doped base region 801 and the second doped base region 802 may be p++ base regions.
Referring to fig. 5, in some embodiments, a method for manufacturing a gate commutated thyristor unit is provided, including:
S1, an anode region 703, a first initial base region 701, a second initial base region, and a cathode region 707 are formed in this order from the anode metal 710 to the cathode metal 709.
S2, forming grooves on two sides of the top of the second initial base region respectively.
S3, forming a first doped base region 801 and a second doped base region 802 below grooves on two sides of the top of the second initial base region.
Wherein the ion concentration in the first doped base region 801 and the second doped base region 802 is greater than the ion concentration of the second initial base region.
And S4, forming a first gate metal 708 and a second gate metal 711 in the grooves of the first doped base region 801 and the second doped base region 802 respectively.
The conductivity types of the anode region 703, the second initial base region, the first doped base region 801 and the second doped base region 802 are the same, the conductivity types of the first initial base region 701 and the cathode region 707 are the same and different from the conductivity type of the anode region 703, and the ion concentration in the first doped base region 801 and the second doped base region 802 is greater than that of the second initial base region.
In some embodiments, a third doped region 702 is formed between the anode region 703 and the first initial base region 701.
The preparation method of the gate commutated thyristor unit provided by the application can be applied to various GCT devices such as reverse resistance type, asymmetric type and reverse conduction type.
As an example, the third doped region 702 may be an N-type buffer region or a P-type anode region, the first initial base region 701 may be an N-base region, the second initial base region includes a second sub-initial base region 704 and a first sub-initial base region 705, the first sub-initial base region 705 is located on top of the second sub-initial base region 704, the cathode region 707 may be an n+ cathode region 707, and the first doped base region 801 and the second doped base region 802 may be p++ base regions.
In the method for manufacturing the gate-commutated thyristor unit in the above embodiment, the first doped base region 801 and the second doped base region 802 with the ion concentration greater than that of the second initial base region are formed on both sides of the top of the second initial base region, so that the first gate metal 708 is at least partially formed in the trench of the first doped base region 801, and the second gate metal 711 is at least partially formed in the trench of the second doped base region 802, and the ion concentrations of the first doped base region 801 and the second doped base region 802 in contact with the first gate metal 708 and the second gate metal 711 are enhanced, so that the path of the carriers generated by dynamic avalanche under the IGCT cathode flowing to the first gate metal 708 and/or the second gate metal 711 is shortened, and meanwhile, the high-concentration ion doping is beneficial to reducing the sheet resistance of the second initial base region near the gate, effectively reducing the risk of dynamic avalanche heavy triggering of the IGCT in the turn-off process, and improving the turn-off capability of the IGCT.
In addition, the first gate metal 708 and the second gate metal 711 are at least partially located in the trenches of the first doped base region 801 and the second doped base region 802, so that the height difference between the cathode metal 709 and the gate metal in the gate commutated thyristor unit can be increased, and the crimping type packaging of the gate commutated thyristor unit is facilitated.
In some embodiments, forming trenches on both sides of the top of the second initial base region includes forming a mask layer on the second initial base region, the mask layer including a first opening pattern and a second opening pattern on both sides, and etching and removing the second initial base region of a target thickness in the first opening pattern and the second opening pattern to form trenches on both sides of the top of the second initial base region, respectively. And forming a mask layer on the second initial base region, and forming a groove on the second initial base region by etching based on a mask plate to provide a base structure for subsequent ion implantation.
In some embodiments, a dry etching process is used to etch and remove the second initial base region of the target thickness within the first and second opening patterns. The method is favorable for optimizing the shape of the groove and reducing etching deviation.
Here, by controlling the depth of the trench, the thickness of the first gate metal 708 is greater than the depth of the trench of the first doped base region 801, and the thickness of the second gate metal 711 is greater than the depth of the trench of the second doped base region 802, so that the gate commutated thyristor unit is prevented from generating larger stress, and meanwhile, the first gate metal 708 and the second gate metal 711 completely cover the trenches of the first doped base region 801 and the second doped base region 802.
As an example, the doping concentration peaks of the first doping base region 801 and the second doping base region 802 areBy limiting the doping concentration of the first doping base region 801 and the second doping base region 802, the influence of the too high ion doping concentration of the first doping base region 801 and the second doping base region 802 on the performances of gate-cathode breakdown voltage, conduction voltage drop, parasitic capacitance, stability and the like of the IGCT is avoided.
As an example, the depth of the trench of the first doped base region 801 and the depth of the trench of the second doped base region 802 are both in the range of 0.5 μm to 6 μm, and the junction depth of the first doped base region 801 and the second doped base region 802 is in the range of 5 μm to 20 μm, which is more advantageous in avoiding the gate commutated thyristor cell from generating larger stress by limiting the trench depth and the junction depth range.
By way of example, the thickness of the first gate metal 708 and the thickness of the second gate metal 711 are both in the range of 8 μm to 15 μm, and by setting the thickness ranges of the first gate metal 708 and the second gate metal 711, it is ensured that the first gate metal 708 and the second gate metal 711 are at least partially located in the trenches of the first doped base region 801 and the second doped base region 802, and at the same time, it is capable of ensuring the height difference between the cathode metal 709 and the gate metal in the gate commutated thyristor unit, which is more advantageous for the compression-bonding type package of the gate commutated thyristor unit.
In some embodiments, the first doped base region and the second doped base region are formed at the connection positions of the grooves on the two sides of the top of the second initial base region and the second initial base region respectively, and the method comprises the steps of performing ion implantation of high-concentration doping on the connection positions of the grooves on the two sides of the top of the second initial base region and the second initial base region based on a mask layer formed on the second initial base region, and adopting an annealing process to form a first doped base region 801 and a second doped base region 802 at the connection positions of the grooves on the two sides of the top of the second initial base region and the second initial base region respectively. The first doped base region 801 and the second doped base region 802 formed by high-concentration doped ion implantation, annealing and junction pushing are performed by using the mask layer etched by the groove, so that consumption of the mask layer is reduced, and the first doped base region 801 and the second doped base region 802 can be formed rapidly and stably.
As an example, a push-junction process may also be employed after the annealing process to more precisely control the introduction and distribution of doping atoms, thereby achieving precise tuning of IGCT electrical characteristics.
As an example, please refer to fig. 9, fig. 9 is a graph comparing the cathode current during the turn-off of the gate commutated thyristor unit of the present application with the cathode current during the turn-off of the conventional gate commutated thyristor unit. The blue line in FIG. 9 shows a gate-commutated thyristor cell according to the present application, wherein the depth of the trench is 5 μm, the junction depth of the P++ base region formed is 15 μm, and the peak doping concentration of the P++ base region isAnd in the case that both the conventional IGCT chip structure (red line in fig. 9) and the patent IGCT chip structure employ the technology of the waved junction P base region 901. Since the regions of the IGCT close to and remote from the gate contact always have slightly different gate impedances, there will be a slight time offset between the individual IGCT cathode rings during the current turn-off, which will lead to a redistribution of the current during turn-off, with the IGCT cathode rings remote from the gate contact being subject to current crowding and thus failure. For ease of comparison, only the cathode currents in a conventional IGCT chip and an IGCT chip of the present application during shutdown are shown in fig. 9. After the cathode-to-gate commutation is completed in the IGCT turn-off process, if the cathode current exceeds 10% of the turn-on current, the cathode can be judged to be in a retrigger failure. As can be seen from fig. 9, the cathode current of the conventional structure increases significantly, and the cathode re-triggering failure will occur before the IGCT of the structure of the present application. At time t1, the cathode current of the traditional IGCT reaches 181A, and the failure of the cathode re-triggering turn-off is judged, but the cathode current of the IGCT is not obviously increased and is normally turned off.
As an example, please refer to fig. 9 and 10, fig. 10 is a graph comparing the current distribution of the gate commutated thyristor unit of the present application at the turn-off time with that of the conventional gate commutated thyristor unit. As can be seen from fig. 10, at time t1 in fig. 9, a significant current density increase phenomenon, that is, a cathode re-triggering failure, occurs in the cathode center in fig. 10 (a) (conventional IGCT), whereas no abnormality is found in the cathode center in fig. 10 (b) (IGCT structure of the present application), and current flows through the cathode to the gate.
As an example, please refer to fig. 9 and 11, fig. 11 is a diagram showing a comparison of the potential distribution of the gate commutated thyristor unit of the present application at the turn-off time and the conventional gate commutated thyristor unit at the turn-off time. As can be seen from fig. 11, at time t1 in fig. 9, the potential of fig. 11 (a) (conventional IGCT) below the cathode center thereof reaches 0.7V, which causes the positive bias of the PN junction formed by the second sub-initial base region 704, n+ cathode region 707, which also causes the re-triggering failure of the cathode center, while the potential of fig. 11 (b) (IGCT structure) below the cathode center thereof is still negative (about-9.6V), which is still in the reverse bias state.
In some embodiments, the embodiment of the disclosure further provides a semiconductor device, which comprises the gate commutated thyristor unit in any embodiment, so that the risk of dynamic avalanche re-triggering of the IGCT in the turn-off process can be effectively reduced, and the turn-off capability of the IGCT is improved.
In some embodiments, the present disclosure provides an electronic device comprising a gate commutated thyristor unit in any of the embodiments described above, or a semiconductor device as in any of the embodiments of the present disclosure. Such as, but not limited to, high capacity power electronics, high voltage direct current transmission systems, grid stabilization devices, high power motor drive systems, renewable energy generation systems, uninterruptible Power Supply (UPS) systems, energy storage systems, and the like.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features of the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples merely represent several embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.
Claims (11)
1. A gate commutated thyristor unit, characterized by comprising the following steps:
The anode region, the first initial base region, the second initial base region and the cathode region are sequentially arranged from anode metal to cathode metal, the second initial base region comprises a first sub-initial base region and a second sub-initial base region, the first sub-initial base region is positioned at the top of the second sub-initial base region, and the ion concentration in the first sub-initial base region is greater than that of the second sub-initial base region;
the first doped base region and the second doped base region are respectively positioned at two sides of the top of the first sub-initial base region;
The first gate metal is at least partially positioned in the groove of the first doping base region;
a second gate metal at least partially within the trench of the second doped base region;
The first doped base region and the second doped base region have ion concentrations larger than those of the first sub-initial base region, the thickness of the first gate metal is larger than the depth of a groove of the first doped base region, and the thickness of the second gate metal is larger than the depth of a groove of the second doped base region.
2. The gate commutated thyristor unit of claim 1, wherein the depth of the trench of the first doped base region and the depth of the trench of the second doped base region are each in the range of 0.5 μιη to 6 μιη, and the junction depth of the first doped base region and the second doped base region is in the range of 5 μιη to 20 μιη.
3. The gate commutated thyristor cell of claim 1, wherein the first and second doped base regions have a peak doping concentration of。
4. The gate commutated thyristor unit of claim 1, wherein the second initial base region comprises a planar junction or a wavelike junction.
5. The gate commutated thyristor unit of claim 1, wherein the thickness of the first gate metal and the thickness of the second gate metal are each in the range of 8 μιη to 15 μιη.
6. A semiconductor device, comprising:
a gate commutated thyristor unit as claimed in any one of claims 1 to 5.
7. An electronic device, comprising:
a gate commutated thyristor unit as claimed in any one of claims 1 to 5, or
The semiconductor device of claim 6.
8. The preparation method of the gate commutated thyristor unit is characterized by comprising the following steps:
Forming an anode region, a first initial base region, a second initial base region and a cathode region in sequence from anode metal to cathode metal, wherein the second initial base region comprises a first sub-initial base region and a second sub-initial base region, the first sub-initial base region is positioned at the top of the second sub-initial base region, and the ion concentration in the first sub-initial base region is greater than that of the second sub-initial base region;
Forming grooves on two sides of the top of the first sub-initial base region respectively;
forming a first doped base region and a second doped base region at the connection positions of grooves on two sides of the top of the first sub-initial base region and the first sub-initial base region respectively, wherein the ion concentration in the first doped base region and the second doped base region is larger than that of the first sub-initial base region;
Forming a first gate metal and a second gate metal in the groove of the first doping base region and the groove of the second doping base region respectively;
The conductivity types of the anode region, the second initial base region, the first doped base region and the second doped base region are the same, and the conductivity types of the first initial base region and the cathode region are the same and different from the conductivity type of the anode region; the thickness of the first gate metal is larger than the depth of the groove of the first doping base region, and the thickness of the second gate metal is larger than the depth of the groove of the second doping base region.
9. The method for manufacturing a gate commutated thyristor unit according to claim 8, wherein forming trenches on both sides of the top of the first sub-initial base region comprises:
forming a mask layer on the first sub-initial base region, wherein the mask layer comprises a first opening pattern and a second opening pattern which are positioned at two sides;
And etching and removing the first sub-initial base region with the target thickness in the first opening pattern and the second opening pattern so as to form grooves on two sides of the top of the first sub-initial base region respectively.
10. The method for manufacturing a gate commutated thyristor unit according to claim 9, wherein the first sub-initial base region of the target thickness is etched and removed in the first and second opening patterns by a dry etching process.
11. The method for manufacturing a gate commutated thyristor unit according to claim 9, wherein forming the first doped base region and the second doped base region at the connection between the trenches on both sides of the top of the first sub-initial base region and the first sub-initial base region respectively comprises:
Performing ion implantation of high-concentration doping on the connection parts of the grooves on the two sides of the top of the first sub-initial base region and the first sub-initial base region based on a mask layer formed on the first sub-initial base region;
and an annealing process is adopted to form a first doped base region and a second doped base region at the connection positions of the grooves at the two sides of the top of the first sub-initial base region and the first sub-initial base region respectively.
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