CN118764030B - A signal synchronization acquisition method, device and computer readable storage medium - Google Patents

Abstract

The invention discloses a signal synchronous acquisition method, a signal synchronous acquisition device and a computer readable storage medium, and belongs to the technical field of satellite-borne synthetic aperture radar data formers. The method comprises the following steps: respectively carrying out delay setting on the input repetition frequency pulse by using a first preset condition and a second preset condition to obtain a plurality of first delay codes corresponding to the first preset condition and a plurality of second delay codes corresponding to the second preset condition; data sampling is carried out on each acquisition board card, and sampling signal time delays corresponding to a plurality of first delay codes and sampling signal time delays corresponding to a plurality of second delay codes of each acquisition board card are determined; determining a target delay code combination corresponding to each acquisition board card; and based on the target delay code combination corresponding to each acquisition board card, the synchronous acquisition of signals is completed. By the method, the influence of temperature on synchronous acquisition of signals among multiple channels is reduced, and the synchronism of signal acquisition among acquisition boards is improved.

Description

A signal synchronization acquisition method, device and computer readable storage medium

Technical Field

The present invention belongs to the technical field of satellite-borne synthetic aperture radar data generators, and in particular relates to a signal synchronization acquisition method, device and computer-readable storage medium.

Background Art

The data generator of the spaceborne synthetic aperture radar includes: a high-speed analog-to-digital converter (ADC) and a field programmable gate array (FPGA). The ADC completes the continuous analog-to-digital conversion of the input analog signal, and the converted data is output to the FPGA. The FPGA uses the falling edge of the input pulse recurrence frequency (PRF) pulse signal as the sampling start time to complete the reception and processing of the sampling data.

In the prior art, first, the sampling clocks of each board adopt the same source clock, and the cables from the sampling clock to each board are strictly equal in length to ensure that the sampling clock reaches the ADC sampling clock input pin in strict phase consistency; then the data synchronization clock and the parallel data line between each board are strictly equal in length to ensure that the data synchronization clock and the data reach the FPGA input pin in strict phase consistency; finally, the PRF cables from the monitoring timer to the data forming each acquisition board are strictly equal in length to ensure that the PRF reaches the FPGA input pin in strict phase consistency. However, after the ADC is reset, although the data synchronization clock output by the ADC maintains a fixed phase output, there is a possibility that the delayed PRF and the stable output data synchronization clock edge are aligned, which will cause the data synchronization clock to be in an uncertain state when the falling edge of the PRF is collected. The moment when the falling edge of the PRF is detected may be advanced or delayed by one cycle, resulting in uncertainty in the moment of the falling edge of the PRF detected by the FPGA, thereby affecting the synchronization of signal acquisition.

Summary of the invention

In order to solve the above technical problems, the present invention provides a signal synchronous acquisition method, device and computer-readable storage medium, which ensure the synchronization of signal acquisition between acquisition boards.

To achieve the above purpose, the technical solution adopted by the present invention is as follows:

An embodiment of the present invention provides a method for synchronously collecting signals, the method comprising:

Delaying the input repetition frequency pulses using the first preset condition and the second preset condition respectively to obtain a plurality of first delay codes corresponding to the first preset condition and a plurality of second delay codes corresponding to the second preset condition;

Based on each first delay code of the plurality of first delay codes and each second delay code of the plurality of second delay codes, data sampling is performed on each acquisition board in sequence to determine acquisition signal delays corresponding to the plurality of first delay codes and acquisition signal delays corresponding to the plurality of second delay codes of each acquisition board;

Determine a target delay code combination corresponding to each acquisition board based on sampling signal delays corresponding to the plurality of first delay codes and sampling signal delays corresponding to the plurality of second delay codes;

Based on the target delay code combination corresponding to each acquisition board, the synchronous acquisition of the signal is completed.

The embodiment of the present invention provides a signal synchronization acquisition device, the device comprising: a setting unit, a determination unit and a completion unit; wherein:

The setting unit is used to set the delay of the input repetition frequency pulse by using the first preset condition and the second preset condition respectively, and obtain a plurality of first delay codes and a plurality of second delay codes corresponding to the preset acquisition boards;

The determining unit is used to determine the sampling delay of the initial first data based on the initial first delay code of the first acquisition board until the sampling delays of multiple first data are determined; the first acquisition board is any one of the preset acquisition boards;

The determining unit is further configured to determine the sampling delay of the initial second data based on the initial second delay code of the first acquisition board, until the sampling delays of the plurality of second data are determined;

The determining unit is further configured to determine the target delay code combinations corresponding to the preset acquisition boards based on the sampling delays of the plurality of first data and the sampling delays of the plurality of second data;

The completion unit is used to complete the synchronous acquisition of signals based on the target delay code combinations corresponding to the preset acquisition boards.

An embodiment of the present invention provides a signal synchronization acquisition device, comprising:

A memory for storing executable instructions;

The processor is used to execute the executable instructions stored in the memory. When the executable instructions are executed, the processor executes the signal synchronization acquisition method.

An embodiment of the present invention provides a computer-readable storage medium, wherein the storage medium stores executable instructions, and when the executable instructions are executed, the processor is used to execute the signal synchronization acquisition method as described in the embodiment of the present invention.

The beneficial effects of the present invention are:

The input repetitive frequency pulse is delayed twice according to two different preset conditions, and finally a group of target delay codes corresponding to each acquisition board is obtained. According to the target delay code combination corresponding to each acquisition board, the synchronous acquisition of the signal is completed, thereby improving the synchronization of signal acquisition between acquisition boards.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart of a signal synchronization acquisition method provided by an embodiment of the present invention;

FIG2 is a single-machine connection diagram of a synthetic aperture radar system provided by an embodiment of the present invention;

FIG3 is a reset timing effect diagram of a high-speed analog-to-digital conversion chip provided by an embodiment of the present invention;

FIG4 is a schematic diagram of the working effect of a data generator provided by an embodiment of the present invention;

FIG5 is a schematic diagram showing the effect of a repetitive frequency pulse being delayed twice provided by an embodiment of the present invention;

FIG6 is another flow chart of a signal synchronization acquisition method provided by an embodiment of the present invention;

FIG7 is a schematic diagram of the structure of a signal synchronization acquisition device provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of the structure of another signal synchronization acquisition device provided by an embodiment of the present invention.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

In order to make the technical personnel in this field better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Figure 1 is a flow chart of a signal synchronization acquisition method provided by an embodiment of the present invention, which will be specifically described in conjunction with the following steps.

S101 , using a first preset condition and a second preset condition to respectively set a delay on an input repetition frequency pulse, to obtain a plurality of first delay codes corresponding to the first preset condition and a plurality of second delay codes corresponding to the second preset condition.

In an embodiment of the present invention, the signal synchronization acquisition device delays the input repetition frequency pulse according to two preset time interval conditions, and obtains multiple delay codes corresponding to the two preset conditions, that is, multiple first delay codes corresponding to the first preset condition and multiple second delay codes corresponding to the second preset condition.

In the embodiment of the present invention, PRF (pulse repetition frequency) is a repetition frequency pulse, which is a periodic pulse signal, and its periodic frequency is the reciprocal of the pulse repetition interval (pulse repetition interval, PRI), and the pulse repetition interval is the time interval between one pulse and the next pulse.

In an embodiment of the present invention, the delay of the input repetitive frequency pulse signal is implemented by the IDELAY primitive inside the FPGA. IDELAY sets the signal delay time according to the delay step value. There are 31 stepping gears, corresponding to step values 0 to 31. For each additional step value, the signal delay time increases by 78ps. In an embodiment of the present invention, for a GHz sampling clock, 78ps is used as the first incremental step, and the first preset condition corresponds to 31 delay step values; for a hundred MHz signal to a synchronous clock, 78 x 7ps is used as the second incremental step, and the second preset condition corresponds to 5 delay step values: 0, 7, 14, 21, 28. The delay code is the delay step value.

In an embodiment of the present invention, the first delay time corresponding to the repetition frequency pulse PRF preset according to the first incremental step is: T0, T1, T2,..., Tn; the second delay time corresponding to the repetition frequency pulse PRF preset according to the second incremental step is: t0, t1,..., tn.

It should be noted that, in the embodiment of the present invention, the signal synchronization acquisition device can first obtain multiple first delay codes, perform data sampling based on the multiple first delay codes, and then determine the first PRF delay code for resetting the ADC on multiple acquisition boards based on the data sampling results corresponding to the first delay codes, so as to achieve synchronization of ADC acquisition echo signals between multiple boards and synchronization between ADC output DCLK and parallel data. Then, multiple second delay codes are obtained, data sampling is performed based on the multiple second delay codes, and then the second PRF delay code is determined based on the data sampling results corresponding to the second delay code, so as to achieve synchronous acquisition of the sampling synchronization clock between multiple boards at the falling edge of the PRF.

S102, based on each first delay code in the multiple first delay codes and each second delay code in the multiple second delay codes, perform data sampling on each acquisition board in at least one acquisition board, and determine the sampling signal delays corresponding to the multiple first delay codes and the sampling signal delays corresponding to the multiple second delay codes corresponding to each acquisition board.

In an embodiment of the present invention, the signal synchronization acquisition device performs data sampling on each acquisition board of at least one preset acquisition board based on each first delay code obtained under the first preset condition and each second delay code obtained under the second preset condition, and determines the sampling signal delay corresponding to the multiple first delay codes corresponding to each acquisition board and the sampling signal delay corresponding to the multiple second delay codes.

In the embodiment of the present invention, data delay refers to the time required for transmission from one end of a network to another end.

S103: Determine a target delay code combination corresponding to each acquisition board based on sampling signal delays corresponding to a plurality of first delay codes and sampling signal delays corresponding to a plurality of second delay codes.

In an embodiment of the present invention, the signal synchronization acquisition device determines the first delay code and the second delay code corresponding to each acquisition board according to the acquired sampling signal delays corresponding to multiple first delay codes and the sampling signal delays corresponding to multiple second delay codes, and according to the signal acquisition delay results.

S104, completing synchronous acquisition of signals based on the first delay code and the second delay code corresponding to each acquisition board.

In an embodiment of the present invention, the signal synchronization acquisition device delays the repetitive frequency pulse of each acquisition board in turn according to the first delay code and the second delay code determined by each acquisition board, thereby completing the synchronous acquisition of signals between each board.

In an embodiment of the present invention, as shown in FIG2, FIG2 is a single-machine connection relationship diagram of a satellite-borne synthetic aperture radar system provided by an embodiment of the present invention. In FIG2, the data former digitizes the analog echo signal input by the radar receiver; the monitoring timer generates a repetition frequency pulse, i.e., the sampling start input pulse repetition frequency and provides it to the data former, and the sampling clock and working clock corresponding to the data former, the monitoring timer and the receiver are all derived from the same reference source. The cables from the receiver output to the input of each acquisition board are strictly equal in length to ensure that the delay of the signal reaching the input end of each acquisition board is the same; the cables from the reference source to the clock input end of each acquisition board are strictly equal in length to ensure that the delay of the sampling clock reaching the clock input end of each acquisition board is the same; the cables from the monitoring timer repetition frequency pulse output to the repetition frequency pulse input end of each acquisition board are strictly equal in length to ensure that the delay of the repetition frequency pulse to each acquisition board is the same.

In an embodiment of the present invention, FIG4 is a schematic diagram of the working effect of a data former provided by an embodiment of the present invention. Combined with FIG4, in this method, according to the preset conditions, the input repetition frequency pulse is delayed twice in the field programmable array, the first delay ensures the synchronization between the output data synchronization clock of the high-speed analog-to-digital conversion chip and the collected data between the acquisition boards (i.e., between acquisition boards 1, 2, and 3); the second delay ensures the synchronization between the data synchronization clock and the falling edge of the input repetition frequency pulse between the acquisition boards (i.e., between acquisition boards 1, 2, and 3), and the reset eliminates the influence of the phase relationship between the data synchronization clock and the input repetition frequency pulse that may be caused by the high-speed analog-to-digital conversion chip, and secondly ensures that the synchronization between the boards is not affected by the temperature of each board; finally, the first delay code and the second delay code corresponding to each acquisition board are obtained, and according to the first delay code and the second delay code corresponding to each acquisition board, the input repetition frequency pulse of each board is delayed twice to complete the synchronous acquisition of the signal by each acquisition board, thereby improving the synchronization of data output between the acquisition boards.

In some embodiments of the present invention, S102 may be implemented through S1021 to S1022, which will be specifically described in conjunction with the following steps.

S1021. Based on each first delay code among the multiple first delay codes, delay the input repetition frequency pulse, perform data sampling on the falling edge of the delayed repetition frequency pulse, and determine the sampling signal delays corresponding to the multiple first delay codes.

In some embodiments of the present invention, the signal synchronization acquisition device delays the input repetition frequency pulse according to each first delay code, uses the first input repetition frequency pulse after the delay to reset the high-speed analog-to-digital conversion chip, obtains the data synchronization clock, and records the sampling data collected starting from the falling edge of the delay pulse and the sampling signal delays corresponding to multiple first delay codes.

S1022. Based on each second delay code among the plurality of second delay codes, delay the input repetition frequency pulse, perform data sampling at the falling edge of the delayed second repetition frequency pulse, and determine sampling signal delays corresponding to the plurality of second delay codes.

In some embodiments of the present invention, the signal synchronization acquisition device delays the input repetitive frequency pulse according to each second delay code, uses the data synchronization clock obtained after the first delay to collect data on the falling edge of the repetitive frequency pulse after the second delay, and records the sampled data at this delay time and the sampling signal delays corresponding to multiple second delay codes.

In some embodiments of the present invention, S1021 and S1022 are sequentially executed; S1021 is executed first, and then S1022 is executed.

In some embodiments of the present invention, S1021 may be implemented through S201 to S204, which will be specifically described in conjunction with the following steps.

S201. Using a field programmable array and each first delay code, delay an input repetition frequency pulse to obtain a delayed first pulse.

In some embodiments of the present invention, the signal synchronization acquisition device completes the corresponding delay of the input repetition frequency pulse according to each first delay code through a field programmable array to obtain a delayed first pulse.

In some embodiments of the present invention, FPGA is the abbreviation of Field-Programmable Gate Array, which is a field programmable gate array. It is a product further developed on the basis of programmable devices such as PAL, GAL, CPLD, etc. It appears as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices. FPGA adopts a new concept of logic cell array LCA (LogicCell Array), which includes three parts: configurable logic module CLB (Configurable LogicBlock), input and output module IOB (Input Output Block) and internal wiring (Interconnect). FPGA uses the falling edge of the PRF pulse signal as the sampling start time to complete the reception and processing of ADC parallel data.

S202: Reset the clock frequency division module of the high-speed analog-to-digital conversion chip using the delayed first pulse to obtain a reset data synchronization clock.

In some embodiments of the present invention, the signal synchronization acquisition device uses the delayed first pulse to reset the clock division module of the high-speed analog-to-digital conversion chip to obtain the reset data synchronization clock.

In some embodiments of the present invention, the clock for FPGA to receive sampled data is the data synchronization clock output by the high-speed analog-to-digital conversion chip, which is generated by the sampling clock FCLK through the frequency division circuit inside the high-speed analog-to-digital conversion chip. FPGA uses the data synchronization clock as the working clock to determine the falling edge of PRF as the sampling start time, and starts receiving sampled data at this time.

S203 : Perform data sampling based on the reset data synchronization clock to obtain first sampled data.

In some embodiments of the present invention, the signal synchronization acquisition device performs data sampling according to the reset data synchronization clock to obtain first sampled data.

S204 . Obtain, according to the first sampling data, a sampling signal delay corresponding to a first delay code corresponding to the first sampling data, until a plurality of sampling signal delays corresponding to a plurality of first delay codes are obtained.

In some embodiments of the present invention, a signal synchronization acquisition device delays an input repetition frequency pulse according to a delay code among multiple first delay codes, uses the delayed first pulse to reset a clock division module of a high-speed analog-to-digital conversion chip, obtains a reset data synchronization clock, performs data sampling on a falling edge of a PRF based on the reset data synchronization clock, obtains first sampling data, obtains a sampling data delay corresponding to the first sampling data based on the first sampling data, until multiple sampling data delays corresponding to multiple first delay codes are obtained.

In some embodiments of the present invention, as shown in FIG3, FIG3 is a high-speed analog-to-digital conversion chip reset timing effect diagram provided by an embodiment of the present invention. In FIG3, when the high-speed analog-to-digital conversion chip reset signal and the sampling clock meet a certain timing relationship, after the high-speed analog-to-digital conversion chip is successfully reset, the data synchronization clock will maintain a fixed phase output. There is a fixed delay time between the start of the trigger and the end of the trigger, and the delayed input repetitive frequency pulse is used as the reset signal of the high-speed analog-to-digital conversion chip to ensure that the data synchronization clock maintains a fixed phase output. That is, each acquisition board of the data former receives its own delay code, delays the repetitive frequency pulse input by the field programmable array, and then outputs it to the high-speed analog-to-digital conversion chip for reset, until the initial phase of the data collected by each board is consistent and stable.

In some embodiments of the present invention, S1022 may be implemented through S301 to S303, which will be specifically described in conjunction with the following steps.

S301. Using a field programmable array and each second delay code, a repetitive frequency pulse after the first delay is delayed for a second time to obtain a delayed second pulse.

In some embodiments of the present invention, the signal synchronization acquisition device completes the corresponding delay of the input repetition frequency pulse according to each second delay code through a field programmable array to obtain the repetition frequency pulse after the second delay.

In some embodiments of the present invention, the second pulse is a repetition frequency pulse obtained by delaying the second delay code.

S302 , using the data synchronization clock obtained after the first delay to collect data at the falling edge of the repetition frequency pulse after the second delay to obtain second sampled data.

In some embodiments of the present invention, the signal synchronization acquisition device performs data sampling according to the reset data synchronization clock to obtain second sampled data.

S303 . Obtain a sampling data delay corresponding to the second sampling data according to the second sampling data, until a plurality of sampling data delays corresponding to a plurality of second delay codes are obtained.

In some embodiments of the present invention, a signal synchronization acquisition device delays a repetitive frequency pulse input according to a delay code among multiple second delay codes, and samples data at the falling edge of the second pulse after the delay using a data synchronization clock obtained by resetting after the first delay to obtain second sampled data, and obtains a sampled data delay corresponding to the second sampled data based on the second sampled data, until multiple sampled data delays corresponding to multiple second delay codes are obtained.

In some embodiments of the present invention, S103 may be implemented through S1031 to S1033, which will be specifically described in conjunction with the following steps.

S1031, selecting a certain intermediate delay value of the sampling signal delay corresponding to the first delay code corresponding to the reference board, if the difference between the sampling signal delay corresponding to a certain delay code of other acquisition boards and the reference intermediate delay value is zero, then the delay code corresponding to each board under the delay value is determined as the first intermediate delay code;

Select a certain intermediate delay value of the sampling signal delay corresponding to the second delay code corresponding to the reference board. If the difference between the sampling signal delay corresponding to a certain delay code of other acquisition boards and the reference intermediate delay value is zero, the delay code corresponding to each board under the delay value is determined as the second intermediate delay code.

A first phase interval is determined according to the multiple first phases; the first phase interval contains the same target first phase; and the number of the target first phases is greater than or equal to a first preset threshold.

In some embodiments of the present invention, the signal synchronization acquisition device finds an interval in which the phase value of each board data is stable among multiple first phases, namely, the first phase interval; in the multiple first phase intervals, the phase value is stable and unchanged.

S1032: Determine a first difference between each acquisition board and a target first phase corresponding to an acquisition board in at least one acquisition board.

In some embodiments of the present invention, after the signal acquisition synchronization device determines the first phase interval corresponding to each acquisition board, it performs a difference operation on the target first phases of any two acquisition boards to obtain a first difference; wherein the target first phase is any value of the first phase interval corresponding to each acquisition board.

S1033. Determine a second phase interval according to the multiple second phases; the second phase interval contains the same target second phase; and the number of the target second phases is greater than or equal to a second preset threshold.

In some embodiments of the present invention, the signal synchronization acquisition device finds an interval in which the phase value of each board data is stable in multiple second phases, namely, the second phase interval; in the multiple second phase intervals, the phase value is stable and unchanged.

S1034: Determine a second difference between each acquisition board and a target second phase corresponding to an acquisition board in at least one acquisition board.

In some embodiments of the present invention, after the signal acquisition synchronization device determines the second phase interval corresponding to each acquisition board, it performs a difference operation on the target second phases of any two acquisition boards to obtain a second difference; wherein the target second phase is any value of the second phase interval corresponding to each acquisition board.

S1035. Determine a first delay code and a second delay code corresponding to each acquisition board based on the first difference and the second difference.

In some embodiments of the present invention, the signal synchronization acquisition device determines the first delay code and the second delay code corresponding to each acquisition board based on the acquired first difference and second difference.

In some embodiments of the present invention, S1035 can be implemented through S401 to S403, which will be specifically described in conjunction with the following steps.

S401: If the first difference is an integer multiple of the high-speed analog-to-digital converter sampling clock, obtain a first delay code interval corresponding to the first phase interval.

In some embodiments of the present invention, the signal synchronization acquisition device performs a quotient operation on the first difference and the high-speed analog-to-digital converter sampling clock. If the first difference is an integer multiple of the high-speed analog-to-digital converter sampling clock, then the delay code gear range of the repetitive frequency pulse corresponding to the first phase interval is determined as the delay value range of the repetitive frequency pulse for resetting the high-speed analog-to-digital conversion chip, that is, the first delay code interval.

S402: If the second difference is an integer multiple of the data synchronization clock, obtain a second delay code interval corresponding to the second phase interval.

In some embodiments of the present invention, the signal synchronization acquisition device performs a quotient operation on the second difference and the data synchronization clock. If the second difference is an integer multiple of the data synchronization clock, then the delay code range of the repetition frequency pulse corresponding to the second phase interval is determined as the delay value range of the repetition frequency pulse for resetting the high-speed analog-to-digital conversion chip, that is, the second delay code interval. Since the delay range value of IDELAY is limited, for a signal synchronization clock of the 100 MHz level, when the second difference is an integer multiple of the data synchronization clock, 1/2 of the data synchronization clock period is usually used as the second delay code range.

S403: Determine a target delay code corresponding to each acquisition board based on the first delay code interval and the second delay code interval.

In some embodiments of the present invention, the signal synchronization acquisition device determines the first delay code and the second delay code corresponding to each acquisition board based on the first delay code interval and the second delay code interval.

In some embodiments of the present invention, S403 may be implemented through S4031 to S4032, which will be specifically described in conjunction with the following steps.

S4031. Determine a first intermediate delay code in a first delay code interval.

In some embodiments of the present invention, the signal synchronization acquisition device takes the middle value between the two boundaries of the first delay code interval and uses it as the first intermediate delay code.

S4032. Determine a second intermediate delay code in a second delay code interval.

In some embodiments of the present invention, the signal synchronization acquisition device takes the middle value between the two boundaries of the second delay code interval as the second intermediate delay code. The first intermediate delay code and the second intermediate delay code are target delay codes.

In some embodiments of the present invention, if there are three acquisition boards, the first intermediate delay codes are T1m, T2n, T3k, and the second intermediate delay codes are t1m, t2n, t3k, respectively, then the target delay codes of the repetitive frequency pulses corresponding to the three acquisition boards are finally determined to be (T1m, t1m), (T2n, t2n), (T3k, t3k). That is, under the corresponding PRF target delay code, the acquisition between the three boards can be guaranteed to be synchronized.

In some embodiments of the present invention, S104 may be implemented through S1041, which will be specifically described in conjunction with the following steps.

S1041. Based on the target delay code, the input repetition frequency pulse is delayed, and data sampling is performed according to the delayed target pulse to obtain target sampling data, thereby completing the synchronous acquisition of the signal.

In some embodiments of the present invention, the signal synchronization acquisition device delays the input repetition frequency pulse according to the acquired target delay code, and performs data sampling according to the delayed target pulse to obtain the target sampling data, thereby completing the synchronous acquisition of the signal.

In some embodiments of the present invention, as shown in FIG4, FIG4 is a schematic diagram of the working effect of a data former provided by an embodiment of the present invention. In FIG4, the digitization of the analog echo signal input to the radar receiver is completed by the data former, and the input repetition frequency pulse signal as the sampling start is generated and provided by the monitoring timer. The data former includes: three acquisition boards, each of which is composed of a high-speed analog-to-digital conversion chip and a field programmable array. The working clock of the field programmable array sampling data is the data synchronization clock output by the high-speed analog-to-digital conversion chip, and the data synchronization clock is generated by the sampling clock through the frequency division circuit inside the high-speed analog-to-digital conversion chip. When the high-speed analog-to-digital conversion chip reset signal and the sampling clock meet a certain timing relationship, after the high-speed analog-to-digital conversion chip is successfully reset, the data synchronization clock will maintain a fixed phase output, and the field programmable array uses the data synchronization clock to judge the falling edge of the repetition frequency pulse and use it as the sampling start time, at this time, the sampling data is received and processed, and finally the data is output.

In some embodiments of the present invention, FIG5 is a schematic diagram of the effect of a repetition frequency pulse being delayed twice provided by an embodiment of the present invention. In FIG5, there are three boards, and the repetition frequency pulse is delayed twice respectively. The first board 1, the second board 2, and the third board 3 make the output data synchronization clock of the high-speed analog-to-digital conversion chip and the parallel data synchronized after the input repetition frequency pulse is delayed once; after the repetition frequency pulse is delayed twice, the data synchronization clock between the first board 1, the second board 2, and the third board 3 is synchronized from the rising edge to the falling edge of the repetition frequency pulse.

It can be understood that in some embodiments of the present invention, the input repetition frequency pulse is delayed twice, the first delay ensures the synchronization between the output data synchronization clock and parallel data of the high-speed analog-to-digital conversion chip between multiple boards, and the second delay ensures the synchronization between the rising edge of the data synchronization clock and the falling edge of the repetition frequency pulse between multiple boards. In addition to eliminating the influence of the phase relationship between the data synchronization clock and the input repetition frequency pulse that may be caused by resetting the high-speed analog-to-digital conversion chip, it also ensures that the synchronization between the boards is not affected by the temperature of each board.

The embodiment of the present invention provides a signal synchronization acquisition method, as shown in FIG6 , which is another flow chart of a signal synchronization acquisition method provided by the embodiment of the present invention, and will be specifically described in conjunction with the following steps:

S1. Set the delay value of the input repetition frequency pulse in incremental steps.

In the embodiment of the present invention, the delay time of the sampling start signal PRF is preset in a certain incremental step: T0, T1, T2, ..., Tn. The monitoring timer sends the delay time T0 to the data former to reset the ADC with the delayed PRF.

S2. Send the delay value of the input repetition frequency pulse to the data former through a control instruction.

In some embodiments of the present invention, the monitoring timer sends the delay time T0 to the data former to reset the ADC with the delayed PRF.

S3. After the data former receives the control instruction, the field programmable array completes the corresponding delay of the input repetition frequency pulse.

S4. Use the first pulse of the delayed input repetitive frequency pulse as the reset of the high-speed analog-to-digital conversion chip.

S5. The data generator records the sampled data and analyzes the data delay.

S6. Change the input repetition frequency pulse delay gear, record the sampling data of different gears and analyze the data delay.

In an embodiment of the present invention, the delay time is set to continue the test at the next gear.

S7. Find the appropriate gear and record its use.

In an embodiment of the present invention, when all phase positions have been tested, the data delays of the boards are compared. First, find the intervals in which the data delay values of each board are stable, that is, within the delay time range of this PRF, the data delay value is stable. Compare the data delay values of the boards in their respective stable intervals. If the data delay difference between every two acquisition boards is an integer multiple of DCLK, then the delay time range of this PRF is determined as the PRF delay value range for resetting the ADC, and the middle value between the two boundaries of the range is the PRF delay value for resetting the ADC. If there are three boards, the PRF delay values for resetting the ADC of the three boards are set to T1m, T2n, and T3k.

S8. On the basis of the above delay of the input repetitive frequency pulse, the delay value of the input repetitive frequency pulse is set again in an incremental step.

S9. Send the delay value of the input repetition frequency pulse to the data former through a control instruction.

In the embodiment of the present invention, the delay time of the sampling start signal PRF is preset according to a certain incremental step: t0, t1, ..., tn.

S10. After the data former receives the control instruction, the field programmable array completes the corresponding delay of the input repetition frequency pulse.

In an embodiment of the present invention, the monitoring timer sends the delay time t0 to the acquisition board of the data generator, and each acquisition board delays the PRF again accordingly based on the delay in the first step.

S11. After the data former receives the control instruction, the field programmable array completes the second delay of the input repetition frequency pulse.

S12. The data generator records the sampled data and analyzes the data delay.

S13, changing the input repetition frequency pulse delay gear, recording the sampling data of different gears and analyzing the data delay.

S14, comparing the data delay values of each board and card, and finding the gear range where the data delay values of each board and card are the same and stable.

In the embodiment of the present invention, when all delay levels are tested, the data delays of the boards are compared. First, the level intervals corresponding to the delay values of each board are found when the data delay values of each board are the same, that is, within the delay time level range of this PRF.

S15. The middle value of the interval is determined as the gear for the second input repetition frequency pulse delay.

In some embodiments of the present invention, the middle value of the stable interval of each board is taken, and this value is the delay value to be determined in the second step. If there are three boards, the PRF delay values of the three boards are set to t1m, t2n, and t3k. The PRF delay values corresponding to the three boards are finally determined to be: (T1m, t1m), (T2n, t2n), (T3k, t3k). That is, under the corresponding PRF delay values, the acquisition between the three boards can be guaranteed to be synchronized.

In an embodiment of the present invention, the input repetitive frequency pulse is delayed twice according to preset conditions, the first delay ensures the synchronization between the output data synchronization clock and the parallel data of the high-speed analog-to-digital conversion chip; the second delay ensures the synchronization of the rising edge of the data synchronization clock between the acquisition boards to the falling edge of the input repetitive frequency pulse, eliminating the influence of the phase relationship between the data synchronization clock and the input repetitive frequency pulse that may be caused by resetting the high-speed analog-to-digital conversion chip, and secondly ensures that the synchronization between the boards is not affected by the temperature of each board; finally, the target delay code corresponding to each acquisition board is obtained, and the synchronous acquisition of the signal is completed according to the target delay code corresponding to each acquisition board, thereby improving the synchronization of signal acquisition between the acquisition boards.

The embodiment of the present invention provides a signal synchronization acquisition device, as shown in FIG7 , which is a schematic diagram of the structure of a signal synchronization acquisition device provided by the embodiment of the present invention, and the signal synchronization acquisition device 7 includes: a setting unit 701, a determination unit 702 and a completion unit 703; wherein,

The setting unit 701 is used to set the delay of the input repetition frequency pulse by using the first preset condition and the second preset condition respectively, and obtain a plurality of first delay codes and a plurality of second delay codes corresponding to the preset acquisition boards;

The determining unit 702 is used to determine the starting phase of the initial first data based on the initial first delay code of the first acquisition board, until the starting phases of multiple first data are determined; the first acquisition board is any one of the preset acquisition boards;

The determining unit 702 is further configured to determine the starting phase of the initial second data based on the initial second delay code of the first acquisition board, until the starting phases of the plurality of second data are determined;

The determining unit 702 is further configured to determine the target delay code corresponding to each of the preset acquisition boards based on the starting phases of the plurality of first data and the starting phases of the plurality of second data;

The completing unit 703 is used to complete the synchronous acquisition of the signal based on the target delay codes corresponding to the preset acquisition boards.

In some embodiments of the present invention, the determination unit 702 is further used to delay the input repetitive frequency pulse based on each first delay code among the multiple first delay codes, and perform data sampling based on the delayed first pulse to determine the multiple first phases; and to delay the input repetitive frequency pulse based on each second delay code among the multiple second delay codes, and perform data sampling based on the delayed second pulse to determine the multiple second phases.

In some embodiments of the present invention, the determination unit 702 is also used to delay the input repetition frequency pulse using each first delay code through a field programmable array to obtain a delayed first pulse; and, using the delayed first pulse to reset the clock division module of the high-speed analog-to-digital converter to obtain a reset data synchronization clock; and, based on the reset data synchronization clock, perform data sampling to obtain first sampling data; and, based on the first sampling data, obtain a first phase corresponding to the first sampling data, until the multiple first phases corresponding to the multiple first delay codes are obtained.

In some embodiments of the present invention, the determination unit 702 is further used to delay the input repetition frequency pulse by using each second delay code through a field programmable array to obtain a delayed second pulse; and, based on the data synchronization clock after the first delay reset, perform data sampling on the falling edge of the delayed second pulse to obtain second sampled data; and, based on the second sampled data, obtain a second phase corresponding to the second sampled data until the multiple second phases corresponding to the multiple second delay codes are obtained.

In some embodiments of the present invention, the determination unit 702 is further used to determine a first phase interval based on the multiple first phases; the first phase interval contains the same target first phase; the number of the target first phases is greater than or equal to a first preset threshold; and, determine a first difference between the target first phase corresponding to each acquisition board and the acquisition board in at least one acquisition board; and, determine a second phase interval based on the multiple second phases; the second phase interval contains the same target second phase; the number of the target second phases is greater than or equal to a second preset threshold; and, determine a second difference between the target second phase corresponding to each acquisition board and the acquisition board in at least one acquisition board; and, based on the first difference and the second difference, determine the target delay code corresponding to each acquisition board.

In some embodiments of the present invention, the determination unit 702 is further used to obtain a first delay code interval corresponding to the first phase interval if the first difference is an integer multiple of the sampling clock; and, if the second difference is an integer multiple of the data synchronization clock, obtain a second delay code interval corresponding to the second phase interval; and, based on the first delay code interval and the second delay code interval, determine the target delay code corresponding to each acquisition board.

In some embodiments of the present invention, the determination unit 702 is further used to determine a first intermediate delay code in the first delay code interval; and, to determine a second intermediate delay code in the second delay code interval; and, to use the first intermediate delay code and the second intermediate delay code as the target delay code.

In some embodiments of the present invention, the completion unit 703 is also used to delay the input repetition frequency pulse based on the target delay code, and perform data sampling according to the delayed target pulse to obtain target sampling data, thereby completing the synchronous acquisition of the signal.

It can be understood that in the above-mentioned device implementation scheme, the input repetitive frequency pulse is delayed twice according to preset conditions. The first delay ensures the synchronization between the output data synchronization clock and the parallel data of the high-speed analog-to-digital conversion chip between the acquisition boards; the second delay ensures the synchronization of the rising edge of the data synchronization clock between the acquisition boards to the falling edge of the input repetitive frequency pulse. In addition to eliminating the influence of the phase relationship between the data synchronization clock and the input repetitive frequency pulse that may be caused by resetting the high-speed analog-to-digital conversion chip, it also ensures that the synchronization between the boards is not affected by the temperature of each board; finally, the target delay code corresponding to each acquisition board is obtained, and the synchronous acquisition of the signal is completed according to the target delay code corresponding to each acquisition board, thereby improving the synchronization of signal acquisition between the acquisition boards.

Based on the method of the above embodiment, a structural diagram of a signal synchronization acquisition device provided by an embodiment of the present invention is shown in Figure 8. Figure 8 is a structural diagram of a signal synchronization acquisition device provided by an embodiment of the present invention, including: a processor 801 and a memory 802; the memory 802 stores one or more programs executable by the processor 801. When one or more programs are executed, a signal synchronization acquisition device corresponding to the above-mentioned embodiment is executed by the processor 801.

The embodiment of the present invention provides a computer-readable storage medium storing executable instructions for causing a processor to execute the instructions to implement the signal synchronization acquisition method.

It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program codes.

The present invention is described with reference to the flowchart and/or block diagram of the method, device (system), and computer program product according to the embodiment of the present invention. It should be understood that each process and/or box in the flowchart and/or block diagram, as well as the combination of the processes and/or boxes in the flowchart and/or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate a device for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention.

Claims (7)

1. A signal synchronous acquisition method, characterized in that it comprises the following steps: Delaying the input repetition frequency pulses using the first preset condition and the second preset condition respectively to obtain a plurality of first delay codes corresponding to the first preset condition and a plurality of second delay codes corresponding to the second preset condition; Based on each first delay code of the plurality of first delay codes and each second delay code of the plurality of second delay codes, data sampling is performed on each acquisition board to determine the sampling signal delays corresponding to the plurality of first delay codes and the sampling signal delays corresponding to the plurality of second delay codes of each acquisition board; Determine a target delay code combination corresponding to each acquisition board based on sampling signal delays corresponding to a plurality of first delay codes and sampling signal delays corresponding to a plurality of second delay codes; Based on the target delay code combination corresponding to each acquisition board, the synchronous acquisition of the signal is completed; The step of determining the target delay code combination corresponding to each acquisition board based on the sampling signal delays corresponding to the plurality of first delay codes and the sampling signal delays corresponding to the plurality of second delay codes comprises: Determine, according to the plurality of first delay codes, a sampling signal delay interval corresponding to the first delay code; Taking one of the acquisition boards as a reference, determining a first difference between the sampling signal delays corresponding to the target first delay code corresponding to each of the other acquisition boards and the acquisition board; Determine, according to the plurality of second delay codes, a sampling signal delay interval corresponding to the second delay code; Taking one of the acquisition boards as a reference, determining a second difference between the sampling signal delays corresponding to the target second delay code corresponding to each of the other acquisition boards and the acquisition board; Based on the first difference and the second difference, determining a target delay code combination corresponding to each acquisition board; The step of determining the target delay code combination corresponding to each acquisition board based on the first difference and the second difference includes: Select a certain intermediate delay value of the sampling signal delay corresponding to the first delay code corresponding to the reference board. If the difference between the sampling signal delay corresponding to a certain delay code of other acquisition boards and the reference intermediate delay value is zero, the delay code corresponding to each board under the delay value is determined as the first intermediate delay code. Select a certain intermediate delay value of the sampling signal delay corresponding to the second delay code corresponding to the reference board. If the difference between the sampling signal delay corresponding to a certain delay code of other acquisition boards and the reference intermediate delay value is zero, the delay code corresponding to each board under the delay value is determined as the second intermediate delay code. The first intermediate delay code and the second intermediate delay code are combined as the target delay code. 2. A signal synchronous acquisition method according to claim 1, characterized in that the step of performing data sampling on each acquisition board based on each first delay code of the plurality of first delay codes and each second delay code of the plurality of second delay codes, and determining the sampling signal delay corresponding to the plurality of first delay codes and the sampling signal delay corresponding to the plurality of second delay codes corresponding to each acquisition board comprises: Based on each first delay code of the plurality of first delay codes, the input repetition frequency pulse is delayed, and data sampling is performed on the falling edge of the delayed repetition frequency pulse to determine the sampling signal delay corresponding to the plurality of first delay codes; Based on each second delay code among the multiple second delay codes, the repetitive frequency pulse delayed by the first delay code is delayed for a second time, and data sampling is performed on the falling edge of the repetitive frequency pulse after the second delay to determine the sampling signal delay corresponding to the multiple second delay codes. 3. A signal synchronization acquisition method according to claim 2, characterized in that the input repetition frequency pulse is delayed based on each first delay code in the plurality of first delay codes, and data sampling is performed on the falling edge of the delayed repetition frequency pulse to determine the sampling signal delay corresponding to the plurality of first delay codes, comprising: By means of a field programmable array, using each of the first delay codes, delaying the input repetition frequency pulse to obtain a delayed repetition frequency pulse; Resetting the data synchronization clock output by the ADC using the first pulse of the delayed repetition frequency pulse to obtain a reset data synchronization clock; Based on the reset data synchronization clock, data sampling is performed at the falling edge of the delayed repetition frequency pulse to obtain first sampled data; The time delay corresponding to the first sampling data is obtained according to the first sampling data, until the multiple sampling signal time delays corresponding to the multiple first delay codes are obtained. 4. A signal synchronous acquisition method according to claim 2, characterized in that, based on each second delay code in the plurality of second delay codes, a second delay is performed on the repetitive frequency pulse after the first delay, and data sampling is performed on the falling edge of the repetitive frequency pulse after the second delay code delay, and the plurality of sampling signal delays corresponding to the plurality of second delay codes are determined, comprising: By means of a field programmable array, using each second delay code, delaying the input repetition frequency pulse after the first delay to obtain a pulse after the second delay; Based on the data synchronization clock reset after the first delay, data sampling is performed on the falling edge of the repetition frequency pulse obtained after the second delay to obtain second sampled data; According to the second sampling data, a sampling signal delay corresponding to the second sampling data is obtained, until the multiple sampling signal delays corresponding to the multiple second delay codes are obtained. 5. A signal synchronous acquisition method according to any one of claims 1 to 4, characterized in that the synchronous acquisition of the signal is completed based on the target delay code combination corresponding to each acquisition board, comprising: Based on the target delay code combination, the input repetition frequency pulse is delayed twice in succession, and data is sampled according to the repetition frequency pulse after the second delay to obtain target sampling data, thereby completing the synchronous acquisition of the target signal by each acquisition board. 6. A signal synchronous acquisition device, characterized in that it comprises: A memory for storing executable instructions; The processor is used to implement the signal synchronization acquisition method described in any one of claims 1 to 5 when executing the executable instructions stored in the memory. 7. A computer-readable storage medium, characterized in that the storage medium stores executable instructions, and when the executable instructions are executed, they are used to cause a processor to execute the signal synchronization acquisition method according to any one of claims 1 to 5.