CN118760627A - Address updating device and method, processor and chip - Google Patents

Abstract

The present disclosure relates to an address updating apparatus and method, a processor and a chip, the address updating apparatus comprising: an address updating unit, a page table updating source, a memory address management unit and a memory; the address updating unit receives an updating request from a page table updating source, wherein the updating request comprises a virtual address and a first physical address corresponding to the virtual address; and the address updating unit updates page table information which is respectively corresponding to the memory and the memory address management unit and is used for describing the mapping relation between the virtual address and the first physical address according to the acquired updating request. According to the embodiment of the disclosure, the address updating unit is introduced, and the address updating unit serving as hardware directly updates the page table information in the memory and the page table information of the memory address management unit, so that software and hardware interaction in system operation is reduced, the page table updating flow is simplified, and the system operation efficiency is improved.

Description

Address updating device and method, processor and chip

Technical Field

The present disclosure relates to the field of computer technology, and in particular to an address updating device and method, a processor and a chip.

Background Art

In the compiled executable code, if the processor accesses instructions or data, a virtual address will be provided for the accessed instruction or data, and the page table in the memory address management unit that records the mapping relationship between the virtual address and the physical address will be queried to convert the virtual address into a physical address and access the instruction or data from the memory.

The memory address management unit's page table update is completed by software (such as a driver). The software will write the updated page table to the memory, and then initiate an invalidation operation to the memory address management unit to notify the memory address management unit that the page table is outdated. In this way, after receiving a new request, the memory address management unit will go to the memory to fetch the page table again, and finally cache it in the on-chip cache of the memory address management unit.

However, when the hardware needs to update the page table, it will first inform the software how to allocate the page table through the hardware-software interface, then write it to the memory, and then notify the memory address management unit to re-obtain the page table from the memory. For high-performance processors, this process takes a long time and affects the overall performance of the processor.

Summary of the invention

The present disclosure proposes a technical solution for address updating.

According to one aspect of the present disclosure, an address updating device is provided, the address updating device comprising: an address updating unit, a page table update source, a memory address management unit, and a memory; the address updating unit receives an update request from the page table update source, the update request comprising a virtual address, and a first physical address corresponding to the virtual address; the address updating unit updates page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, the page table information being used to describe a mapping relationship between the virtual address and the first physical address.

In a possible implementation, the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, including: the address update unit sends a first virtual address request carrying the virtual address to the memory address management unit according to the virtual address carried in the update request; the memory address management unit generates a read request for accessing the memory according to the first virtual address request; the address update unit intercepts the read request and sends the first physical address to the memory address management unit; the address update unit obtains a second physical address from the page table update source, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory.

In a possible implementation, the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, including: the address update unit waits for the page table update source to send an update request, and generates the page table information to be updated according to the previously obtained unprocessed update request; the address update unit intercepts the read request from the memory address management unit, and the read request is used to access the memory; the address update unit compares the read request with the page table information to be updated to obtain a comparison result; the address update unit updates the page table information to be updated and the page table information corresponding to the memory and the memory address management unit respectively in response to the comparison result indicating that the read request and the page table information to be updated have the same virtual address.

In a possible implementation, the address update unit is further used to feed back an update result to the page table update source, where the update result is used to indicate that the address update unit has completed the update of the memory and the memory address management unit.

In a possible implementation, the address update unit sends a first virtual address request carrying the virtual address to the memory address management unit based on the virtual address carried in the update request, including: the address update unit sends a first virtual address request carrying a first identifier and the virtual address to the memory address management unit; the read request includes the virtual address and the first identifier, and the first identifier is used to indicate that the source category of the virtual address is the update request; the address update unit intercepts the read request, including: the address update unit intercepts the read request in response to the read request containing the first identifier.

In a possible implementation, when the page table information includes a multi-level page table, the address update unit obtains a second physical address from the page table update source, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory, including: the address update unit sends a physical address request to the page table update source, and the physical address request includes a third identifier used to indicate the number of page table levels; the address update unit receives the second physical address fed back by the page table update source, and the second physical address corresponds to the third identifier; the address update unit writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory according to the second physical address corresponding to each third identifier.

In one possible implementation, the memory address management unit receives a second virtual address request from the page table update source, the second virtual address request carrying a virtual address and a second identifier; in response to the memory address management unit identifying, based on the second identifier, that the source category of the virtual address is a request of a category other than the update request, the memory address management unit returns a first physical address corresponding to the virtual address to the page table update source.

In one possible implementation, the address update unit transmits the read request from the memory address management unit to the memory in response to a read request including a second identifier; the address update unit transmits the return result of the memory in response to the read request to the memory address management unit, and the second identifier is used to indicate that the source category of the virtual address of the read request is a request of a category other than the update request.

In one possible implementation, the memory address management unit receives the first virtual address request, and queries the cache of the memory address management unit for the virtual address carried by the first virtual address request; if the virtual address is not found in the cache of the memory address management unit, space for storing page table information is allocated in the cache for the first virtual address request; or, if the virtual address is found in the cache of the memory address management unit, the associated space of the virtual address is cleared in the cache, and space for storing page table information is allocated in the cache for the first virtual address request.

According to one aspect of the present disclosure, there is provided an address updating method, which is applied to the address updating device, wherein the address updating device comprises: an address updating unit, a page table update source, a memory address management unit, and a memory; the method comprises: the address updating unit receiving an update request from the page table update source, the update request comprising a virtual address, and a first physical address corresponding to the virtual address; the address updating unit updates page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, the page table information being used to describe a mapping relationship between the virtual address and the first physical address.

In a possible implementation, the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, including: the address update unit sends a first virtual address request carrying the virtual address to the memory address management unit according to the virtual address carried in the update request; the memory address management unit generates a read request for accessing the memory according to the first virtual address request; the address update unit intercepts the read request and sends the first physical address to the memory address management unit; the address update unit obtains a second physical address from the page table update source, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory.

In a possible implementation, the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, including: the address update unit waits for the page table update source to send an update request, and generates the page table information to be updated according to the previously obtained unprocessed update request; the address update unit intercepts the read request from the memory address management unit, and the read request is used to access the memory; the address update unit compares the read request with the page table information to be updated to obtain a comparison result; the address update unit updates the page table information to be updated and the page table information corresponding to the memory and the memory address management unit respectively in response to the comparison result indicating that the read request and the page table information to be updated have the same virtual address.

In a possible implementation, the method further includes: the address update unit feeding back an update result to the page table update source, wherein the update result is used to indicate that the address update unit completes the update of the memory and the memory address management unit.

In a possible implementation, the address update unit sends a first virtual address request carrying the virtual address to the memory address management unit based on the virtual address carried in the update request, including: the address update unit sends a first virtual address request carrying a first identifier and the virtual address to the memory address management unit; the read request includes the virtual address and the first identifier, and the first identifier is used to indicate that the source category of the virtual address is the update request; the address update unit intercepts the read request, including: the address update unit intercepts the read request in response to the read request containing the first identifier.

In a possible implementation, when the page table information includes a multi-level page table, the address update unit obtains a second physical address from the page table update source, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory, including: the address update unit sends a physical address request to the page table update source, and the physical address request includes a third identifier used to indicate the number of page table levels; the address update unit receives the second physical address fed back by the page table update source, and the second physical address corresponds to the third identifier; the address update unit writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory according to the second physical address corresponding to each third identifier.

In one possible implementation, the method also includes: the memory address management unit receives a second virtual address request from the page table update source, the second virtual address request carries a virtual address and a second identifier; in response to the memory address management unit identifying, based on the second identifier, that the source category of the virtual address is a request of a category other than the update request, the memory address management unit returns the first physical address corresponding to the virtual address to the page table update source.

In a possible implementation, the method also includes: the address update unit transmits the read request from the memory address management unit to the memory in response to the read request sent by the memory address management unit including a second identifier; the address update unit transmits the return result of the memory in response to the read request to the memory address management unit, and the second identifier is used to indicate that the source category of the virtual address of the read request is a category request other than the update request.

In a possible implementation, the method also includes: the memory address management unit receives the first virtual address request, and queries the cache of the memory address management unit for the virtual address carried by the first virtual address request; if the virtual address is not found in the cache of the memory address management unit, space for storing page table information is allocated in the cache for the first virtual address request; or, if the virtual address is found in the cache of the memory address management unit, the associated space of the virtual address is cleared in the cache, and space for storing page table information is allocated in the cache for the first virtual address request.

According to one aspect of the present disclosure, a processor is provided, wherein the processor includes the address updating device as described above.

According to one aspect of the present disclosure, a chip is provided, wherein the chip includes the processor as described above.

According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

In the disclosed embodiment, the address update device includes: an address update unit, a page table update source, a memory address management unit, and a memory; the address update unit receives an update request from the page table update source, the update request includes a virtual address, and a first physical address corresponding to the virtual address; the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the acquired update request, and the page table information is used to describe the mapping relationship between the virtual address and the first physical address. In this way, by introducing the address update unit, the address update unit as hardware directly updates the page table information in the memory and the page table information of the memory address management unit, thereby reducing the software and hardware interaction in the system operation, simplifying the page table update process, and improving the system operation efficiency.

It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

FIG. 1 shows a block diagram of an address updating device according to an embodiment of the present disclosure.

FIG. 2 shows a schematic diagram of an address updating device according to an embodiment of the present disclosure.

FIG3 is a schematic diagram showing an address updating method according to an embodiment of the present disclosure.

FIG. 4 shows a block diagram of an electronic device according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

Figure 1 shows a block diagram of an address updating device according to an embodiment of the present disclosure. As shown in Figure 1, the address updating device includes: an address updating unit 1, a page table update source 2, a memory address management unit 3, and a memory 4; the address updating unit 1 is connected to the page table update source 2, and the address updating unit 1 receives an update request from the page table update source 2, and the update request includes a virtual address and a first physical address corresponding to the virtual address; the address updating unit 1 is connected between the memory address management unit 3 and the memory 4, and the address updating unit 1 updates the page table information corresponding to the memory 4 and the memory address management unit 3 respectively according to the obtained update request, and the page table information is used to describe the mapping relationship between the virtual address and the first physical address.

In one possible implementation, the address update unit 1, the page table update source 2, and the memory address management unit 3 can be implemented by a circuit board card or an integrated circuit composed of general analog components, digital circuit components, etc. The present disclosure does not limit the specific implementation method of the address update unit 1, the page table update source 2, and the memory address management unit 3.

In one possible implementation, the memory 4 can be composed of semiconductor storage units, such as random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, etc. The embodiments of the present disclosure do not limit the specific form of the memory 4.

In one possible implementation, the page table update source 2 is used to generate an update request, which is used to change the memory address management unit 3 and the page table information in the memory 4, and the page table information can be used to describe the mapping relationship between the virtual address and the first physical address. Optionally, the page table information may include N (N≥1) virtual addresses, and the first physical address corresponding to each virtual address. For example, the virtual address VA1 corresponds to the first physical address PA1, the virtual address VA2 corresponds to the first physical address PA2, and so on, the virtual address VAN corresponds to the first physical address PAN. Among them, the virtual address is the logical address used by the program code when it is running, and the program code can access the memory 4 through the virtual address instead of directly accessing the first physical address of the memory 4.

Optionally, the page table update source 2 can respond to the page table update requirements of the upstream software and generate an update request for changing the memory address management unit 3 and the page table information in the memory 4; for example, assuming that a thread requests more memory space, the thread can instruct the page table update source 2 to generate a page table update request, change the memory address management unit 3 and the page table information in the memory 4, and assign the first physical address occupied by other threads (such as invalid historical threads) to the virtual address of the thread.

Optionally, the page table update source 2 may also respond to the page table update requirements of the upstream hardware and generate an update request for changing the page table information in the memory address management unit 3 and the memory 4. For example, assuming that the device driver changes the value of a register of a certain hardware, since such a change will affect the physical address associated with the register, the page table information in the memory address management unit 3 and the memory 4 needs to be updated to reflect such a change. The hardware may send a timing signal to the page table update source 2, instructing the page table update source 2 to generate a page table update request, change the page table information in the memory address management unit 3 and the memory 4, and update the first physical address corresponding to the virtual address of the hardware register.

It should be understood that the page table update source 2 can respond to the page table update requirements of the upstream software (or hardware) and generate an update request for changing the memory address management unit 3 and the page table information in the memory 4, and the embodiments of the present disclosure are not limited to this.

In a possible implementation, the memory address management unit 3 can store the latest page table information for describing the mapping relationship between the virtual address and the first physical address, and is responsible for the mapping of the virtual address to the first physical address, and provides a hardware mechanism for memory access permission check (for example, it can be queried in the page table information whether there is a corresponding first physical address for an access request carrying a certain virtual address, so as to determine whether the access request has memory access permission), so as to improve the memory usage efficiency and system security. The memory address management unit 3 can also provide the user program with an operation interface such as the application and release of the memory 4.

Optionally, the memory address management unit 3 may include a cache, which is a high-speed memory having a data access speed faster than the memory 4, such as a cache memory. In the cache of the memory address management unit 3, page table information for describing the mapping relationship between the virtual address and the first physical address may be stored. The page table information cached by the memory address management unit 3 may be part of the page table information stored in the memory 4 (such as the latest page table information expected to be used in the near future), or may be all the page table information stored in the memory 4, and the present disclosure does not limit this.

In the example, a virtual address query can be performed based on the page table information cached by the memory address management unit 3. If the first physical address required by the virtual address is in the cache, the first physical address can be returned directly; if the first physical address required by the virtual address is not in the cache, access to the memory 4 can be initiated.

In one possible implementation, the address update unit 1 can be connected to the page table update source 2, the memory address management unit 3, and the memory 4, respectively, to receive an update request from the page table update source 2 carrying a virtual address and a first physical address corresponding to the virtual address, and update the page table information of the memory 4 and the memory address management unit 3 according to the received update request, so that the page table information has a mapping relationship between the virtual address indicated by the update request and the first physical address.

In this way, when the page table update source 2 has a page table mapping that needs to be updated to the memory address management unit 3 and the memory 4, the new page table information can be updated to the address update unit 1 first, and then the address update unit 1 updates the new page table information to the memory 4 and the memory address management unit 3.

For the scenario where the hardware needs to update the page table, compared with the related art, the software is first notified through the software-hardware interface how to allocate the page table, and then the software writes the page table information into the memory 4, and then notifies the memory address management unit 3 to re-acquire the page table information. This process in the related art involves synchronization between software and hardware, and accessing the memory, which consumes too much time, which in turn affects the performance of the processor. In the address update device of the embodiment of the present disclosure, by introducing the address update unit 1, the address update unit 1 as hardware directly updates the page table information in the memory 4 and the page table information of the memory address management unit 3, thereby reducing the software and hardware interaction during system operation (the address update unit 1 obtains the update request on how to allocate the page table initiated by the hardware via the page table update source 2), simplifying the page table update process and improving the system operation efficiency.

FIG2 shows a schematic diagram of an address updating device according to an embodiment of the present disclosure. As shown in FIG2 , the memory address management unit 3 will pass through the address updating unit 1 during the process of accessing the memory 4. For conventional memory accesses (e.g., access requests unrelated to address updates), the address updating unit 1 will pass them through to the memory 4, and the result returned by the memory 4 will also be passed through and returned to the memory address management unit 3. For the address update request initiated by the page table update source 2, the address update unit 1 will intercept it and return the page table information previously updated by the page table update source 2, so that the memory address management unit 3 will obtain the updated page table information. At the same time, the address update unit 1 will write the new page table information into the memory 4, so that there is also a new copy of the page table information in the memory 4, which is provided to the software or other memory address management units 3 for subsequent use.

The following takes FIG. 2 as an example to exemplarily illustrate the update process of the address update device in the embodiment of the present disclosure.

In a possible implementation, the address update unit 1 updates the page table information corresponding to the memory 4 and the memory address management unit 3 respectively according to the obtained update request, including: the address update unit 1 sends a first virtual address request carrying the virtual address to the memory address management unit 3 according to the virtual address carried in the update request; the memory address management unit 3 generates a read request for accessing the memory 4 according to the first virtual address request; the address update unit 1 intercepts the read request and sends the first physical address to the memory address management unit 3 to implement the update of the memory address management unit 3; the address update unit 1 obtains the second physical address from the page table update source 2, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address to the storage location indicated by the second physical address in the memory 4 to implement the update of the memory 4; the address update unit 1 feeds back the update result to the page table update source 2, and the update result is used to indicate that the address update unit 1 completes the update of the memory 4 and the memory address management unit 3.

By introducing the address update unit 1 in the address update device of the embodiment of the present invention, the address update unit 1 as hardware directly updates the page table information in the memory 4 and the page table information of the memory address management unit 3, thereby simplifying the page table information update process, and the update needs from various hardware modules obtained via the page table update source 2 no longer involve synchronization between software and hardware (for example, it does not involve notifying the software through the software-hardware interface how to allocate the page table, the software writing to the memory 4, and then notifying the memory address management unit 3 to re-acquire the page table). This reduces the software-hardware interaction during system operation and improves the address update efficiency.

Exemplarily, as shown in S1 in FIG. 2 , the page table update source 2 may send an update request to the address update unit 1, and the update request may include a virtual address and its corresponding first physical address. The update request may be a table creation request indicating that a new mapping relationship between a virtual address and a first physical address is established in the memory address management unit 3 and the memory 4, or may be a request to change the mapping relationship between a virtual address and a first physical address in the memory address management unit 3 and the memory 4, and the present disclosure does not limit this.

For example, assuming that the update request issued by the page table update source 2 carries the virtual address VA and the first physical address PA, if the virtual address VA is not recorded in the memory address management unit 3 and the memory 4, the update request is a table creation request, requesting to establish a mapping relationship between the virtual address VA and the physical address PA; if the virtual address VA has been recorded in the memory address management unit 3 and the memory 4, but the first physical address corresponding to the virtual address VA is not the first physical address PA, the update request is a change request, requesting to change the mapping relationship between the virtual address VA and other physical addresses to change the virtual address VA to correspond to the first physical address PA.

The address update unit 1 may receive an update request from the page table update source 2, the update request carrying the virtual address and the first physical address corresponding to the virtual address. The address update unit 1 may retain the first physical address, and as shown in S2 in FIG. 2 , generate a first virtual address request according to the received virtual address, and send the first virtual address request carrying the virtual address to the memory address management unit 3.

In a possible implementation, the address update unit 1 sends a first virtual address request carrying the virtual address to the memory address management unit 3 according to the virtual address carried in the update request, including: the address update unit 1 generates a first identifier according to the virtual address carried in the update request; the address update unit 1 sends a first virtual address request carrying the first identifier and the virtual address to the memory address management unit 3; by setting the first identifier, the memory address management unit 3 can quickly identify that the received first virtual address request is a request related to address update.

Exemplarily, since the first virtual address request is generated based on the update request from the page table update source 2, in order to indicate that the source of the virtual address carried in the first virtual address request is the virtual address in the update request, the address update unit 1 may generate a first identifier for the virtual address, which is used to mark that the source category of the virtual address is an update request for updating the page table information in the memory address management unit 3 and the memory 4. Then, in S2 in FIG. 2 , the address update unit 1 may send the first virtual address request carrying the first identifier and the virtual address to the memory address management unit 3.

In this way, when the page table update source 2 initiates an update request to the memory address management unit 3 cache, it will first inform the address update unit 1. The address update unit 1 will send a first virtual address request to the memory address management unit 3. This type of first virtual address request needs to have a first identifier to distinguish that the first virtual address request is not an ordinary virtual address request, but a first virtual address request related to the page table update.

Among them, each type of virtual address request received by the memory address management unit 3 may have an identification information to distinguish different types of virtual address requests. For example, a first virtual address request carrying a first identification (for example, the first identification is 1) is used to represent a request related to address update; a second virtual address request carrying a second identification (for example, the second identification is 0) is used to represent other types of requests not related to address update. Among them, the first identification and the second identification can be a combination of at least one or more of numbers, letters, and symbols, and the present disclosure does not limit this.

In one possible implementation, the memory address management unit 3 receives the first virtual address request, and queries the virtual address carried by the first virtual address request in the cache of the memory address management unit 3; if the virtual address is not found in the cache of the memory address management unit 3, space for storing page table information is allocated in the cache for the first virtual address request; or, if the virtual address is found in the cache of the memory address management unit 3, the associated space of the virtual address is cleared in the cache, and space for storing page table information is allocated in the cache for the first virtual address request.

The memory address management unit 3 allocates space in the cache for storing page table information, and can mark the cache space for storing page table update information, which can facilitate subsequent page table updates and reduce the probability of other data occupying the space.

In this way, the memory address management unit 3 can create new page table information for representing the mapping relationship between the virtual address and the first physical address, and can also change the mapping relationship between the existing virtual address and the first physical address in the cache, which can be applied to more scenarios.

As shown in S3 in FIG. 2 , the memory address management unit 3 may generate a read request for accessing the memory 4 according to the first virtual address request. For example, after receiving the first virtual address request, the memory address management unit 3 may query and judge in the on-chip cache. Because the virtual address is a newly created virtual address, the first physical address corresponding to the virtual address cannot be found in the on-chip cache of the memory address management unit 3. According to the process in the related art, the memory address management unit 3 will send a read request to the memory 4, read the page table information in the memory 4, and obtain the corresponding first physical address.

In an embodiment of the present disclosure, the memory address management unit 3 generates a read request for accessing the memory 4 based on the first virtual address request, and the read request includes the virtual address and the first identifier, and the first identifier is used to indicate that the source category of the virtual address is the update request, so that the subsequent address update unit 1 can intercept the read request based on the first identifier.

It should be understood that although the read request is used to be sent to the memory 4, the actual transmission path allows the address update unit 1 to intercept it. Whether the address update unit 1 intercepts the read request can be determined according to the actual application scenario, and the embodiments of the present disclosure do not limit this.

In a possible implementation, as shown in S4 in Figure 2, the address update unit 1 intercepts the read request in response to the read request containing the first identifier, and sends the first physical address to the memory address management unit 3 to implement the update of the memory address management unit 3.

For example, after receiving a read request from the memory address management unit 3, the address update unit 1 will determine that the read request is a request related to address update based on the first identifier carried in the read request. For such a read request related to address update, the address update unit 1 will intercept its access to the memory 4, and at the same time return the first physical address to the memory address management unit 3, that is, the first physical address carried by the request information in S1 in FIG2, to implement the update of the memory address management unit 3. In this way, when the memory address management unit 3 subsequently receives a second virtual address request carrying a second identifier and a virtual address, it can query the first physical address corresponding to the virtual address.

As shown in S5 in FIG. 2 , the address update unit 1 sends a physical address request to the page table update source 2. The physical address request requires the address update unit 1 to feedback a second physical address. The purpose of the second physical address is to tell the address update unit 1 that the mapping relationship information between the virtual address and the physical address previously established by the page table update source 2 needs to be stored in the location in the memory 4. As shown in S6 in FIG. 2 , after obtaining the second physical address, the address update unit 1 initiates a write operation to the memory 4, and writes the mapping relationship between the virtual address and the physical address established by the page table update source 2 to the location indicated by the second physical address in the memory 4.

After the writing is completed, as shown in S7 in FIG. 2 , the address update unit 1 has updated the new page table mapping relationship to the memory address unit 3 and the memory 4 , and can feed back the update result of the page table update completion to the page table update source 2 .

In an embodiment of the present disclosure, the address update unit 1 can update the page table information of the memory 4 and the memory address management unit 3 in an actively triggered manner based on the acquired update request; alternatively, the address update unit 1 can also passively wait for the page table update source 2 to send an update request, and the address update unit 1 can save the page table information that has not been updated. Each time the address update unit 1 receives a read request from the memory address management unit 3, it can compare it with the saved page table information that has not been updated, and if the virtual address carried in the read request satisfies the page table information that has not been updated, update the page table information of the memory 4 and the memory address management unit 3, and delete the content related to the virtual address from the page table information that has not been updated.

Exemplarily, the address update unit 1 updates the page table information corresponding to the memory 4 and the memory address management unit 3 respectively according to the obtained update request, including: the address update unit 1 waits for the page table update source 2 to send an update request, and generates the page table information to be updated according to the previously obtained unprocessed update request; the address update unit 1 intercepts the read request from the memory address management unit 3, and the read request is used to access the memory 4; the address update unit 1 compares the read request with the page table information to be updated to obtain a comparison result; the address update unit 1 responds to the comparison result indicating that the read request and the page table information to be updated have the same virtual address, updates the page table information to be updated (for example, deletes the updated virtual address from the page table information to be updated), and the page table information corresponding to the memory 4 and the memory address management unit 3 respectively; the address update unit 1 feeds back the update result to the page table update source 2, and the update result is used to indicate that the address update unit 1 completes the update of the memory 4 and the memory address management unit 3.

In this way, through the page table information to be updated, the address update unit 1 can process the previously obtained unprocessed update requests while waiting for the page table update source 2 to send an update request, which can ensure that the page table information is updated in a timely and continuous manner, and reduce the probability of update delays due to waiting for new update requests. In addition, by comparing the read request with the page table information to be updated, the address update unit 1 can accurately determine which read requests can be performed immediately, which can reduce unnecessary memory access waits, reduce system overhead, and improve system operation efficiency.

It should be understood that the address update unit 1 updates the page table information corresponding to the memory 4 and the memory address management unit 3 respectively according to the obtained update request. It can adopt the triggering method of actively triggering the update of the memory address management unit 3, or passively wait for the page table update source 2 to send an access request. The embodiments of the present disclosure do not limit this and can be set according to the application scenario to be implemented.

In one possible implementation, as shown in S8 in Figure 2, the page table update source 2 is connected to the memory address management unit 3, and the memory address management unit 3 receives a second virtual address request from the page table update source 2, and the second virtual address request carries a virtual address and a second identifier; in response to the memory address management unit 3 identifying that the source category of the virtual address is a category request other than the update request according to the second identifier, the memory address management unit 3 returns the first physical address corresponding to the virtual address to the page table update source 2.

Exemplarily, after receiving the update result fed back by the address update unit 1, the page table update source 2 may send a second virtual address request carrying a virtual address and a second identifier to the memory address management unit 3, and read the first physical address corresponding to the virtual address in the second virtual address request from the cache of the memory address management unit 3, where the second identifier is used to indicate that the source category of the virtual address is a category request other than the update request.

For example, after the page table update is completed, the latest page table information for indicating the mapping relationship between the virtual address and the first physical address is stored in the cache of the memory address management unit 3. For example, the page table information contains the virtual address A and the first physical address A corresponding to the virtual address. The memory address management unit 3 receives a second virtual address request carrying the virtual address A and the second identifier. When the memory address management unit 3 recognizes the second identifier in the second virtual address request, it can be known that the second virtual address request is a request that cannot be updated with the address. The virtual address A can be queried in the page table information in the cache, and it can be found that the virtual address A corresponds to the first physical address A. The first physical address A can be returned to the page table update source 2.

In this way, after receiving the notification of page table update completion, the page table update source 2 may send a virtual address request to the memory address management unit 3, or may notify other hardware modules or software that the mapping relationship is available.

In the above update process, if a multi-level page table is involved, in S3 as shown in Figure 2, the address update unit 1 will send multiple physical address requests to the page table update source 2. In a possible implementation, when the page table information includes a multi-level page table, the address update unit 1 obtains a second physical address from the page table update source 2, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory 4, including: the address update unit 1 sends a physical address request to the page table update source 2, and the physical address request includes a third identifier for indicating the number of page table levels; the address update unit 1 receives the second physical address fed back by the page table update source 2, and the second physical address corresponds to the third identifier; the address update unit 1 writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory 4 according to the second physical address corresponding to each third identifier.

Optionally, the physical address request sent by the address update unit 1 to the page table update source 2 may carry multiple third identifiers of different levels at a time. The page table update source 2 may receive multiple third identifiers at a time and feed back multiple second physical addresses corresponding to all levels to the address update unit 1 at a time based on the multiple third identifiers. The address update unit 1 may write the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory 4 based on the second physical address corresponding to each third identifier.

Optionally, the address update unit 1 sends physical address requests to the page table update source 2 multiple times, each physical address request may carry a third identifier indicating the page table level at one time, and the number of transmissions is determined by the level of the multi-level page table; the address update unit 1 receives the second physical address fed back by the page table update source 2 each time, the second physical address is a second physical address corresponding to the third identifier generated by the page table update source 2 according to the physical address request carrying the third identifier; the address update unit 1 writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory 4 according to the second physical address corresponding to each third identifier.

It should be understood that during the interaction between the address update unit 1 and the page table update source 2, each physical address request can carry one or more third identifiers at a time, and different third identifiers can correspond to different page table levels. The embodiments of the present disclosure do not limit the specific interaction method between the address update unit 1 and the page table update source 2, and can be set according to the actual application scenario.

By setting up a multi-level page table, you can optimize memory space, improve memory utilization, support a larger virtual address space, and increase address translation speed.

For example, if there are multiple levels of page tables in the memory address management unit 3, the address update unit 1 needs to send physical address requests to the page table update source 2 multiple times, because the establishment of each level of page table requires an available second physical address. At the same time, in order to let the address update unit 1 know which level of page table the currently established page table belongs to, the physical address request sent by the address update unit 1 each time includes a third identifier for indicating the number of page table levels, and the page table update source 2 can generate a second physical address corresponding to the third identifier based on the physical address request carrying the third identifier.

For example, the multi-level page table may include M levels (M>1), and the address update unit 1 may send M physical address requests to the page table update source 2.

The physical address request 1 sent by the address update unit 1 to the page table update source 2 for the first time may carry a third identifier 1 for indicating the first-level list. The page table update source 2 may generate a second physical address 1 corresponding to the third identifier 1 according to the physical address request 1 carrying the third identifier 1, which is used to indicate the location where the first-level page table information is written in the memory 4. The page table update source 2 may feedback the second physical address 1 corresponding to the third identifier 1 to the address update unit 1, and the address update unit 1 may write the first-level page table information to the second physical address 1 in the memory 4 according to the second physical address 1, thereby updating the first-level page table information in the memory 4.

Similarly, the physical address request 2 sent by the address update unit 1 to the page table update source 2 for the first time may carry a third identifier 2 for indicating the second-level list. The page table update source 2 may generate a second physical address 2 corresponding to the third identifier 2 based on the physical address request 2 carrying the third identifier 2, which is used to indicate the location where the second-level page table information is written in the memory 4. The page table update source 2 may feed back the second physical address 2 corresponding to the third identifier 2 to the address update unit 1, and the address update unit 1 may write the second-level page table information to the second physical address 2 in the memory 4 based on the second physical address 2, thereby updating the second-level page table information in the memory 4.

By analogy, the physical address request M sent by the address update unit 1 to the page table update source 2 for the Mth time may carry a third identifier M for indicating the Mth level list. The page table update source 2 may generate a second physical address M corresponding to the third identifier M according to the physical address request M carrying the third identifier M, which is used to indicate the location in the memory 4 where the Mth level page table information is written. The page table update source 2 may feed back the second physical address M corresponding to the third identifier M to the address update unit 1, and the address update unit 1 may write the Mth level page table information to the second physical address M in the memory 4 according to the second physical address M, thereby updating the Mth level page table information in the memory 4.

In one possible implementation, when the page table information includes a multi-level page table, the read request generated by the memory address management unit 3 for accessing the memory 4 may also include a third identifier for indicating the page table level information. When the address update unit 1 receives the read request carrying the first identifier and the third identifier, it will intercept the read request based on the first identifier and prevent it from being sent to the memory 4. At the same time, based on the third identifier representing the page table level information, it will return the page table content updated by the page table update source 2 (for example, the first physical address corresponding to the virtual address) to the on-chip cache of the memory address management unit 3.

Among them, according to the working process of the memory address management unit 3, assuming that the multi-level page table is a three-level page table, the memory address management unit 3 can send read requests carrying the third identifier to the address update unit 1 in sequence. For example, the third identifier carried by the first read request is used to represent the first-level page table PC, the third identifier carried by the second read request is used to represent the second-level page table PD, and the third identifier carried by the third read request is used to represent the third-level page table PD. The address update unit 1 will issue page table information for describing the mapping relationship between the virtual address and the first physical address according to the page table update source 2, and return the first physical address to the memory address management unit 3. At the same time, the address update unit 1 can record the second physical address of the memory 4 accessed by the memory address management unit 3 according to the physical address request, and initiate a write operation on the second physical address, and the write data can come from the first physical address of the page table update source 2. In this way, the page table information of the page table update source 2 will be synchronized to the memory 4 and the memory address management unit 3.

In one possible implementation, the address update unit 1 includes a second identifier in response to a read request sent by the memory address management unit 3, and the address update unit 1 transmits the read request from the memory address management unit 3 to the memory 4, and the address update unit 1 transmits the return result of the memory 4 in response to the read request to the memory address management unit 3, and the second identifier is used to indicate that the source category of the virtual address of the read request is a category request other than the update request.

In this way, an address update unit 1 is introduced between the memory address management unit 3 and the memory 4, and its function is to identify the read request sent by the memory address management unit 3 to the memory 4. If it is a read request containing the second identifier, it means it is an ordinary read request, and the source category of the virtual address of the read request is other category requests other than the update request. The address update unit 1 can release the read request carrying the second identifier, and pass the read request from the memory address management unit 3 to the memory 4, so that it can perform the memory 4 read operation normally; if the read request contains the first identifier, it means it is a read request related to the page table update, and the address update unit 1 can intercept it. The address update unit 1 not only improves the address update efficiency, but also does not affect the operations between the memory address management unit 3 and the memory 4 that are not related to the address update.

Among them, when the memory address management unit 3 sends a read request to the address update unit 1, the first identifier or the second identifier included can be used to distinguish whether the read request is a request related to the page table update. Further, the read request can also include a third identifier to indicate which level of page table update request the read request is. The present disclosure does not limit the specific forms of the first identifier to the third identifier.

In summary, the address updating device of the embodiment of the present disclosure may include: an address updating unit 1, a page table update source 2, a memory address management unit 3, and a memory 4, wherein the page table update source 2 may be connected to the memory address management unit 3 and the address updating unit 1, and the address updating unit 1 is connected between the memory address management unit 3 and the memory 4. The address updating unit 1 receives an update request from the page table update source 2, the update request including a virtual address and a first physical address corresponding to the virtual address; the address updating unit 1 generates a first identifier according to the virtual address carried by the update request; the address updating unit 1 sends a first virtual address request carrying the first identifier and the virtual address to the memory address management unit 3; the memory address management unit 3 generates a read request for accessing the memory 4 according to the first virtual address request, the read request including the virtual address and the first identifier, the first identifier being used to indicate that the source category of the virtual address is the update request, so that the address updating unit 1 can A read request carrying a first identifier is intercepted according to the first identifier, and the first physical address is sent to the memory address management unit 3 to update the memory address management unit 3; the address update unit 1 sends a physical address request to the page table update source 2 to obtain the second physical address from the page table update source 2, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory 4 to update the memory 4; then, the address update unit 1 feeds back the update result to the page table update source 2, and the update result is used to indicate that the address update unit 1 completes the update of the memory 4 and the memory address management unit 3.

After the update is completed, the page table update source 2 can send a second virtual address request carrying the virtual address and the second identifier to the memory address management unit 3, and read the first physical address corresponding to the virtual address in the second virtual address request from the cache of the memory address management unit 3. The second identifier is used to indicate that the source category of the virtual address is other category requests other than the update request.

In this way, for the scenario where the hardware needs to update the page table, compared with the related art, the software is first notified through the software-hardware interface how to allocate the page table, and then the software writes the page table information into the memory 4, and then notifies the memory address management unit 3 to re-acquire the page table information. This process in the related art involves synchronization between software and hardware, and accessing the memory, which consumes too much time, thereby affecting the performance of the processor. In the address update device of the embodiment of the present disclosure, by introducing the address update unit 1, the address update unit 1 as hardware directly updates the page table information in the memory 4 and the page table information of the memory address management unit 3, thereby reducing the software-hardware interaction during system operation (the address update unit 1 obtains the update request on how to allocate the page table initiated by the hardware via the page table update source 2), simplifying the page table update process, and improving the system operation efficiency.

It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

In addition, the present disclosure also provides an address update method, a processor, a chip, an electronic device, a computer-readable storage medium, and a program, all of which can be used to implement any address update scheme provided by the present disclosure. The corresponding technical scheme and description refer to the corresponding records in the method part and will not be repeated here.

Figure 3 shows a schematic diagram of the address updating method according to an embodiment of the present disclosure. As shown in Figure 3, the method is applied to the address updating device, and the address updating device includes: an address updating unit 1, a page table update source 2, a memory address management unit 3, and a memory 4; the method includes: in step S31, the address updating unit 1 receives an update request from the page table update source 2, and the update request includes a virtual address and a first physical address corresponding to the virtual address; in step S32, the address updating unit 1 updates the page table information corresponding to the memory 4 and the memory address management unit 3 respectively according to the obtained update request, and the page table information is used to describe the mapping relationship between the virtual address and the first physical address.

In a possible implementation, step S32 may include: the address update unit 1 sends a first virtual address request carrying the virtual address to the memory address management unit 3 according to the virtual address carried by the update request; the memory address management unit 3 generates a read request for accessing the memory 4 according to the first virtual address request; the address update unit 1 intercepts the read request and sends the first physical address to the memory address management unit 3; the address update unit 1 obtains a second physical address from the page table update source 2, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address to the storage location indicated by the second physical address in the memory 4.

In a possible implementation, step S32 may include: the address update unit 1 waits for the page table update source 2 to send an update request, and generates page table information to be updated based on the previously obtained and unprocessed update request; the address update unit 1 intercepts a read request from the memory address management unit 3, and the read request is used to access the memory 4; the address update unit 1 compares the read request with the page table information to be updated to obtain a comparison result; the address update unit 1 updates the page table information to be updated and the page table information corresponding to the memory 4 and the memory address management unit 3 in response to the comparison result indicating that the read request and the page table information to be updated have the same virtual address.

In a possible implementation, the method further includes: the address update unit 1 feeds back an update result to the page table update source 2 , wherein the update result is used to indicate that the address update unit 1 completes the update of the memory 4 and the memory address management unit 3 .

In a possible implementation, the address update unit 1 sends a first virtual address request carrying the virtual address to the memory address management unit 3 according to the virtual address carried in the update request, including: the address update unit 1 sends a first virtual address request carrying a first identifier and the virtual address to the memory address management unit 3; the read request includes the virtual address and the first identifier, and the first identifier is used to indicate that the source category of the virtual address is the update request; the address update unit 1 intercepts the read request, including: the address update unit 1 intercepts the read request in response to the read request containing the first identifier.

In one possible implementation, when the page table information includes a multi-level page table, the address update unit 1 obtains a second physical address from the page table update source 2, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory 4, including: the address update unit 1 sends a physical address request to the page table update source 2, and the physical address request includes a third identifier for indicating the number of page table levels; the address update unit 1 receives the second physical address fed back by the page table update source 2, and the second physical address corresponds to the third identifier; the address update unit 1 writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory 4 according to the second physical address corresponding to each third identifier.

In a possible implementation, the method also includes: the memory address management unit 3 receives a second virtual address request from the page table update source 2, the second virtual address request carries a virtual address and a second identifier; in response to the memory address management unit 3 identifying, based on the second identifier, that the source category of the virtual address is a request of a category other than the update request, the memory address management unit 3 returns the first physical address corresponding to the virtual address to the page table update source 2.

In a possible implementation, the method also includes: the address update unit 1 transmits the read request from the memory address management unit 3 to the memory 4 in response to the read request sent by the memory address management unit 3 including a second identifier; the address update unit 1 transmits the return result of the memory 4 in response to the read request to the memory address management unit 3, and the second identifier is used to indicate that the source category of the virtual address of the read request is a category request other than the update request.

In a possible implementation, the method also includes: the memory address management unit 3 receives the first virtual address request, and queries the virtual address carried by the first virtual address request in the cache of the memory address management unit 3; if the virtual address is not found in the cache of the memory address management unit 3, space for storing page table information is allocated in the cache to the first virtual address request; or, if the virtual address is found in the cache of the memory address management unit 3, the associated space of the virtual address is cleared in the cache, and space for storing page table information is allocated in the cache to the first virtual address request.

In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

The embodiment of the present disclosure further provides a processor, which includes the address updating device as described above.

The embodiment of the present disclosure also provides a chip, which includes the processor as described above.

The embodiment of the present disclosure also provides a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above method is implemented. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

The electronic device can be provided as a terminal, a server or other form of device, such as a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc.

FIG4 shows a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal device. Referring to FIG4 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, any of which may include an address updating device as described above, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each of which corresponds to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

The electronic device 1900 may further include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input/output interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Microsoft's server operating system (Windows Server ^™ ), Apple's graphical user interface-based operating system (Mac OS X ^™ ), a multi-user multi-process computer operating system (Unix ^™ ), a free and open source Unix-like operating system (Linux ^™ ), an open source Unix-like operating system (FreeBSD ^™ ), or the like.

In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

The present disclosure may be a system, a method and/or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing/processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and/or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and/or edge servers. The network adapter card or network interface in each computing/processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing/processing device.

The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

Various aspects of the present disclosure are described herein with reference to the flowcharts and/or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and/or block diagram and the combination of each box in the flowchart and/or block diagram can be implemented by computer-readable program instructions.

These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions/actions specified in one or more boxes in the flowchart and/or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and/or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions/actions specified in one or more boxes in the flowchart and/or block diagram.

Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions/actions specified in one or more boxes in the flowchart and/or block diagram.

The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and/or flow chart, and the combination of the square boxes in the block diagram and/or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (12)

1. An address updating device, characterized in that the address updating device comprises: an address updating unit, a page table updating source, a memory address management unit, and a memory; The address updating unit receives an update request from the page table update source, wherein the update request includes a virtual address and a first physical address corresponding to the virtual address; The address updating unit updates page table information corresponding to the memory and the memory address management unit respectively according to the acquired update request, wherein the page table information is used to describe a mapping relationship between the virtual address and the first physical address. 2. The address updating device according to claim 1, wherein the address updating unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the acquired update request, comprising: The address updating unit sends a first virtual address request carrying the virtual address to the memory address management unit according to the virtual address carried in the update request; The memory address management unit generates a read request for accessing the memory according to the first virtual address request; The address updating unit intercepts the read request and sends the first physical address to the memory address management unit; The address updating unit obtains a second physical address from the page table update source, and writes page table information describing a mapping relationship between the virtual address and the first physical address into a storage location indicated by the second physical address in the memory. 3. The address updating device according to claim 1, wherein the address updating unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the acquired update request, comprising: The address update unit waits for the page table update source to send an update request, and generates the page table information to be updated according to the previously obtained unprocessed update request; The address updating unit intercepts a read request from the memory address management unit, wherein the read request is used to access the memory; The address updating unit compares the read request with the page table information to be updated to obtain a comparison result; In response to the comparison result indicating that the read request and the page table information to be updated have the same virtual address, the address update unit updates the page table information to be updated and the page table information corresponding to the memory and the memory address management unit respectively. 4. The address updating device according to claim 2 or 3 is characterized in that the address updating unit is also used to feed back an update result to the page table update source, and the update result is used to indicate that the address updating unit completes the update of the memory and the memory address management unit. 5. The address updating device according to claim 2, wherein the address updating unit sends a first virtual address request carrying the virtual address to the memory address management unit according to the virtual address carried in the update request, comprising: The address updating unit sends a first virtual address request carrying a first identifier and the virtual address to the memory address management unit; The read request includes the virtual address and the first identifier, where the first identifier is used to indicate that the source category of the virtual address is the update request; The address updating unit intercepts the read request, comprising: In response to the read request containing the first identifier, the address update unit intercepts the read request. 6. The address updating device according to claim 2, characterized in that, when the page table information includes a multi-level page table, the address updating unit obtains a second physical address from the page table update source, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory, comprising: The address updating unit sends a physical address request to the page table update source, where the physical address request includes a third identifier for indicating a page table level; The address updating unit receives a second physical address fed back by the page table update source, where the second physical address corresponds to the third identifier; The address updating unit writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory according to the second physical address corresponding to each third identifier. 7. The address updating device according to claim 2 or 3, characterized in that the memory address management unit receives a second virtual address request from the page table update source, the second virtual address request carries a virtual address and a second identifier; In response to the memory address management unit identifying, according to the second identifier, that the source category of the virtual address is a request of another category other than the update request, the memory address management unit returns the first physical address corresponding to the virtual address to the page table update source. 8. The address updating device according to claim 2 or 3, characterized in that the address updating unit transmits the read request from the memory address management unit to the memory in response to the read request sent by the memory address management unit containing the second identifier; The address update unit transparently transmits the return result of the memory in response to the read request to the memory address management unit, and the second identifier is used to indicate that the source category of the virtual address of the read request is other category requests other than the update request. 9. The address updating device according to claim 2, wherein the memory address management unit receives the first virtual address request and searches the cache of the memory address management unit for the virtual address carried in the first virtual address request; In the case where the virtual address is not found in the cache of the memory address management unit, allocating space for storing page table information in the cache for the first virtual address request; or When the virtual address is found in the cache of the memory address management unit, the associated space of the virtual address is cleared in the cache, and space for storing page table information is allocated in the cache for the first virtual address request. 10. An address updating method, characterized in that the method is applied to the address updating device, the address updating device comprising: an address updating unit, a page table updating source, a memory address management unit, and a memory; The method comprises: The address updating unit receives an update request from the page table update source, wherein the update request includes a virtual address and a first physical address corresponding to the virtual address; The address updating unit updates page table information corresponding to the memory and the memory address management unit respectively according to the acquired update request, wherein the page table information is used to describe a mapping relationship between the virtual address and the first physical address. 11. A processor, characterized in that the processor comprises the address updating device according to claims 1 to 9. 12. A chip, characterized in that the chip comprises the processor according to claim 11.