CN118784196B

CN118784196B - Window detection method, system, electronic device and storage medium for differential link

Info

Publication number: CN118784196B
Application number: CN202411276712.6A
Authority: CN
Inventors: 曹桂平; 杨晨飞; 董宁
Original assignee: Hefei Eko Photoelectric Technology Co ltd
Current assignee: Hefei Eko Photoelectric Technology Co ltd
Priority date: 2024-09-12
Filing date: 2024-09-12
Publication date: 2024-12-10
Anticipated expiration: 2044-09-12
Also published as: CN118784196A

Abstract

The application provides a window detection method, a system, electronic equipment and a storage medium of a differential link, and relates to the field of data processing. The method comprises the steps of splitting differential signals in a differential link into positive polarity signals and negative polarity signals, collecting signal data of the positive polarity signals and the negative polarity signals under different delay time to be used as a first data sequence and a second data sequence respectively, performing inverse processing on the signal data in the second data sequence to obtain a third data sequence, and selecting delay time intervals with the same data in the first data sequence and the third data sequence as latch windows of the differential signals. Based on the processing, the application screens the stable interval of the positive polarity signal and the negative polarity signal by comparing the first data sequence with the third data sequence, thereby realizing the rapid detection of the position and the size of the latch window. Moreover, the application belongs to a delay detection method of a data channel without training a data set, and has great universality.

Description

Window detection method, system, electronic device and storage medium for differential link

Technical Field

The invention belongs to the field of data processing, and particularly relates to a window detection method, a system, electronic equipment and a storage medium of a differential link.

Background

Differential links are common in various systems for data acquisition, transmission, etc. For example, in the field of machine vision, image sensors utilize differential links for image data acquisition, long-distance transmission, and the like. And, as the resolution and output frame rate of the image sensor continue to increase, the number of data channels in the differential link increases. The data interface, such as an image sensor, is typically composed of a single clock and a number of lanes of data (e.g., 144 lanes of data).

In the differential link, due to the influences of wiring delay, chip package parasitic parameters and the like, various delay differences exist between clock signals and differential signals as well as between different differential signals, and finally, the traditional fixed data acquisition mode with 90-degree delay to the clock signals is gradually disabled. Particularly, under the condition of a large number of data channels, an effective latch window formed between different differential signals is reduced, and the data transmission efficiency of the differential link is affected. The latch window represents a time window in which logic levels can be stably acquired based on an effective clock edge of a clock signal.

Therefore, a window detection method is needed to detect the latch window of each differential signal in the differential link, so as to facilitate the subsequent alignment of the latch windows of the differential signals in different data channels.

Disclosure of Invention

The application provides a window detection method, a system, electronic equipment and a storage medium for a differential link, which are used for detecting a latch window of a differential signal in the differential link.

In order to achieve the above purpose, the present application proposes the following technical solutions:

In a first aspect of the present application, there is provided a window detection method for a differential link, including:

Splitting differential signals in the differential link into positive polarity signals and negative polarity signals;

Collecting signal data of the positive polarity signal and the negative polarity signal under different delay time to respectively serve as a first data sequence and a second data sequence;

Performing inversion processing on the signal data in the second data sequence to obtain a third data sequence

And selecting the delay time interval with the same data in the first data sequence and the third data sequence as a latch window of the differential signal.

Optionally, the signal receiving end of the differential link is set as a fully differential circuit.

Optionally, the differential link includes a clock signal for collecting the signal data.

Optionally, the clock signal is used to collect the signal data after each of a plurality of consecutive delays.

Optionally, the delay is a fixed step size.

Optionally, the method further comprises:

acquiring a latch window of each data channel in the differential link, wherein each data channel is used for transmitting a differential signal;

determining the delay step number of each data channel based on the time value of the center of the latch window;

And performing delay compensation on each data channel based on the delay step number and the delay chain of each data channel so as to make the moment value of the center of the latch window in each data channel identical.

Optionally, the method further comprises:

Selecting a positive polarity signal or a negative polarity signal as a reference signal, and using the remaining signal as a working signal for transmitting data in the differential link;

Delaying or advancing the reference signal for a preset time period to serve as a signal to be compared;

Judging whether signal data of the signal to be compared and signal data of the working signal are the same or not, if so, keeping time positions of the positive polarity signal and the negative polarity signal unchanged, and if not, advancing or delaying the positive polarity signal and the negative polarity signal for the preset time period;

the signal data of the signal to be compared and the signal data opposite value of the working signal are extracted from the same acquisition time, and the acquisition time is determined based on the clock signal in the differential link.

Optionally, the preset time period is within half of the latch window time length.

In a second aspect of the present application, there is provided a window detection system of a differential link, comprising:

the signal splitting module is used for splitting differential signals in the differential link into positive polarity signals and negative polarity signals;

the signal acquisition module is used for acquiring signal data of the positive polarity signal and the negative polarity signal under different delay time and respectively used as a first data sequence and a second data sequence;

A data inverting module for inverting the signal data in the second data sequence to obtain a third data sequence

And the interval selection module is used for selecting the delay time interval with the same data in the first data sequence and the third data sequence as the latch window of the differential signal.

In a third aspect of the present application, there is provided an electronic device comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

a memory for storing a computer program;

And the processor is used for realizing the steps of any window detection method when executing the program stored in the memory.

In a fourth aspect of the present application, there is provided a computer readable storage medium having a computer program stored therein, the computer program when executed by a processor implementing the steps of any window detection method.

The beneficial effects of the application are as follows:

The application provides a window detection method of a differential link, which comprises the steps of splitting differential signals in the differential link into positive polarity signals and negative polarity signals, collecting signal data of the positive polarity signals and the negative polarity signals under different delay time to be respectively used as a first data sequence and a second data sequence, carrying out inverse processing on the signal data in the second data sequence to obtain a third data sequence, and selecting delay time intervals with the same data in the first data sequence and the third data sequence as latch windows of the differential signals.

Based on the processing, the stable intervals of the positive polarity signal and the negative polarity signal are screened out by comparing the first data sequence with the third data sequence, so that the intervals with the same data are used as latch windows, and the quick detection of the position and the size of the latch windows is effectively realized. In addition, the technical scheme provided by the application can directly detect the position and the size of the latch window by processing the differential signals continuously working in the differential link, belongs to a delay detection method of a data channel without training a data set, has extremely high universality and can effectively improve the stability of data acquisition and transmission in the high-speed differential link.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 is a schematic flow chart of an improved effective latch window according to the present application;

FIG. 2 is a flow chart of a window detection method provided by the application;

FIG. 3 is a schematic diagram of a window detection process according to the present application;

FIG. 4 is a schematic flow chart of signal acquisition provided by the application;

FIG. 5 is a schematic diagram of a latch window movement provided by the present application;

FIG. 6 is a schematic diagram of a latch window calibration flow provided by the present application;

FIG. 7 is a schematic flow chart of another latch window calibration provided by the present application;

FIG. 8 is a schematic diagram of a differential link workflow provided by the present application;

FIG. 9 is a block diagram of a window detection system provided by the present application;

fig. 10 is a block diagram of an electronic device provided by the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application.

Transmitting a digital signal can be understood as transmitting a series of digital sequences consisting of 0's or 1's. When communicating with different devices, the timing information is associated with the transmitted bits, so that the clock signal is required to provide the timing signals to various portions of the digital circuitry, so that each signal data transmission process can be triggered at a precise point in time. The clock signal is used to synchronize the digital signal transmitter and the signal receiver during data transmission. Wherein the determined edges of the clock are also referred to as valid clock edges. The digital signal transmitter triggers a new data transmission at each active clock edge, while the signal receiver performs data sampling at each active clock edge.

In order to improve the anti-interference capability of signal transmission and inhibit electromagnetic interference, the prior art generally adopts a differential signal form to transmit a required digital signal. In the actual transmission process, a certain time is required for the voltage change process on two lines for transmitting the differential signal, so that a voltage change area exists at two ends of the differential signal for a period of time and a voltage constant area exists in the middle of the differential signal. Accordingly, at the effective clock edge time of the clock signal, the signal receiving end can stably collect the logic '1' and the logic '0' states from the voltage constant region. Wherein, the voltage constant area in the differential signal is defined as a latch window of the differential signal in the application. Or the latch window may be understood as a stable window formed by the setup time and the hold time near the active clock edge of the signal receiving terminal when the signal receiving terminal samples the data on the digital line, so that the signal receiving terminal can reliably collect the data.

Taking the field of machine vision as an example, the vast majority of occasions such as image sensor data acquisition, long-distance transmission of image data and the like adopt differential links, the level standard is changed from LVDS to sub-LVDS to SLVS and the like, and the interface type is changed from the common CameraLink interface of an industrial camera, the common MIPI interface of a mobile phone, the common PCIE interface of a computer and the like. Basically, all data acquisition systems are composed of a front-end image sensor and a back-end processor, and considering implementation complexity and cost, at present, most of image sensor data output adopts an LVDS differential interface, adopts a non-protocol (pure data mode) or MIPI protocol to output data, and in order to be compatible with drive-end design (generally an FPGA or other embedded processors), the interface rate is generally below 1.6Gbps, and adopts a double-edge (DDR) data latch mode.

With increasing image sensor resolution and output frame rates, image sensor data interfaces typically consist of a single clock and a large number of data channels (e.g., 144 data channels). Due to the effects of routing delay, chip package parasitic parameters and the like, various delay differences exist between clock signals and data (namely differential signals in the application) and between data and data channels, and finally, the data acquisition mode of delaying the clock signals by 90 degrees, which is originally fixed, gradually fails. Especially when the number of data channels is large, it is common to cause the effective latch window of the differential signal to become smaller. In the technical scheme provided by the application, the data channel represents a channel for transmitting differential signals, and the effective latch window represents a common interval of different latch windows in a plurality of data channels.

Referring to fig. 1, fig. 1 is a schematic flow chart for improving an effective latch window according to the present application. As shown in fig. 1, before the differential signals in the data channels are delay aligned, each data channel has a delay time relative to a reference time, and the difference of the delay times is a result of the combination of factors such as output delay, routing delay, device packaging, parasitic parameters in the device and the like of a data transmitting end (for example, an image sensor), so that an effective latch window is small under a unified latch signal, and error codes are extremely easy to be caused. By calculating the delay of each data channel, such as t1-t4 in fig. 1, and then performing delay compensation through a delay chain, each aligned data channel can be obtained, and at this time, the effective latch window in the differential link can be greatly improved, so that the data integrity is ensured, and the occurrence of error code phenomenon is avoided.

In order to solve the problem that the effective latch window in the existing differential link is smaller, the position and the size of the latch window of each of different data channels need to be detected first, based on this, the application provides a window detection method of the differential link, as shown in fig. 2, the window detection method comprises the following steps:

S201, splitting differential signals in a differential link into positive-polarity signals and negative-polarity signals.

S202, collecting signal data of the positive polarity signal and the negative polarity signal under different delay time to respectively serve as a first data sequence and a second data sequence.

S203, performing inversion processing on the signal data in the second data sequence to obtain a third data sequence.

S204, selecting the delay time interval with the same data in the first data sequence and the third data sequence as a latch window of the differential signal.

Based on the processing, the stable intervals of the positive polarity signal and the negative polarity signal are screened out by comparing the first data sequence with the third data sequence, so that the intervals with the same data are used as latch windows, and the quick detection of the position and the size of the latch windows is effectively realized. In addition, the technical scheme provided by the application can directly detect the position and the size of the latch window by processing the differential signals continuously working in the differential link, belongs to a delay detection method of a data channel without training a data set, has extremely high universality and can effectively improve the stability of data acquisition and transmission in the differential link.

For step S201, a fully differential circuit is provided at the signal receiving end of the differential link, and then the differential signal in the differential link is split into a positive polarity signal and a negative polarity signal based on the fully differential circuit. For the characteristic that the differential signal has positive and negative signals, the signal receiving end adopts a circuit (for example, a fully differential amplifier) with differential input and differential output to still convert the differential signal into differential processing after receiving the differential signal. Each data channel is virtually divided into two sub-data channels at the signal receiving end according to differential positive and negative signals, including a positive sub-data channel and a negative sub-data channel. Wherein the positive sub-data path is used to transmit a positive side signal (i.e., positive polarity signal) and the negative sub-data path is used to transmit a negative side signal (i.e., negative polarity signal). The scheme is effectively different from the traditional mode that the signal receiving end adopts differential input, and the single-ended output amplifier converts a differential signal into a single-ended post-processing process.

Due to the effects of asymmetry in circuit parameters of the signal transmitting end, slight differences in wiring delays (differential signal wiring generally requires equal lengths, but delay differences are introduced), load differences of the signal receiving end, and the like, the two sub-data channels have slight delay differences. But this delay difference is typically within 100ps, which is substantially negligible for bit widths on the order of 10 ns. The adverse effect of this scheme can be equivalently understood as essentially losing only a portion of the latch window.

In some embodiments, the clock signal is included in the differential link. Accordingly, step S202 may include the steps of:

s20201, delaying the clock signal in the differential link a plurality of times based on the fixed delay step.

S20202, after each delay, collecting signal data of the positive polarity signal and the negative polarity signal based on the delayed clock signal.

In actual operation, the clock signal may be delayed by the delay chain to scan the data channel to acquire a plurality of signal data of the positive polarity signal and the negative polarity signal. That is, each time the clock signal is shifted by a fixed value step, the positive polarity signal and the negative polarity signal are data-collected. Specifically, step S202 includes the steps of:

s20203 delays the clock signal in the differential link a plurality of times in succession using the delay chain. Wherein the step sizes between different delays are the same.

S20204, after each delay, collecting signal data of the positive polarity signal and the negative polarity signal based on the clock signal.

For step S20203, the delay chain delays the clock signal by one step length each time during the scanning of the data channel, and performs data acquisition on the positive polarity signal and the negative polarity signal. The signal data of the positive polarity signal acquired after the first delay is set to be D1, and the signal data of the negative polarity signal is set to be B1. If the clock signal is delayed and shifted n times, the data sequences D1-Dn of the positive polarity signal data and the data sequences B1-Bn of the negative polarity signal data can be obtained.

Based on the above processing, the data sequences D1 to Dn of the positive polarity signal data are taken as the first data sequences, and the data sequences B1 to Bn of the negative polarity signal data are taken as the second data sequences. And then, carrying out inverting operation on each sampled data in the second data sequence to obtain inverted data sequences C1-Cn as a third data sequence.

Then, D1-Dn and C1-Cn are compared, and when the acquisition interval is in an unstable interval (such as the interval where D1 or C1 is in FIG. 3). At this time, D1 is not always equal to C1 (i.e., an unstable section in the differential signal) because the differential signal has not stabilized while superimposing a slight delay difference of the positive and negative terminal signals and a sampling clock wiring delay difference. At a certain clock step, by detecting the data change condition in a period of time, the comparison result of Dx |=cx can be obtained for the unstable region. For the stable interval, a comparison of dx=cx is always obtained. Wherein Dx represents signal data of the positive polarity signal after the xth delay, cx represents signal data of the negative polarity signal after the xth delay. Thus, by comparing the data sequence results, the effective latch window for the data channel can be obtained, as shown in FIG. 3 for the Dj-Dk or Cj-Ck intervals.

In actual operation, the signal data (e.g., D1, C1, etc.) sampled after each delay may be a binary value of 1 bit or more. Wherein the total number of bits in the signal data is related to the number of samples after each delay. Specifically, after each time the clock signal is delayed, based on the effective clock edge of the clock signal, logic level collection may be performed on the positive polarity signal and the negative polarity signal for one or more times, so as to obtain a binary value of 1 bit or more bits as signal data. For example, if the sampling number is 5, the corresponding sampling data D1 is "01110", B1 is "10001", and C1, which is the inverse of B1, is "01110". At this time, D1 is identical to the data in C1, indicating that D1 matches C1, i.e., d1=c1.

In addition, the window detection method provided by the application does not require that the complete data sequences (for example, D1-Dn and C1-Cn) are stored and then the data comparison is performed in actual operation. Instead, data comparison can be performed simultaneously in the sampling process of the signal data, so as to improve the efficiency of latch window detection.

The application divides the original data channel into positive and negative sub-channels (namely, divides the differential signal into positive polarity signal and negative polarity signal) by adopting the full differential circuit at the signal receiving end, and simultaneously scans and collects the data of the two sub-channels, and then the latch window position and size in the data channel (namely, the differential signal in the application) can be obtained by comparing the collected data of the two sub-channels. It is noted that the above process removes the need for the data channel to have to output a training data set, and is applicable to all differential link based data signal acquisitions.

It is noted that the collection of the signal data of the positive polarity signal and the negative polarity signal is completed in different signal periods under different delay times. Wherein signal data is typically collected only once per signal period. In the technical scheme provided by the application, the positions of the latch windows of the differential signals are basically fixed in different signal periods. The window detection method provided by the application can be understood that the data sequences of the positive polarity signal and the negative polarity signal under different delay time are respectively acquired in a plurality of signal periods, the data in the two data sequences are compared (the data sequences of the negative polarity signal are subjected to inverse operation before comparison), and the delay time interval corresponding to the same comparison result is used as the latch window of the differential signal.

In addition, the application provides that the cost of the fully differential (i.e. differential input differential output) receiving circuit is basically negligible compared with the cost of the differential-to-single-ended (i.e. differential input single-ended output) circuit, and the traditional FPGA mostly supports the fully differential input circuit, so that the window detection method of the differential link can be realized based on the FPGA.

In some embodiments, the latch window may also be detected by a link training data set and delay chain scanning implementation. That is, a signal output terminal (e.g., an image sensor) is set to output data of a fixed pattern as a training data set (TRAINING PATTERN), and a signal receiving terminal (typically FPGA) calculates delays of the respective data channels by detecting the training data.

The amount of delay per channel can be calculated by a delay chain scan in conjunction with the image sensor outputting a fixed training data set, such as t1-t4 in fig. 1. Specifically, the clock channel is delayed by the delay chain (at this time, the data channel is not delayed, or another operation mode is that the clock channel is not delayed, the data channel moves one step length each time, the principle is the same), the data channel is scanned, one step length is moved each time, data acquisition is performed, the data acquired by the first acquisition is made to be D1, and after the data are moved n times, the data sequence from D1 to Dn can be obtained. Because the data channel outputs the training data set in the fixed mode at this time, only the data sequence conforming to the training data set needs to be found out from D1-Dn, and the corresponding interval (e.g., interval shown by Dj-Dk in fig. 4) is the latch window position and size of the data channel. The effective latch window position for the data channel is shown in fig. 4 as j, the window size is k-j, and the unit is the number of delay chain steps. According to the method, window positions and sizes of all data channels can be obtained, and preparation can be made for aligning all data channels through delay compensation in the next step.

Based on the above processing, the window positions and sizes of all data channels can be obtained, thereby increasing the size of the effective latch window. However, the training data set is dependent on the data channel, and if the signal transmitting end (such as the image sensor or the data transmitting module) does not support the output mode of the training data set, the method will be directly disabled.

After completing the detection of the latch window in the differential link, each data channel may be delay-supplemented by a delay chain to maximize the data latch window, comprising the steps of:

and a step a, obtaining a latch window of each data channel in the differential link. Each data channel is used for transmitting a differential signal.

And b, determining the delay step value of each data channel based on the time value of the center of the latch window.

And c, performing delay compensation on each data channel in the differential link based on the delay step value and the delay chain of each data channel so as to make the moment value of the center of the latch window in each data channel identical.

The steps a-c can be completed through a delay chain integrated in the FPGA. Specifically, after the differential signals are scanned by the delay chain delay clock signals, delay step intervals corresponding to latch window intervals of different differential signals are obtained. For example, the delay step number included in a certain delay step number section is "3, 4, 5, 6, and 7", respectively. The latch window of the differential signal can be obtained by using the delay step interval, and the delay step number 5 is used as the center point of the latch window. Then, the differential signal is delay-compensated by using a delay chain, so that the sampling point of the differential signal is set at the center of the latch window, that is, the effective clock edge of the clock signal corresponds to the center point of the latch window.

For a differential link after delay alignment is completed or for a differential link which does not need to be subjected to delay alignment, delay alignment is often performed only once when a signal output end (such as an image sensor) is powered on and initialized, and is not adjusted in subsequent normal operation, when the working environments of the image sensor and a signal receiving end (FPGA) are greatly changed, such as temperature change, certain working voltages are possibly changed when the link speed is high, an original latch window is shifted, so that an original set sampling point is not valid any more, and error code phenomenon is caused.

Specifically, the latch window detection and calibration process is typically completed at power-up initialization of the sensor, and once the sensor is in normal operation, the image sensor continues to output a data stream, typically without re-performing window detection and calibration during operation. As shown in fig. 5, if the working temperature of the image sensor changes greatly (for example, the working temperature rises from about 25 degrees to 60-70 degrees under full-speed working during cold start), and when factors such as poor ripple control of the power supply of the data interface at the end of the image sensor are superimposed, the offset relationship detected between the clock signal and the data channel may change greatly, compared with the power-on initialization, if the interval of the original latch window is smaller, the original sampling point position is likely to fail, and further data acquisition errors are caused, and at this time, many pixels similar to noise points will appear in the image data.

Aiming at the situation, the application also provides a calibration method of the differential link, which is used for solving the problem of latch window transfer caused by the change of the working environment so as to avoid the problem of error codes possibly caused by latch window transfer. After completing splitting the differential signals in the differential link into a positive polarity signal and a negative polarity signal, the method comprises the steps of:

S301, selecting a positive polarity signal or a negative polarity signal as a reference signal, and using the remaining signal as a working signal for transmitting data in a differential link.

S302, judging whether signal data of the working signal and signal opposite values of the first signal to be compared are the same, if so, keeping original time positions of the positive polarity signal and the negative polarity signal unchanged, and if not, reversely moving the positive polarity signal and the negative polarity signal to a preset time period relative to the original time positions.

The first signal to be compared is a signal after a preset time period of the forward moving reference signal. Forward movement is denoted as time delay or time advance, and reverse movement denotes reverse time operation relative to forward movement. Specifically, if the forward movement is time-delayed, the reverse movement is time-advanced.

The signal data of the working signal and the signal opposite value of the first signal to be compared are acquired at the same moment. The signal opposite value of the signal to be compared represents the signal data of the acquired signal to be compared after the signal data are subjected to inverse processing.

Based on the processing, the application transmits the data in the differential link through the working signal, is used for guaranteeing the normal operation of the differential link, and simultaneously, can pre-judge the problem of sampling point failure possibly occurring in the differential link by adjusting the reference signal and comparing the reference signal with the working signal, and can calibrate the latch window in advance through the operation of reversely moving the positive polarity signal and the negative polarity signal, thereby avoiding the problem of error codes possibly caused by the transfer of the latch window.

For step S302, the working signal is used to transmit valid data of the differential signal in the differential link. Specifically, the working signal is used as a carrier for data transmission and is used for signal acquisition, and the acquired signal data is always in a latch window of the working signal, so that the normal operation of the data transmission is ensured.

In one implementation, the differential link includes a clock signal for collecting the signal data. The clock signal based effective clock edge completes the collection work of signal data, and ensures that the signal data collected in different signals are at the same collection time.

In some embodiments, the present application also provides a dynamic calibration method of a latch link, as shown in fig. 7, after step S301, the dynamic calibration method includes the steps of:

S401, executing a data judging step, if not, turning to S402, and if so, turning to S403. The data judging step comprises judging whether signal data of the working signal and a signal opposite value of the first signal to be compared are the same or not.

S402, reversely moving the positive polarity signal and the negative polarity signal to a preset time period relative to the original time position, and turning to S401.

S403, judging whether the signal data of the working signal and the signal opposite value of the second comparison signal are the same, if yes, turning to S404, otherwise turning to S405. The second comparison signal is obtained after the reference signal is reversely moved for a preset time period.

S404, the original time positions of the positive polarity signal and the negative polarity signal are kept unchanged, and the process goes to S401.

S405, the positive polarity signal and the negative polarity signal are moved forward to a preset time period corresponding to the original time position, and the process goes to S401.

Based on the processing, the dynamic calibration of the differential link is realized, so that the accuracy of data acquisition in the whole data transmission process is ensured.

After moving the positive polarity signal and the negative polarity signal forward or backward to a preset time period relative to the original time position, the moved signals need to be checked to confirm whether the calibration is completed. That is, in the foregoing steps S402 and S405, the above-described verification process is performed before proceeding to step S401.

Specifically, in step S402 or S405, the following are included:

and step A, judging whether the shifted positive polarity signal and the shifted negative polarity signal are matched. If yes, the calibration is completed once, and the step S401 is carried out, and if not, the step B is carried out. Wherein the movement includes a forward movement and a reverse movement. The judgment mode of the matching is to judge whether the signal data of the shifted positive polarity signal and the signal opposite value of the shifted negative polarity signal are the same.

Step B, cancel the operation of moving the positive polarity signal and the negative polarity signal to the preset time period with respect to the original time position, and reduce the length of the preset time period, and go to S401.

Based on the above processing, after canceling the operation of shifting the positive polarity signal and the negative polarity signal to the preset time period with respect to the original time position, the time length of the preset time period is reduced, and the differential signal is dynamically calibrated again. It is noted that by reducing the length of the preset time period, the time length of the reference time delay or the reference time advance can be reduced, so that not only the detection precision of the latch window movement is improved, but also the dynamic calibration under the condition that the latch window interval is reduced can be realized.

In actual operation, after step S301, the calibration method further includes the following steps:

s303, comparing whether the signal data of the signal to be compared and the signal opposite value of the working signal are the same or not, and if not, turning to step S304. The left shift signal to be compared represents a signal obtained by advancing a reference signal by a preset time period.

S304, delaying the positive polarity signal and the negative polarity signal for a preset period of time.

Based on the above processing, under the condition of advancing the reference signal for a preset period of time, by comparing the left shift comparison signal with the working signal, if the comparison result is the same, the original latch window is known to have a certain margin in the time advance direction, and then the differential signal does not need to be delayed or advanced. If the comparison results are different, the margin of the latch window in the time advance direction is lower, so that the positive polarity signal and the negative polarity signal are delayed for a preset time period relative to the original positions later, and the margin of the latch window in the time advance direction is improved. As shown in fig. 5, based on the above-described processing, the problem of the latch window moving leftward (i.e., the time advance direction) margin being low is solved.

In one implementation, after step S304, the dynamic calibration method further includes the steps of:

s305, if yes, comparing whether the signal data of the signal to be compared and the signal opposite value of the working signal are the same, and if not, turning to S306. If yes, go to S303. The right shift comparison signal is represented as a signal obtained by delaying the reference signal for a preset time period.

S306, advancing the positive polarity signal and the negative polarity signal by a preset period of time.

Based on the above processing, if the comparison result of the right shift comparison signal and the working signal is different, it can be known that the margin of the latch window in the time delay direction is lower, so that the positive polarity signal and the negative polarity signal are both advanced for a preset time period relative to the original position subsequently, so as to improve the margin of the latch window in the time delay direction, thereby solving the problem that the margin of the latch window in the right shift direction (i.e., the time delay direction) is lower.

Further, the length of the preset time period may be determined by a latch window section of the differential signal. Specifically, the preset time period is within half of the latch window time length. That is, the preset time period ranges from 0< T < S/2. Wherein T represents a preset time period, and S represents a time length of a latch section of the differential signal.

After the detection and calibration of the power-on initialization window are completed, sampling points of positive polarity signals and negative polarity signals obtained by splitting each differential signal are all at the optimal positions (namely, the centers of effective windows), namely, the corresponding relations of clock signals, data positive sub-channels and data negative sub-channels in the original positions are shown in fig. 6. Thus, the length of the preset time period is set to not more than one half of the latch window size. Typically, the window is cut into N aliquots according to the effective window size, with each aliquot representing a delay time of TN. As shown in fig. 6, the preset period TN is set to one quarter of the latch window size by periodically phase shifting the negative polarity signal in the data negative sub-channel by 90 degrees with respect to the effective window, i.e., setting N to 4.

In the actual working process, as shown in fig. 6, after the power-on calibration is completed, the positive polarity signal in the data positive sub-channel is set as the working signal, and the following operations are performed on the negative polarity signal in the data negative sub-channel:

Step one, shift TN left with respect to the original position (i.e., forward shift in the present application) as a first signal to be compared. Detecting the data matching condition of the positive sub-channel and the negative sub-channel of the data in t0 time, if the data are completely matched, indicating that the margin of a latch window on the right side of the sampling point is enough, and jumping to the second step, otherwise jumping to the third step.

Detecting that the data of the positive sub-channel and the negative sub-channel are matched in the time t0 indicates that the data of the positive signal and the negative signal are completely sampled in the time range with the time period length of t0, and comparing whether the sampled signal data are the same or not. The data sampling process is also that the positive polarity signal and the negative polarity signal are acquired through the effective clock edge of the clock signal.

And step two, right shifting TN relative to the original position (namely, reverse shifting in the application) is used as a second comparison signal. And (3) testing the data matching condition of the positive sub-channel and the negative sub-channel of the data in the t0 time, if the data are completely matched, indicating that the margin of the latch window at the left side of the sampling point is enough, and jumping to the first step, otherwise jumping to the fourth step.

Step three, entering the step, namely that the left latch window allowance of the right side of the current sampling point is not enough under the influence of environmental change, the whole data channel needs to be moved to the right side by TN, note that the positive and negative data sub-channels need to be moved to the right side simultaneously at the same time, and the step five is skipped.

Step four, entering the step, namely that the left latch window margin of the current sampling point is not enough under the influence of environmental change, the whole data channel needs to be moved to the left side by TN, note that the positive and negative data sub-channels need to be simultaneously moved to the left side by TN, and the step five is skipped.

Step five, entering the step indicates that the position of the original latch window is just adjusted, the validity of the adjusted position needs to be detected, the data matching condition of the positive and negative sub-channels of the data is detected in the time t0, if the data is completely matched, the position of the adjusted window is free, if the data is not matched, the movement of the latch windows in the step three and the step four is canceled, and the step one is restarted.

In the fifth step, the window detection is performed again by canceling the previous adjustment operation in the current strategy under the condition that the data mismatch (error code) still exists after the dynamic adjustment calibration is performed on the latch window. Before window detection is performed again, the time length of TN can be reduced, so that the time length of reference time delay or reference time advance can be reduced, the detection precision of latch window movement is improved, and dynamic calibration under the condition that the latch window interval is reduced can be realized.

In addition, the phenomenon that the data of the adjustment window is not matched in an extreme case exists, namely the original latch window is smaller and is further compressed until no effective latch window exists after being influenced by environmental factors such as temperature and the like, otherwise, the sampling precision of sampling points can be improved after the latch window is dynamically adjusted and calibrated.

It should be noted that, in the above-mentioned moving process (i.e. delay or advance), the original position of the positive polarity signal or the negative polarity signal is taken as the reference point. Wherein the home position represents a time position before the calibration method is performed. Specifically, if the latch window is calibrated only once during the transmission of the differential signal, the original position can be understood as a time position after the delay compensation is completed for the differential signal. If the latch window is dynamically calibrated multiple times in the differential signal transmission process, the original position corresponds to the time position after the last calibration is completed.

The step three may be to move the positive polarity signal and the negative polarity signal to the right side simultaneously by TN after the step one is completed. Alternatively, after the end of the first step, the negative polarity signal in the data negative sub-channel is not restored to the original position, but the positive polarity signal is shifted to the right by TN and the negative polarity signal is shifted to the right by TN by 2 times in the third step.

Note that the above-mentioned dynamic window detection and calibration method is at the cost of not sacrificing data integrity, namely, through dynamic adjustment of the data negative sub-channel, the problem of sampling point failure which is likely to occur is pre-judged in advance and window calibration is performed in advance, at this time, data is always collected by taking the data positive sub-channel as a sample, and the collected data is always in an effective window, namely, the data collection process is always accurate.

In addition, the granularity and the step length of window calibration can be adjusted by setting TN size, and the frequency of window calibration can be set by t 0. The calibration frequency in dynamic calibration can be increased by reducing the value of t 0. According to the time of the effective delay amount setting in the prior FPGA, the technical scheme provided by the application can support the calibration frequency of millisecond level, and can cope with all factors which can influence the change of the external environment condition of the change of the effective data latch window, such as the most dominant temperature change.

In addition, the window detection method and the dynamic calibration method can be separately or simultaneously applied to the FPGA. The window detection method can be combined with an FPGA internal delay chain to obtain the position and the size of an effective latch window of each data channel and perform delay compensation, so that the data latch window can be maximized, and the data integrity is ensured. Meanwhile, the calibration method of the latch window can be used for solving the problem of error codes possibly caused by data latch window transfer. The method does not depend on a training data set, has extremely high universality, can greatly increase the stability of differential signal data acquisition and transmission, and provides powerful guarantee for a plurality of image acquisition and transmission occasions in the field of machine vision.

Referring to fig. 8, the window detection and calibration method provided by the present application can be applied to an FPGA. The specific workflow is shown in fig. 8, and at the initial time, the transmission system of the differential link performs power-up processing, and the respective internal initialization of the signal transmitting end and the signal receiving end is completed. Wherein link (i.e., latch window) dynamic detection and calibration may be a configuration option. When enabled, after the detection and calibration of the power-on initialization window are completed, in the working process, the dynamic detection and calibration module carries out real-time calibration on the latch window, if not enabled, the detection and calibration of the power-on initialization window are completed, namely the position of a sampling point in the subsequent work is always fixed, and the detection and calibration of the power-on single time can be adopted under the conditions that the differential link rate is not high or the window is large and the link is relatively stable.

In some embodiments, the present application further provides a window detection system of a differential link, as shown in fig. 9, where the window detection system includes:

the signal splitting module 901 is configured to split a differential signal in the differential link into a positive polarity signal and a negative polarity signal.

The signal acquisition module 902 is configured to acquire signal data of the positive polarity signal and the negative polarity signal under different delay times as a first data sequence and a second data sequence, respectively.

The data inverting module 903 is configured to perform inverting processing on the signal data in the second data sequence, so as to obtain a third data sequence.

The interval selection module 904 is configured to select a delay time interval in which data in the first data sequence and the third data sequence are identical as a latch window of the differential signal.

The embodiment of the application also provides an electronic device, as shown in fig. 10, which comprises a processor 1001, a communication interface 1002, a memory 1003 and a communication bus 1004, wherein the processor 1001, the communication interface 1002 and the memory 1003 complete communication with each other through the communication bus 1004,

A memory 1003 for storing a computer program;

The processor 1001 is configured to implement any of the above-described window detection methods for differential links when executing the program stored in the memory 1003.

The communication bus mentioned above for the electronic device may be a Peripheral component interconnect standard (Peripheral ComponentInterconnect, PCI) bus or an extended industry standard architecture (Extended Ind ustry StandardArchitecture, EISA) bus, or the like. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.

The communication interface is used for communication between the electronic device and other devices.

The Memory may include random access Memory (Random Access Memory, RAM) or may include Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.

The Processor may be a general-purpose Processor including a central processing unit (Central Processing Unit, CPU), a network Processor (Network Processor, NP), etc., or may be a digital signal Processor (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components.

In yet another embodiment of the present application, a computer readable storage medium is provided, in which a computer program is stored, which when executed by a processor, implements the steps of the method for detecting a window of any differential link described above.

In yet another embodiment of the present application, there is also provided a computer program product containing instructions that, when run on a computer, cause the computer to perform the window detection method steps of any of the differential links of the above embodiments.

The foregoing embodiments are merely for illustrating the technical solution of the present application, but not for limiting the same, and although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that modifications may be made to the technical solution described in the foregoing embodiments or equivalents may be substituted for parts of the technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solution of the embodiments of the present application in essence.

Claims

1. A method for detecting a window of a differential link, comprising:

Performing inverse processing on the signal data in the second data sequence to obtain a third data sequence;

Selecting the delay time interval with the same data in the first data sequence and the third data sequence as a latch window of the differential signal;

the differential link includes a clock signal;

The acquiring signal data of the positive polarity signal and the negative polarity signal under different delay time comprises:

delaying the clock signal in the differential link a plurality of times based on the fixed delay step size;

after each delay, signal data of the positive polarity signal and the negative polarity signal are acquired based on the delayed clock signal.

2. The method of claim 1, wherein the signal receiving end of the differential link is configured as a fully differential circuit.

3. The method according to any one of claims 1-2, further comprising:

4. A method according to claim 3, characterized in that the method further comprises:

Judging whether signal data of the working signal and signal opposite values of a first signal to be compared are the same, if so, keeping original time positions of the positive polarity signal and the negative polarity signal unchanged, and if not, reversely moving the positive polarity signal and the negative polarity signal to a preset time period relative to the original time positions;

The first signal to be compared is a signal after forward movement of the reference signal for a preset time period, the forward movement is represented by time delay or time advance, the reverse movement is represented by reverse time operation relative to the forward movement, signal data of the working signal and signal opposite values of the first signal to be compared are acquired from the same moment, and the signal opposite values of the signal to be compared are obtained by reversely processing the acquired signal data of the signal to be compared.

5. The method of claim 4, wherein the predetermined period of time is within half of the latch window time length.

6. A window detection system for a differential link, comprising:

The interval selection module is used for selecting the delay time interval with the same data in the first data sequence and the third data sequence as a latch window of the differential signal;

the differential link includes a clock signal;

7. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;

a memory for storing a computer program;

A processor for implementing the window detection method of any one of claims 1-5 when executing a program stored on a memory.

8. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, which computer program, when being executed by a processor, implements the window detection method according to any of claims 1-5.