CN118782471A - A ring-gate stacked nanodevice and its preparation method - Google Patents

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a ring-gate stack nano device and a preparation method thereof. The present invention forms a second sidewall by covering the entire surface with a second sidewall dielectric and filling the embedded groove, and then depositing an inner sidewall sacrificial layer on the surface of the second sidewall, and etching away part of the inner sidewall sacrificial layer to make it flush with the second sidewall dielectric, and then isotropically etching the second sidewall, and the etching stops at the depth of the inner sidewall sacrificial layer, and finally removing the inner sidewall sacrificial layer, so that the inner sidewall can be formed on both sides of the sacrificial layer. The preparation method of the inner sidewall can effectively reduce the thickness of the inner sidewall and accurately control the thickness of the inner sidewall. In addition, the present invention performs selective Si epitaxy at the concave part of the inner sidewall, thereby forming a continuous Si layer, and when the SiGe sacrificial layer is released, even if the ultra-thin inner sidewall is partially damaged, it will not cause damage to the GeSi epitaxial layer of the source/drain, which significantly improves the reliability of the ring-gate stack nano device.

Description

A ring-gate stacked nanodevice and its preparation method

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a ring-gate stacked nanodevice and a preparation method thereof.

Background Art

As transistor feature sizes continue to shrink, traditional MOSFET devices have undergone a transformation from a planar structure to a three-dimensional structure, improving device performance while reducing the impact of short channel effects. Currently, the research progress of GAA stacked nanosheet FETs has received widespread attention from academia and industry. The constantly updated preparation process and key processes, as well as the optimized device structure are hot research directions for new CMOS devices, and are considered to be mainstream devices after the 3nm node.

GAA stacked nanosheet FET is a new device developed on the basis of FinFET and Nanowire-FET, with a ring gate structure and horizontal nanosheet (NS) as a conductive channel. In terms of gate control, the ring gate structure has better gate control capability than the FinFET device structure, which can effectively suppress the short channel effect of the device; in terms of current drive, Nanosheet-GAAFET has an effective gate adjustable and vertical and horizontal stacking design, which can also significantly enhance the current drive performance of the device.

However, there are a large number of defects in the source and drain regions of the gate-all-around stacked nanodevice (GAA) of the conventional stacked nanosheet GAA-FET, which makes it difficult for the source and drain regions to provide stress to the channel region, which is not conducive to improving the carrier mobility in the channel region, resulting in poor working performance of the gate-all-around transistor.

In view of this, the present invention is proposed.

Summary of the invention

The purpose of the present invention is to provide a ring-gate stacked nanodevice and a preparation method thereof, which significantly improves the formation quality of the source region and the drain region, and facilitates the source region and the drain region to provide stress to the channel region, thereby significantly improving the reliability of the ring-gate stacked nanodevice.

In a first aspect, the present invention provides a method for preparing a gate-all-around stacked nanodevice, comprising the following steps:

Depositing a first spacer dielectric on both sides of the dummy gate structure, and then etching the first spacer dielectric in a horizontal direction to form a first spacer; performing source/drain etching on the fin to form a source/drain region for preparing a source/drain electrode on both sides of the first spacer; etching away the edge portion of the sacrificial layer along the center direction of the source/drain region to form an embedded groove;

Depositing a second sidewall dielectric so that the second sidewall dielectric covers the entire surface and fills the embedded groove to form a second sidewall; depositing an inner sidewall sacrificial layer on the surface of the second sidewall; isotropically etching the second sidewall; removing the inner sidewall sacrificial layer and retaining the second sidewall dielectric on both sides of the sacrificial layer to form an inner sidewall;

Performing selective Si epitaxy on the sidewall of the fin below the first sidewall, and aligning the fin with the first sidewall;

Epitaxially grown source/drain.

As a preferred embodiment of the present technical solution, the depth of the groove is 4-20 nm.

As a preferred embodiment of the present technical solution, when the second sidewall is isotropically etched, the etching depth does not exceed the depth of the inner sidewall sacrificial layer.

As a preferred embodiment of the present technical solution, the thickness of the second side wall or the inner side wall is 0.5-2 nm.

As a preferred embodiment of the present technical solution, the method for preparing the dummy gate structure includes:

Alternately growing a sacrificial layer and a channel layer on a provided substrate, etching the channel layer and the sacrificial layer into a plurality of periodically distributed fins, and forming a shallow trench isolation region between two adjacent fins;

A dummy gate layer and a dummy gate hard mask layer are sequentially formed on the exposed surface of the fin, and a dummy gate structure across the fin is formed through photolithography and etching patterning processes.

As a preferred embodiment of the present technical solution, the first spacer dielectric includes any one of silicon nitride, nitrogen-doped silicon oxide and nitrogen-doped silicon carbide;

The second spacer dielectric includes any one of silicon oxycarbon nitride, silicon oxide carbon, silicon oxynitride and nitrogen-doped silicon carbide;

The material of the inner sidewall sacrificial layer includes any one of carbon, polysilicon and polyimide.

As a preferred embodiment of the present technical solution, during the selective Si epitaxy, the epitaxial Si is in-situ doped to form a Si epitaxial region.

As a preferred embodiment of the present technical solution, the following steps are also included:

After epitaxially growing the source/drain, an isolation layer dielectric is deposited on the source/drain, and the isolation layer dielectric is chemically mechanically polished until the dummy gate hard mask layer is removed to expose the dummy gate layer;

Etching to remove the dummy gate layer;

Etching to remove the sacrificial layer and release the channel layer to form a nanosheet channel;

Depositing a high-K metal gate to form a metal gate surrounding the nanosheet channel;

The isolation layer dielectric is continuously deposited to form contact holes respectively contacting the source/drain and the metal gate, the contact holes are etched, and silicon compounds are deposited to form a conductive channel in the contact holes.

In the second aspect, the present invention further discloses a ring-gate stacked nanodevice, which should also fall within the protection scope of the present invention. The ring-gate stacked nanodevice includes a substrate, a nanosheet channel, a metal gate, a source/drain, a Si epitaxial region and an inner sidewall.

The nanosheet channel is located above the substrate, the metal gate is arranged around the nanosheet channel, the source/drain is connected to the nanosheet channel, the Si epitaxial region and the inner sidewall are arranged between the source/drain and the metal gate, and the Si epitaxial region is close to the source/drain.

As a preferred embodiment of the present technical solution, the material of the Si epitaxial region is in-situ doped silicon.

The method for preparing the ring-gate stacked nanodevice of the present invention has at least the following technical effects:

The present invention forms a second sidewall by covering the entire surface with a second sidewall dielectric and filling the embedded groove, and then depositing an inner sidewall sacrificial layer on the surface of the second sidewall, and etching away part of the inner sidewall sacrificial layer to make it flush with the second sidewall dielectric, and then isotropically etching the second sidewall, and the etching stops at the depth of the inner sidewall sacrificial layer, and finally removing the inner sidewall sacrificial layer, so that the inner sidewall can be formed on both sides of the sacrificial layer. The preparation method of the inner sidewall in the ring-gate stacked nano device can effectively reduce the thickness of the inner sidewall and accurately control the thickness of the inner sidewall. In addition, the present invention performs selective Si epitaxy at the recess of the inner sidewall, thereby forming a continuous Si layer, and when the SiGe sacrificial layer is released, even if the ultra-thin inner sidewall is partially damaged, it will not cause damage to the GeSi epitaxial layer of the source/drain. Therefore, the method significantly improves the formation quality of the source region and the drain region, and is conducive to the source region and the drain region to provide stress to the channel region, and significantly improves the reliability of the ring-gate stacked nano device.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a cross-sectional view along the X-X' direction after a SiGe/Si stacked superlattice layer is grown on a silicon substrate according to the present invention;

FIG2 is a schematic diagram of a three-dimensional structure of the present invention after fins are formed on a substrate;

FIG3 is a cross-sectional view along the X-X' direction after the superlattice stack is made into a plurality of periodically distributed fins according to the present invention;

FIG4 is a cross-sectional view along the X-X' direction after a shallow trench isolation region is formed between two adjacent fins of the present invention;

FIG5 is a cross-sectional view along the X-X' direction after a dummy gate layer is formed on the exposed fin surface of the present invention;

FIG6 is a cross-sectional view along the Y-Y' direction after a dummy gate layer is formed on the exposed fin surface of the present invention;

FIG7 is a cross-sectional view along the Y-Y' direction after the dummy gate structure is patterned and formed according to the present invention;

FIG8 is a cross-sectional view along the Y-Y' direction after the first sidewall dielectric is deposited according to the present invention;

FIG9 is a schematic diagram of a three-dimensional structure after etching the first sidewall dielectric to form the first sidewall according to the present invention;

FIG10 is a cross-sectional view along the Y-Y' direction after etching the first sidewall dielectric to form the first sidewall according to the present invention;

FIG11 is a cross-sectional view along the Y-Y' direction after the fin is etched for source/drain according to the present invention;

FIG12 is a cross-sectional view along the Y-Y' direction after etching the edge of the sacrificial layer of the present invention;

FIG13 is a cross-sectional view along the Y-Y' direction after the second sidewall dielectric is deposited according to the present invention;

FIG14 is a cross-sectional view along the Y-Y' direction after the inner sidewall sacrificial layer is deposited according to the present invention;

FIG15 is a cross-sectional view along the Y-Y' direction after etching the inner sidewall sacrificial layer of the present invention;

FIG16 is a cross-sectional view along the Y-Y' direction after etching the second sidewall according to the present invention;

FIG17 is a cross-sectional view along the Y-Y' direction after etching the inner sidewall sacrificial layer of the present invention;

FIG18 is a cross-sectional view along the Y-Y' direction after selective Si epitaxy is performed on the sidewall of the entire SiGe/Si stacked fin according to the present invention;

FIG19 is a cross-sectional view along the Y-Y' direction after the fin is etched for source/drain using the dummy gate hard mask layer and the first sidewall as a mask according to the present invention;

FIG20 is a cross-sectional view along the Y-Y' direction after forming epitaxially grown source/drain electrodes according to the present invention;

FIG21 is a cross-sectional view along the Y-Y' direction after an isolation layer dielectric is deposited on the source/drain of the present invention;

FIG22 is a cross-sectional view along the Y-Y' direction after the dummy gate layer of the present invention is etched away;

FIG23 is a cross-sectional view along the Y-Y' direction after selectively etching the sacrificial layer in the superlattice stack according to the present invention;

FIG24 is a cross-sectional view along the X-X' direction after selectively etching the sacrificial layer in the superlattice stack according to the present invention;

FIG25 is a cross-sectional view along the X-X' direction after depositing a high-K metal gate according to the present invention;

FIG26 is a cross-sectional view along the Y-Y' direction after depositing a high-K metal gate according to the present invention;

FIG27 is a cross-sectional view of the ring-gate stacked nanodevice of the present invention along the Y-Y’ direction.

Description of reference numerals:

1: substrate; 2: sacrificial layer; 3: channel layer; 4: shallow trench isolation region; 5: dummy gate layer; 6: dummy gate hard mask layer; 7: first sidewall; 8: groove; 9: second sidewall; 10: inner sidewall sacrificial layer; 11: inner sidewall; 12: source/drain; 13: isolation layer; 14: metal gate; 15: conductive channel.

DETAILED DESCRIPTION

The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as limiting the present invention.

In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

Example 1

This embodiment provides a method for preparing a gate-all-around stacked nanodevice, which specifically includes the following steps:

S1, sequentially growing a sacrificial layer 2 and a channel layer 3 on a substrate 1, etching the channel layer 3 and the sacrificial layer 2 into a plurality of periodically distributed fins, and forming a shallow trench isolation region 4 between two adjacent fins;

S2, forming a dummy gate structure on the exposed fin surface;

S3, depositing a first spacer dielectric on both sides of the dummy gate structure, and then etching the first spacer dielectric in the horizontal direction to form a first spacer 7; performing source/drain etching on the fin to form a source/drain region for preparing a source/drain 12 on both sides of the first spacer 7; etching away the edge portion of the sacrificial layer 2 along the center direction of the source/drain region to form an embedded groove 8;

S4, depositing a second sidewall dielectric so that the second sidewall dielectric covers the entire surface and fills the embedded groove 8, forming a second sidewall 9; depositing an inner sidewall sacrificial layer 1 on the surface of the second sidewall 9; accurately isotropically etching the second sidewall 9, and the etching depth does not exceed the depth of the inner sidewall sacrificial layer 10; removing the inner sidewall sacrificial layer 10, retaining the second sidewall dielectric on both sides of the sacrificial layer 2, forming an inner sidewall 11;

S5, performing selective Si epitaxy on the sidewall of the fin below the first sidewall 7, and aligning the fin with the first sidewall 7;

S6, epitaxially growing the source/drain 12, and doping the source/drain 12 at the same time;

S7, depositing an isolation layer dielectric on the source/drain 12, and performing chemical mechanical polishing on the isolation layer dielectric until the dummy gate hard mask layer 6 is removed to expose the dummy gate layer 5;

S8, etching to remove the dummy gate layer 5;

S9, etching and removing the sacrificial layer 2, releasing the channel layer 3 to form a nanosheet channel;

S10, depositing a high-K metal gate to form a metal gate 14 surrounding the nanosheet channel;

S11, continue to deposit isolation layer dielectric to form contact holes respectively contacting the source/drain 12 and the metal gate 14, etch the contact holes, deposit silicon compounds, and form conductive channels 15 in the contact holes.

The preparation method is described in more detail below:

In step S1, as shown in FIG1, a sacrificial layer 2 and a channel layer 3 are first grown in sequence on a substrate 1 by epitaxy, wherein the substrate 1 is generally a silicon substrate 1, the sacrificial layer 2 is generally SiGe, and the channel layer 3 is generally Si. The sacrificial layer 2 and the channel layer 3 are a superlattice structure, and the Si layer determines the number of subsequent nanowires. The Si layer is ≥1, and each layer is less than 30 nm. The final thickness directly determines the height of the nanosheet channel and the electrical properties.

On the basis of the above, as shown in FIG2-3, the sacrificial layer 2 and the channel layer 3 are further formed into a plurality of periodically distributed fins. Specifically, a hard mask layer is deposited above the topmost channel layer 3, and after patterning, the epitaxially grown superlattice stack is made into a plurality of periodically distributed fins through an etching process, the height of the fins is 10nm-400nm, the width is 1-100nm, and the etching stops at the substrate 1, or below the substrate 1.

On the basis of the above, as shown in FIG4 , a shallow trench isolation region 4 (STI) is formed between two adjacent fins. Specifically, an insulating dielectric material is first deposited and planarized, and after the hard mask layer is exposed, the hard mask layer is removed by wet or dry etching, and then the insulating dielectric material is selectively etched back to expose the three-dimensional fin structure, and a shallow trench isolation region 4 is formed between adjacent fins. The upper surface of the shallow trench isolation region 4 is generally flush with the interface between the superlattice stacked structure in the fin and the single crystal silicon of the substrate 1, and may also be higher or lower than the interface level.

In step S2, as shown in FIGS. 5-6, a dummy gate layer 5 and a dummy gate hard mask layer 6 are sequentially formed on the exposed fin surface. Specifically, an oxide layer and polysilicon (or amorphous silicon) are sequentially deposited above the shallow trench isolation region 4, and CMP is performed, and then a dummy gate hard mask layer 6 is deposited; then, as shown in FIG. 7, a dummy gate structure across the fin is formed by photolithography and etching patterning processes, and after etching, the dummy gate hard mask layer 6 above the dummy gate structure is retained.

The material of the dummy gate hard mask layer 6 may be oxide, carbide, carbide, organic matter, etc.

In step S3, as shown in Figures 8-9, a first sidewall dielectric is deposited on both sides of the dummy gate structure, and then the sidewall dielectric in the horizontal direction is etched, leaving only the dielectric on the sidewalls of the dummy gate and the hard mask layer to form a first sidewall 7; then, based on Figure 10, referring to Figure 11, the hard mask layer 4 and the first sidewall 7 are used as masks, and the fin is etched for source/drain through an etching process to form source/drain regions for preparing source/drain electrodes 12 on both sides of the first sidewall 7, and the edge portion of the SiGe sacrificial layer 2 is etched away in the center direction of the source/drain electrode 12 by a pull-back etching method to form an embedded groove 8, wherein the depth of the groove 8 is 4-20nm, and preferably 5nm (Figure 12).

The material of the first spacer dielectric may be silicon nitride, nitrogen-doped silicon oxide, nitrogen-doped silicon carbide, etc. During etching, the integrity of the channel layer 3 can be ensured because the sacrificial layer 2 and the channel layer 3 have a large etching selectivity.

In step S4, as shown in FIG13, a second sidewall dielectric is deposited so that the second sidewall dielectric covers the entire surface and fills the embedded groove 8 to form a second sidewall 9; further, based on FIG13, referring to FIG14, an inner sidewall sacrificial layer 10 is deposited on the surface of the second sidewall 9, such as a sacrificial layer of carbon, polysilicon and polyimide, and the sacrificial layers of these materials can be removed by etching or chemical solutions, thereby releasing the required structure; based on FIG14, referring to FIG15, the inner sidewall sacrificial layer 10 is etched to be flush with the second sidewall dielectric; as shown in FIG16, the second sidewall 9 is precisely isotropically etched, and the etching depth does not exceed the depth of the inner sidewall sacrificial layer 10; finally, as shown in FIG17, the inner sidewall sacrificial layer 10 is removed, and the second sidewall dielectric on both sides of the sacrificial layer 2 is retained, i.e., an inner sidewall 11 is formed, wherein the thickness of the inner sidewall 11, i.e., the thickness of the second sidewall 9 is 0.5-2nm.

The material of the second sidewall dielectric may be SiOCN (silicon oxycarbon nitride), SiOC (silicon oxygen carbon), SiON (silicon oxynitride), NDC (nitrogen-doped silicon carbide) or other dielectrics.

In step S5 , as shown in FIGS. 18-19 , first, selective Si epitaxy is performed on the fin sidewall below the first sidewall 7 , and then, the fin is etched for source/drain using the dummy gate hard mask layer 4 and the first sidewall 7 as masks to align the fin with the first sidewall 7 .

Among them, when performing selective Si epitaxy, in-situ doping can be performed as required to form a steep, evenly distributed Si epitaxial region with a precisely controllable lateral junction depth through doping diffusion, thereby controlling the effective length of the channel, avoiding the short channel effect caused by improper doping of the Si epitaxial region, and improving the performance and reliability of the device.

In step S6, referring to FIG. 20, the source/drain 12 is epitaxially grown by metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth or the like, or a combination of the foregoing, and the source/drain 12 is doped at the same time. For P-type FET, the source/drain 12 material is boron-doped SiGe (SiGe:B), and for N-type FET, the source/drain 12 material is phosphorus-doped silicon (Si:P).

It can be seen that the inner sidewall 11 of the present invention is covered with the entire surface by the second sidewall dielectric and filled with the embedded groove 8 to form the second sidewall 9, and then the inner sidewall sacrificial layer 10 is deposited on the surface of the second sidewall 9, and part of the inner sidewall sacrificial layer 10 is etched away to make it flush with the second sidewall dielectric, and then the second sidewall 9 is isotropically etched, and the etching stops at the depth of the inner sidewall sacrificial layer 10, and finally the inner sidewall sacrificial layer 10 is removed, and the inner sidewall 11 can be formed on both sides of the sacrificial layer. The preparation method of the inner sidewall 11 can effectively reduce the thickness of the inner sidewall 11 and accurately control the thickness of the inner sidewall 11. In addition, the present invention performs selective Si epitaxy in the recessed part of the inner side wall 11, thereby forming a continuous Si layer. When the SiGe sacrificial layer 2 is released, even if the ultra-thin inner side wall 11 is partially damaged, it will not cause damage to the GeSi epitaxial layer of the source/drain 12. Therefore, this method significantly improves the formation quality of the source and drain regions, and facilitates the source and drain regions to provide stress to the channel region, thereby significantly improving the reliability of the ring-gate stacked nanodevice.

In step S7, after forming the source/drain 12, as shown in Figure 21, an isolation layer dielectric is deposited on the source/drain 12, and the isolation layer dielectric is chemically mechanically polished to make it flat to obtain an isolation layer 13, and the dummy gate hard mask layer 6 is further removed to expose the dummy gate layer 5.

In step S8, based on the above, further, as shown in FIG. 22, the dummy gate layer 5 formed of the polycrystalline silicon (p-Si) or amorphous silicon (a-Si) is etched away by a selective etching or corrosion process.

In step S9, based on the above, further, as shown in FIGS. 23-24 , the sacrificial layer 2 in the superlattice stack is selectively etched to release the nanosheet channel.

In step S10, based on the above, further, as shown in FIGS. 25-26, high-K metal gates are sequentially deposited and CMP is performed to form a metal gate 14 surrounding the nanosheet channel.

In step S11, based on the above, further, as shown in FIG. 27, an isolation layer dielectric is deposited on the top, and dielectric CMP is performed, and then contact hole lithography and etching are performed, silicide is deposited, and a conductive channel 15 is formed in the contact hole.

In steps S9-S11, specifically, the nanosheet channel is located above the substrate 1, the metal gate 14 surrounds the nanosheet channel, the source/drain 12 is connected to the nanosheet channel, the isolation layer 13 is located above the source/drain 12; and the conductive channel 15 is arranged inside the isolation layer 13.

Example 2

As shown in Figure 27, this embodiment provides a ring-gate stacked nanodevice, specifically including a substrate 1, a nanosheet channel, a metal gate 14, a source/drain 12, a Si epitaxial region and an inner sidewall 11, wherein the nanosheet channel is located above the substrate 1, the metal gate 14 is arranged around the nanosheet channel, the source/drain 12 is connected to the nanosheet channel, the Si epitaxial region and the inner sidewall 11 are arranged between the source/drain 12 and the metal gate 14, and the Si epitaxial region is close to the source/drain 12.

The present invention performs selective Si epitaxy at the recessed portion of the inner sidewall 11, and the continuous Si layer thus formed serves as a Si epitaxial region. When the SiGe sacrificial layer is released, even if the ultra-thin inner sidewall 11 is partially damaged, the GeSi epitaxial layer of the source/drain 12 will not be damaged, thereby significantly improving the reliability of the ring-gate stacked nanodevice.

Specifically, when selective Si epitaxy is performed on the sidewalls of the fins below the first sidewall 7, in-situ doping can be performed as required to form a steep, uniformly distributed Si epitaxial region with a precisely controllable lateral junction depth through doping diffusion, thereby controlling the effective length of the channel, avoiding the short channel effect caused by improper doping of the Si epitaxial region, and improving the performance and reliability of the device. Therefore, the material of the Si epitaxial region is preferably in-situ doped silicon.

The gate-all-around stacked nanodevice of the embodiment of the present invention is formed by the aforementioned method embodiment 1, wherein the materials and characteristics of each part can be referred to the aforementioned method embodiment, and will not be described in detail here.

In the above description, the technical details of patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. The preparation method of the ring gate stacked nano device is characterized by comprising the following steps of:

Depositing first side wall media at two sides of the false gate structure, and then etching the first side wall media in the horizontal direction to form a first side wall (7); performing source/drain etching on the fin, and forming source/drain regions for preparing source/drain electrodes (12) on two sides of the first side wall (7); etching off the edge part of the sacrificial layer (2) along the central direction of the source/drain region to form an embedded groove (8);

Depositing a second side wall medium, so that the second side wall medium covers the whole surface and is filled with the embedded groove (8) to form a second side wall (9); depositing an inner side wall sacrificial layer (10) on the surface of the second side wall (9); isotropically etching the second side wall (9); removing the inner side wall sacrificial layer (10), and reserving second side wall media at two sides of the sacrificial layer (2) to form an inner side wall (11);

Carrying out selective Si epitaxy on the side wall of the fin below the first side wall (7) and aligning the fin with the first side wall (7);

Epitaxially grown source/drains (12).

2. The preparation method according to claim 1, characterized in that the depth of the grooves (8) is 4-20nm.

3. The method according to claim 1, characterized in that the etching depth does not exceed the depth of the inner wall sacrificial layer (10) when the second side wall (9) is isotropically etched.

4. The method of manufacturing according to claim 1, characterized in that the thickness of the second side wall (9) or the inner side wall (11) is 0.5-2nm.

5. The method of manufacturing of claim 1, wherein the method of manufacturing the dummy gate structure comprises:

Alternately growing a sacrificial layer (2) and a channel layer (3) on a provided substrate (1), etching the channel layer (3) and the sacrificial layer (2) into a plurality of fins which are distributed periodically, and forming shallow slot isolation areas (4) between two adjacent fins;

And forming a dummy gate layer (5) and a dummy gate hard mask layer (6) on the exposed surface of the fin in sequence, and forming a dummy gate structure crossing the fin through photoetching and etching patterning processes.

6. The method of manufacturing according to claim 1, wherein the first sidewall medium comprises any one of silicon nitride, nitrogen doped silicon oxide, and nitrogen doped silicon carbide;

the second side wall medium comprises any one of silicon oxycarbide, silicon oxynitride and nitrogen doped silicon carbide;

The material of the inner side wall sacrificial layer (10) comprises any one of carbon, polysilicon and polyimide.

7. The method of claim 1, wherein the Si epitaxial region is formed by in-situ doping of the epitaxial Si during selective Si epitaxy.

8. The method of manufacturing according to claim 1, further comprising the steps of:

After epitaxially growing the source/drain electrode (12), depositing an isolation layer medium on the source/drain electrode (12), and carrying out chemical mechanical polishing on the isolation layer medium until the dummy gate hard mask layer (6) is removed and the dummy gate layer (5) is exposed;

etching to remove the false gate layer (5);

Etching to remove the sacrificial layer (2) and releasing the channel layer (3) to form a nano-sheet channel;

depositing a high-K metal gate to form a metal gate (14) surrounding the nanoplatelet channel;

And continuing depositing isolation layer medium, forming contact holes respectively contacted with the source/drain electrode (12) and the metal gate (14), etching the contact holes, depositing silicon compound, and forming conductive channels (15) in the contact holes.

9. A ring gate stacked nano device is characterized by comprising a substrate (1), a nano sheet channel, a metal gate (14), a source/drain electrode (12), a Si epitaxial region and an inner side wall (11),

The nano-sheet channel is located above the substrate (1), the metal gate (14) is arranged around the nano-sheet channel, the source/drain (12) is connected with the nano-sheet channel, the Si epitaxial region and the inner side wall (11) are arranged between the source/drain (12) and the metal gate (14), and the Si epitaxial region is close to the source/drain (12).

10. The gate-all-around stacked nano-device according to claim 9, wherein the Si epitaxial region is made of in-situ doped silicon.