CN118796291B - Host awakening method - Google Patents
Host awakening method Download PDFInfo
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- CN118796291B CN118796291B CN202411269285.9A CN202411269285A CN118796291B CN 118796291 B CN118796291 B CN 118796291B CN 202411269285 A CN202411269285 A CN 202411269285A CN 118796291 B CN118796291 B CN 118796291B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4418—Suspend and resume; Hibernate and awake
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- General Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
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Abstract
本发明公开了一种主机唤醒方法。为克服非标准的主机无法通过传统的PCIe方式唤醒的缺陷，本发明的主机唤醒方法包括如下步骤：USB设备发送远程唤醒请求至USB主机模块；USB主机模块发送第一唤醒信号至PCIe模块中的休眠与唤醒模块；休眠与唤醒模块从LTSSM模块中获取链路状态，并根据获取的链路状态判断是否处于L1模式；若判断结果指示处于L1模式，则进一步判断从PCIe插槽获取的PERST信号是否为低电平；若判断结果指示PERST信号是低电平，则拉低休眠与唤醒模块向PCIe插槽发送的第二唤醒信号；若判断结果指示PERST信号是高电平，则发送PME消息至PCIe插槽，以唤醒主机。本发明实现了通过PCIe方式也能唤醒非标准的主机的技术效果。
The present invention discloses a host wake-up method. In order to overcome the defect that a non-standard host cannot be awakened by a traditional PCIe method, the host wake-up method of the present invention comprises the following steps: a USB device sends a remote wake-up request to a USB host module; the USB host module sends a first wake-up signal to a sleep and wake-up module in a PCIe module; the sleep and wake-up module obtains a link state from an LTSSM module, and judges whether it is in L1 mode according to the obtained link state; if the judgment result indicates that it is in L1 mode, it further judges whether a PERST signal obtained from a PCIe slot is at a low level; if the judgment result indicates that the PERST signal is at a low level, the second wake-up signal sent by the sleep and wake-up module to the PCIe slot is pulled down; if the judgment result indicates that the PERST signal is at a high level, a PME message is sent to the PCIe slot to wake up the host. The present invention achieves the technical effect of waking up a non-standard host by a PCIe method.
Description
Technical Field
The invention relates to the field of computers, in particular to a host awakening method.
Background
Peripheral component interconnect express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIe) and universal serial bus (Universal Serial Bus, USB) are two widely recognized interface technologies in the art. Modern computer systems commonly employ PCIe as their internal high speed bus standard and integrate multiple PCIe slots on the motherboard so that additional hardware devices connect directly to the central processor through these slots. Meanwhile, most computers are provided with USB host controller interfaces for connecting various USB peripheral devices. Notably, many USB host interfaces are also in essence communicating with the CPU via the PCIe bus. Therefore, a conversion chip or a circuit module for converting PCIe into USB is specially designed to realize signal adaptation and conversion between the PCIe slot and the USB interface.
To optimize energy efficiency, the computer enters a low power standby state or sleep mode instead of being completely shut down when idle or no task is performed, thereby avoiding time loss caused by restarting. During sleep, if the computer needs to be re-activated, a wake event is typically triggered by a device (e.g., keyboard input) connected to the USB host interface. The specific process involves the USB device sending a wake-up signal to a USB host module in a PCIe to USB chip, then the wake-up signal is forwarded to the PCIe portion, and then specific wake-up instructions are communicated to the system host.
In a typical sleep management strategy, the PCIe link switches to a low power mode such as L1 mode or L2 mode to conserve energy. In standard operation, the L1 mode maintains the PCIe reset signal (PCIE RESET, PERST) high, ensuring that the reference clock is active and the main power is not turned off. Upon receiving the wake request, the PCIe device in L1 mode will notify the host over the link using a Power management event (Power MANAGEMENT EVENT, PME) message, causing the host to go out of dormancy and instruct all PCIe Endpoints (EPs) to exit L1 mode.
Conversely, in L2 mode the PERST signal is pulled low, indicating that the main power is off and the reference clock is off, rather than indicating a reset signal. The wake-up operation relies on pulling down the external wake-up signal, as link communication is not available at this stage. After the host wakes up, the main power supply and the clock source are restarted, and PCIe link activity is restored.
However, there are some non-standard hosts on the market that have different management and wake-up mechanisms for PCIe links during dormancy than the standard practices described above, making existing wake-up techniques difficult to apply to these special devices.
After the computer enters dormancy, not only the PCIe link is switched into L1 mode, but also the PERST signal is abnormally pulled down, and the main power supply is cut off, and only the wake-up signal out of band is pulled down to be used as a wake-up path. This specific behavior challenges existing PCIe wake solutions, and there is an urgent need to develop new wake mechanisms to be compatible with and solve such non-standard host wake problems.
In general terms, non-standard hosts behave differently from standard hosts after going to sleep, mainly in the following ways:
(1) After the standard host goes dormant, the PCIe link can be selectively put into the L1 mode or the L2 mode, whereas the non-standard host can only put the PCIe link into the L1 mode.
(2) After the standard host enters the L2 mode, the PERST signal is pulled down, the reference clock is closed, and the main power supply is removed; after the nonstandard host enters the L1 mode, the PERST signal is also pulled down, the reference clock is turned off, and the main power supply is removed.
(3) After the standard host enters the L1 mode, the PCIe device can wake up the host by sending a PME message through a PCIe link, and the standard host only needs to wake up by using a wake-up signal in the L2 mode; whereas a non-standard host needs to wake up by pulling down the wake-up signal.
In addition, the PCIe endpoint chip on the market must receive the wake-up signal sent by the application layer after entering the L2 mode, and pull down the wake-up signal of the PCIe link, but cannot send out the wake-up signal in the L1 mode; also, in the L1 mode, the PCIe PERST signal is treated as a reset signal instead of a primary power supply withdrawal signal. Therefore, when the PERST signal is pulled low, the entire chip is reset, so that all configuration information is lost, and the PCIe link is broken, so that the connection relationship between PCIe and the host is invalid.
For some non-standard hosts on the market, the behavior after entering the sleep mode is different from that of the traditional standard hosts, so that the traditional PCIe wake-up mode cannot be used for waking up the non-standard hosts. The invention mainly aims to solve the problem that the nonstandard host cannot wake up through the PCIe link when the PCIe link enters the L1 mode.
Disclosure of Invention
In order to alleviate or partially alleviate the above technical problem, the solution of the present invention is as follows:
A host awakening method is applied to a PCIe-to-USB chip and comprises the following steps: the USB equipment sends a remote wake-up request to the USB host module; the USB host module sends a first wake-up signal to a dormancy and wake-up module in the PCIe module; the dormancy and awakening module acquires a link state from the LTSSM module and judges whether the dormancy and awakening module is in an L1 mode according to the acquired link state; if the judging result indicates that the PCIe slot is in the L1 mode, further judging whether a PERST signal acquired from the PCIe slot is in a low level or not; if the judging result indicates that the PERST signal is of a low level, the second wake-up signal sent to the PCIe slot by the sleep and wake-up module is pulled down; if the judging result indicates that the PERST signal is at a high level, a PME message is sent to the PCIe slot so as to wake up the host; in addition, the PCIe module also comprises a PERST processing module; when a PERST processing module in the PCIe module receives the PERST signal, judging whether the PERST signal is in a low level or not; if yes, further judging whether the link state is in the L1 mode or the L2 mode; if the judging result indicates that the link state is not in the L1 mode or the L2 mode, resetting the PCIe-to-USB chip; the PCIe-to-USB chip comprises the PCIe module and the USB host module.
Further, the USB host module sends a first wake-up signal specifically: and the power consumption control module in the USB host module sends the first wake-up signal.
Further, the USB device is a keyboard or a mouse.
Further, the LTSSM module sends a link status to a PERST processing module and a sleep and wake module.
Further, the host is a standard host or a non-standard host.
The technical scheme of the invention has one or more of the following beneficial technical effects:
the invention can realize the purpose of waking up the host computer through the USB device on the standard host computer, and can realize the purpose of waking up the host computer through the USB device on the nonstandard host computer.
Furthermore, other advantageous effects that the present invention has will be mentioned in the specific embodiments.
Drawings
FIG. 1 is a block diagram of a PCIe to USB chip configuration of the present invention;
FIG. 2 is an information processing flow diagram of a PERST processing module;
FIG. 3 is a flow chart of information processing of the sleep and wake module.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. Those skilled in the art will appreciate that the words "first," "second," and the like do not limit the number and order of execution.
FIG. 1 is a block diagram of a PCIe to USB chip configuration according to the present invention. The PCIe-to-USB chip comprises a PCIe module and a USB host module. The USB host module comprises a USB port 1 and a USB port 2, and data connection is established through the USB port 1 and the USB port 2 with various USB devices such as a keyboard and a mouse respectively by means of cables. And the PCIe module in the PCIe-to-USB chip establishes data connection with the PCIe slot through the first interface, and establishes data connection with the USB host module through the second interface.
The PCIe module includes: sleep and wake module, PERST processing module, link training and state machine (LINK TRAINING AND Status STATE MACHINE, LTSSM) module, physical layer, data link layer, transaction layer, and application interface layer. The physical layer, the data link layer, the transaction layer, and the application interface layer are common general knowledge in the art, and are not described herein.
For example, the LTSSM module may send link states, which may include L1 mode and L2 mode, to the PERST processing module, the sleep and wake module.
In the present invention, the L0 mode, the L1 mode and the L2 mode are general technical terms in the art and belong to common general knowledge of a person skilled in the art.
In the present invention, a plurality of data links may be established in the first interface. Illustratively, the sleep and wake module sends a second wake signal to the PCIe slot; the PCIe slot sends a PERST signal to a PERST processing module in the PCIe module; the PCIe slot sends clock signals CLKP, CLKN, and data signals pcie_rx to the PCIe module, which sends request clocks CLKREQ and data signals pcie_tx to the PCIe slot. The specific means of establishing these data links are well known to those of ordinary skill in the art and will not be described in detail herein.
The USB host module includes a power consumption control module, an extensible host controller interface (eXtensible Host Controller Interface, xHCI) controller, and a root hub. The USB host module, specifically, may be a power consumption control module in the USB host module, sends a first wake-up signal to the sleep and wake-up module. The xHCI controller and root hub are common general knowledge in the art and will not be described in detail here.
Fig. 2 is an information processing flow diagram of a PERST processing module. And the PERST processing module receives a PERST signal from the PCIe slot, judges whether the PERST signal is at a low level after receiving the PERST signal, and does not process if the PERST signal is at the low level. If yes, further judging whether the current link is in an L1 mode or an L2 mode according to the link state sent by the LTSSM module. If yes, not processing; if not, resetting the PCIe to USB chip.
In other words, after the link enters the L1 mode, if the PERST signal is received as a low level, the reset operation is not performed, so that the nonstandard host is prevented from pulling the low PERST signal in the L1 mode, and erroneous reset of the PCIe to USB chip is prevented.
FIG. 3 is a flow chart of information processing of the sleep and wake module. The dormancy and wake-up module receives a first wake-up signal from the power consumption control module and judges whether the link is in an L1 mode or not. If not, the processing is not performed. If so, it is further determined whether the PERST signal is low. If not, then sending PME message to wake up host. If yes, the second wake-up signal is pulled down to wake up the host.
In other words, after the link enters the L1 mode, after receiving the first wake-up signal sent by the sleep and wake-up module in the USB host, the PME message is not directly sent according to the conventional scheme, but it is further determined whether the PERST signal is at a low level, and the PME message is sent according to this determination.
An exemplary procedure for entering L1 mode at a non-standard host and remotely waking up by a USB device is:
the host modifies the PCIe power management Device power management state (D-States) from D0 to D3, where D0 represents the Device fully on state and D3 is the Device fully off state. Then, the remote wake-up function of the USB device is started, and the host enters a low power consumption mode.
Then, after negotiating with the PCIe module, the host enters the L1 mode and pulls down the PERST signal.
At this time, according to the foregoing technical solution of the present invention, after detecting that the PERST signal is low, the PCIe module is combined with the current L1 mode, and does not reset the PCIe to USB chip, thereby avoiding an erroneous reset operation.
After that, when the user sends a remote wake-up request to the USB host module through the USB device, according to the technical solution of the present invention, the USB host module sends a first wake-up signal to the sleep and wake-up module.
After receiving the first wake-up signal, the PCIe module does not send the PME message in a conventional manner, but pulls down the second wake-up signal, negotiates with the host to exit the L1 mode, and enters the L0 mode.
Through the scheme, the invention can realize the purpose of waking up the host through the USB device on the standard host, and can also realize the purpose of waking up the host through the USB device on the nonstandard host.
Numerous specific details are set forth in the above description in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (5)
1. A host awakening method is applied to a PCIe-to-USB chip and is characterized by comprising the following steps:
the USB equipment sends a remote wake-up request to the USB host module;
the USB host module sends a first wake-up signal to a dormancy and wake-up module in the PCIe module;
The dormancy and awakening module acquires a link state from the LTSSM module and judges whether the dormancy and awakening module is in an L1 mode according to the acquired link state;
If the judging result indicates that the PCIe slot is in the L1 mode, further judging whether a PERST signal acquired from the PCIe slot is in a low level or not;
If the judging result indicates that the PERST signal is of a low level, the second wake-up signal sent to the PCIe slot by the sleep and wake-up module is pulled down;
If the judging result indicates that the PERST signal is at a high level, a PME message is sent to the PCIe slot so as to wake up the host; in addition, in the case of the optical fiber,
The PCIe module also comprises a PERST processing module;
When a PERST processing module in the PCIe module receives the PERST signal, judging whether the PERST signal is in a low level or not;
If yes, further judging whether the link state is in the L1 mode or the L2 mode;
If the judging result indicates that the link state is not in the L1 mode or the L2 mode, resetting the PCIe-to-USB chip; wherein,
The PCIe to USB chip comprises the PCIe module and the USB host module.
2. The host wakeup method according to claim 1, wherein:
the USB host module sends a first wake-up signal specifically:
and the power consumption control module in the USB host module sends the first wake-up signal.
3. The host wakeup method according to claim 2, wherein:
The USB device is a keyboard or a mouse.
4. A host wakeup method according to claim 3, wherein:
The LTSSM module sends a link status to a PERST processing module and a sleep and wake module.
5. The host wakeup method of claim 4, wherein:
the host is either a standard host or a non-standard host.
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| CN118796291B true CN118796291B (en) | 2024-11-19 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107741780A (en) * | 2012-12-20 | 2018-02-27 | 英特尔公司 | Click on near-field communication (NFC) equipment for waking up and clicking on and log in |
| CN107957885A (en) * | 2017-12-01 | 2018-04-24 | 天津麒麟信息技术有限公司 | A kind of PCIE link devices based on platform of soaring are standby and restoration methods |
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| US9467120B1 (en) * | 2013-12-19 | 2016-10-11 | Altera Corporation | Power management for PCI express |
| WO2022071925A1 (en) * | 2020-09-30 | 2022-04-07 | Hewlett-Packard Development Company, L.P. | Wake settings |
| US12253966B2 (en) * | 2021-09-23 | 2025-03-18 | Intel Corporation | PCIe deterministic link training using OOB communications and enumeration optimization during different power-up states |
| US12164448B2 (en) * | 2022-08-22 | 2024-12-10 | Qualcomm Incorporated | Mechanism to reduce exit latency for deeper power saving modes L2 in PCIe |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107741780A (en) * | 2012-12-20 | 2018-02-27 | 英特尔公司 | Click on near-field communication (NFC) equipment for waking up and clicking on and log in |
| CN107957885A (en) * | 2017-12-01 | 2018-04-24 | 天津麒麟信息技术有限公司 | A kind of PCIE link devices based on platform of soaring are standby and restoration methods |
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Address after: 610096 Sichuan Province, Chengdu City, No. 399, West Section of Fucheng Avenue, Chengdu High-tech Development Zone, China (Sichuan) Free Trade Pilot Zone, Building 7, Unit 3, 14th Floor, Room 1409 Patentee after: Chengdu Xingtuo Microelectronics Technology Co.,Ltd. Country or region after: China Address before: No. 1409, 14th Floor, Unit 3, Building 7, No. 399 Fucheng Avenue West Section, High tech Zone, Chengdu City, Sichuan Province Patentee before: Chengdu CETC Xingtuo Technology Co.,Ltd. Country or region before: China |