CN118798123B

CN118798123B - Chip verification method and device, server and storage medium

Info

Publication number: CN118798123B
Application number: CN202411256327.5A
Authority: CN
Inventors: 郭龙成; 李元铖
Original assignee: Gechuang Communication Zhejiang Co ltd
Current assignee: Gechuang Communication Zhejiang Co ltd
Priority date: 2024-09-09
Filing date: 2024-09-09
Publication date: 2025-01-03
Anticipated expiration: 2044-09-09
Also published as: CN118798123A

Abstract

The embodiment of the application provides a chip verification method, a device, a server and a storage medium, which are applied to a first CPU core, wherein the method comprises the steps of obtaining a simulation task of chip verification, wherein the simulation task comprises a plurality of subtasks; and sending the plurality of subtasks to the corresponding second CPU cores so that each second CPU core executes the corresponding subtasks, and utilizing the underlying communication space to interact data generated in the execution process of the subtasks with other second CPU cores. The scheme can improve the chip verification efficiency and reduce the chip verification cost.

Description

Chip verification method and device, server and storage medium

Technical Field

The present application relates to the field of chip technologies, and in particular, to a chip verification method, device, server, and storage medium.

Background

Before the chip is subjected to streaming production, a special processor such as a server or a field programmable gate array (Field Programmable GATE ARRAY, FPGA) and a simulation (simulation) accelerator is required to be adopted to verify the chip, so that the function of the chip is ensured to meet the EDA design requirement, and the quality of the chip is ensured.

However, with the rapid development of artificial intelligence (ARTIFICIAL INTELLIGENCE, AI), the demand for data centers is growing, and the single chip scale, the chiplet (Chiplet) scale, and the chip networking scale applied to data centers are rapidly expanding. The chip verification is performed by the server, namely, the chip verification is actually performed by a central processing unit (Central Processing Unit, CPU) core in the server, and under the condition that the single chip scale, the small chip scale and the chip networking scale are increased, the chip verification is performed by a single CPU core, so that the verification efficiency is lower, and the verification cost is higher although the verification efficiency is higher by adopting a special processor to verify a large-scale single chip, small chip or chip networking.

Disclosure of Invention

The embodiment of the application aims to provide a chip verification method, a device, a server and a storage medium, so that chip verification efficiency is improved, and chip verification cost is reduced. The specific technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a chip verification method, applied to a first CPU core, where the method includes:

acquiring a simulation task of chip verification, wherein the simulation task comprises a plurality of subtasks;

Allocating idle second CPU cores for each subtask respectively, and creating a bottom communication space for the plurality of subtasks;

and sending the plurality of subtasks to the corresponding second CPU cores so that each second CPU core executes the corresponding subtask, and utilizing the bottom communication space to interact data generated in the execution process of the subtask with other second CPU cores.

In some embodiments, the method further comprises:

Continuously acquiring simulation time of a plurality of second CPU cores;

When the difference value of the simulation time of the third CPU core and the simulation time of the fourth CPU core is larger than or equal to a first preset duration, the third CPU core is instructed to stop executing the subtasks, wherein the third CPU core is any one of the plurality of second CPU cores, and the fourth CPU core is the second CPU core with the slowest simulation time in the plurality of second CPU cores;

and when the difference value of the simulation time of the third CPU core and the fourth CPU core is smaller than or equal to a second preset duration, indicating the third CPU core to resume executing the subtasks.

In some embodiments, the step of instructing the third CPU core to suspend executing the subtask when the difference between the simulation times of the third CPU core and the fourth CPU core is greater than or equal to a first preset duration includes:

And when the difference value of the simulation time of the third CPU core and the simulation time of the fourth CPU core is larger than or equal to a first preset duration and the simulation time of the third CPU core reaches a simulation period, indicating the third CPU core to suspend executing the subtasks.

In some embodiments, the second preset time period is zero;

and when the difference value of the simulation time between the third CPU core and the fourth CPU core is less than or equal to a second preset duration, indicating the third CPU core to resume executing the subtask, wherein the method comprises the following steps:

and when the simulation time of the fourth CPU core reaches a simulation period, indicating the third CPU core to resume executing the subtask.

In some embodiments, the step of creating an underlying communication space for the plurality of subtasks comprises:

determining two second CPU cores with data interaction according to the topological structures of the plurality of subtasks;

an underlying communication space is created for the two second CPU cores.

In some embodiments, the method further comprises:

Detecting each second CPU core to obtain the execution status of the subtask in each second CPU core;

and carrying out post-processing corresponding to the execution status on the subtasks in each CPU core.

In some embodiments, the underlying communication space is a shared file, a shared memory, or a Unix domain socket.

In some embodiments, the first CPU core is located on the same server as the plurality of second CPU cores.

In a second aspect, an embodiment of the present application provides a chip verification apparatus, applied to a first CPU core, including:

the first acquisition module is used for acquiring a simulation task for chip verification, wherein the simulation task comprises a plurality of subtasks;

The allocation module is used for allocating idle second CPU cores for each subtask respectively and creating a bottom communication space for the plurality of subtasks;

And the sending module is used for sending the plurality of subtasks to the corresponding second CPU cores so that each second CPU core executes the corresponding subtask and utilizing the bottom communication space to interact data generated in the execution process of the subtask with other second CPU cores.

In some embodiments, the apparatus further comprises:

the second acquisition module is used for continuously acquiring simulation time of a plurality of second CPU cores;

the system comprises an indication module, a third CPU core, a fourth CPU core and a third CPU core, wherein the indication module is used for indicating the third CPU core to suspend executing subtasks when the difference value of the simulation time of the third CPU core and the fourth CPU core is larger than or equal to a first preset time length, the third CPU core is any one of the second CPU cores, the fourth CPU core is the second CPU core with the slowest simulation time among the second CPU cores, and the indication module is used for indicating the third CPU core to resume executing subtasks when the difference value of the simulation time of the third CPU core and the fourth CPU core is smaller than or equal to a second preset time length.

In some embodiments, the indication module is specifically configured to:

In some embodiments, the second preset time period is zero;

the instruction module is specifically configured to instruct the third CPU core to resume executing the subtask when the simulation time of the fourth CPU core reaches a simulation period.

In some embodiments, the allocation module is specifically configured to:

an underlying communication space is created for the two second CPU cores.

In some embodiments, the apparatus further comprises:

The detection module is used for detecting each second CPU core to obtain the execution status of the subtask in each second CPU core;

And the processing module is used for carrying out post-processing corresponding to the execution status on the subtasks in each CPU core.

In a third aspect, an embodiment of the present application provides a server, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;

a memory for storing a computer program;

and the processor is used for realizing any one of the methods when executing the program stored in the memory.

In a fourth aspect, embodiments of the present application provide a computer readable storage medium having a computer program stored therein, which when executed by a processor, implements any of the methods described above.

In a fifth aspect, embodiments of the present application also provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform any of the methods described above.

The embodiment of the application has the beneficial effects that:

In the technical scheme provided by the embodiment of the application, the first CPU core splits the simulation task verified by one chip into a plurality of subtasks, and allocates an idle second CPU core for each subtask, and each second CPU core respectively executes the subtasks to realize that the plurality of second CPU cores execute the subtasks in parallel so as to complete the simulation task and improve the chip verification efficiency. In addition, in the embodiment of the application, the processing is completed by the CPU core on the server, and a special processor with high price is not needed, so that the cost of chip verification is reduced.

Of course, it is not necessary for any one product or method of practicing the application to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and other embodiments may be obtained according to these drawings to those skilled in the art.

FIG. 1 is a schematic diagram of a chip verification scenario;

fig. 2 is a schematic flow chart of a chip verification method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of shared file creation according to an embodiment of the present application;

fig. 4 is a first flowchart of a time synchronization method according to an embodiment of the present application;

fig. 5 is a second flowchart of a time synchronization method according to an embodiment of the present application;

FIG. 6 is a schematic diagram of time synchronization in a simulation task execution process according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a chipset network according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a topology of subtasks provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of an abstract model of a topology of a chipset network according to an embodiment of the present application;

Fig. 10 is a schematic diagram of a first structure of a chip verification device according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a second structure of a chip verification device according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by the person skilled in the art based on the present application are included in the scope of protection of the present application.

Authentication intellectual property (VIP) a set of pre-packaged codes for chip authentication.

The current chip verification method is realized based on a circuit design automation (Electronic Design Automation, EDA) tool, and mainly comprises the following two modes:

in the first mode, a server is adopted for chip verification.

As shown in the chip verification scenario of FIG. 1, a user writes a simulation task of chip verification on a client that submits the simulation task to a management server in a Load-sharing facility (Load SHARING FACILITY, LSF) cluster. The management server may send the simulation task to one of the execution servers in the LSF cluster in a load balancing manner. The execution server includes a plurality of CPU cores thereon. The execution server assigns the simulation task to an idle CPU core. The CPU core adopts EDA tools to construct a plurality of threads matched with simulation tasks, and simulates the circuit design of a chip or a chip network. And the computing resources among the threads coordinate to finish chip verification. The execution server executes the simulation task, and the management server is a server for managing the execution server.

In this manner, a single CPU core performs one simulation task. However, with the rapid development of AI technology, the single chip scale, the chiplet (Chiplet) scale, and the chipset network scale are rapidly expanding, and the data volume size of the corresponding simulation task is rapidly increasing. A single CPU core performs simulation tasks of large-scale chipset Verification (LCV), which would cause the CPU core to operate in overload, the CPU core to operate in a stuck state, the chip Verification efficiency is low, and even the chip Verification fails.

And in a second mode, a special processor is adopted for chip verification.

The user writes the simulation task of chip verification on the client, and the client submits the simulation task to a special processor such as an FPGA, a simulation accelerator and the like. The special processor adopts EDA tool to construct a plurality of threads matched with the simulation task, and simulates the circuit design of the chip or the chip network. And the computing resources among the threads coordinate to finish chip verification.

The special processor can meet the calculation resource requirement of the simulation task of the LCV, and the chip verification efficiency is higher. But the cost of the special purpose processor is higher and the cost of the special purpose processor may be higher to meet the computational resource requirements of the simulation task for larger data volume sizes.

In order to solve the above problems, while improving the chip verification efficiency and reducing the chip verification cost, an embodiment of the present application provides a chip verification method, as shown in fig. 2, applied to a first CPU core, the method including the steps of:

Step S201, a simulation task of chip verification is obtained, wherein the simulation task comprises a plurality of subtasks;

step S202, respectively allocating idle second CPU cores for each subtask, and creating a bottom communication space for a plurality of subtasks;

Step S203, a plurality of subtasks are sent to the corresponding second CPU cores, so that each second CPU core executes the corresponding subtask, and the data generated in the execution process of the subtask is interacted with other second CPU cores by using the bottom communication space.

The technical scheme provided by the embodiment of the application supports the verification of the large-scale chip networking of the second CPU core number. For example, the server has 144 CPU cores, and in theory, the embodiment of the application can realize networking verification of 144 chips.

In the embodiment of the present application, the first CPU core may be any CPU core in any server (such as the above-mentioned execution server) in the LSF cluster. The first CPU core is responsible for controlling and detecting each CPU core (such as the second CPU core) executing the simulation task.

In the step S201, the simulation task may be a simulation task for a single chip, or may be a simulation task for a large-scale chip networking. A simulation task includes a plurality of subtasks, one subtask forming a simulation test platform (Simulation Test Bench, sim TB) when running in the CPU core. When the simulation task is a simulation task for a single chip, the single chip is a tested object, and one subtask is a part of logic circuits which can independently run in the single chip. When the simulation task is directed at the simulation task of the large-scale chip network, the chip network is the object to be tested, and one subtask can be a part of logic circuits which can independently run in the single chip or can be an integral logic circuit of one chip in the chip network.

A user writes a simulation task for chip verification on a client, which submits the simulation task to a management server in the LSF cluster. The management server may send the simulation task to an execution server in the LSF cluster in a load balancing manner, so that a CPU core (e.g., a first CPU core) on the execution server acquires the simulation task.

In step S202, the first CPU core may select a plurality of CPU cores (e.g., second CPU cores) from the idle CPU cores, and allocate the selected second CPU cores to each subtask, where one subtask corresponds to one second CPU core, and the second CPU core is allocated to one subtask, which indicates that the second CPU core executes the subtask.

In the embodiment of the present application, the first CPU core and the plurality of second CPU cores may be located on the same server (such as the execution server described above). In this way, the first CPU can be facilitated to check the plurality of second CPU cores for control and detection. In addition, the plurality of second CPU cores are positioned on the same server, when the plurality of second CPU cores execute subtask interaction, the data receiving and transmitting time delay of the second CPU core interaction can be greatly shortened, the problem of unstable data transmission caused by large receiving and transmitting time delay is further solved, and stable data acquisition is obtained.

In the embodiment of the present application, the first CPU core and the plurality of second CPU cores may also be located on a plurality of servers, that is, the plurality of second CPU cores may be located on a plurality of servers. In order to solve the problem of unstable data transmission caused by large transceiving time delay, stable data acquisition is obtained, and the data transmission bandwidth between the plurality of servers is more than or equal to the bandwidth required by the interaction data between the second CPU cores.

When a second CPU core is allocated for a subtask, the first CPU core creates an underlying communication space for a plurality of subtasks. The bottom communication space is a medium for data generated in the execution process of the plurality of second CPU core interaction subtasks. In the embodiment of the application, the underlying communication space may be a shared file, a shared memory or a Unix domain socket. One or more underlying communication spaces may be established between two second CPU cores, and the underlying communication spaces between different second CPU cores may be the same or different.

In some embodiments, a first CPU core may acquire a topology of a plurality of subtasks, determine two second CPU cores for which there is data interaction based on the topology of the plurality of subtasks, and create an underlying communication space for the two second CPU cores. Through the topological structure of the plurality of subtasks, the first CPU core can accurately acquire two second CPU cores needing to establish the bottom communication space, and establish the corresponding bottom communication space.

In the embodiment of the application, a user can also input two second CPU cores needing to establish the bottom communication space through a user interaction interface, and the first CPU core acquires the information of establishing the bottom communication space input by the user through the user interface, so as to establish the corresponding bottom communication space. The first CPU core may also establish the underlying communication space in other ways, which is not limited.

The communication based on the bottom communication space of the server can avoid the large time delay caused by the data transmission of the local area network (Local Area Network, LAN), greatly reduce the data receiving and transmitting time delay of the interaction between the second CPU cores, and further solve the problem of unstable data transmission caused by the large receiving and transmitting time delay.

In step S203, the first CPU core transmits the plurality of subtasks to the corresponding second CPU core. After receiving the subtasks, the second CPU core may create a process and call the process to execute the received subtasks. The execution subtasks of the plurality of second CPU cores are mutually independent, so that the subtasks of the plurality of second CPU cores are executed in parallel, the maximum efficiency of parallel calculation of the plurality of CPU core resources in the server is further exerted, and the chip verification efficiency of the system level and the networking level is improved.

During execution of the subtasks, the second CPU core may write the generated data to the underlying communication space and read the required data from the underlying communication space by a process. Correspondingly, other second CPU cores can read the data written by the second CPU cores from the bottom communication space, and write the data required by the second CPU cores and generated in the process of executing the subtasks into the bottom communication space.

For example, the simulation tasks include subtask 1 through subtask 3. Subtask 1 is assigned CPU core 1, subtask 2 is assigned CPU core 2, and subtask 3 is assigned CPU core 3. The CPU core 1 executes the subtask 1 to form a simulation test platform Sim TB1, the CPU core 2 executes the subtask 2 to form a simulation test platform Sim TB2, and the CPU core 3 executes the subtask 3 to form a simulation test platform Sim TB3, as shown in fig. 3. The data interaction is required between the CPU core 1 and the CPU core 2, the data interaction is required between the CPU core 2 and the CPU core 3, that is, the data interaction is required between the Sim TB1 and the Sim TB2, the data interaction is required between the Sim TB2 and the Sim TB3, and further the shared file 1 and the shared file 2 are established between the CPU core 1 and the CPU core 2, and the shared file 3 and the shared file 4 are established between the CPU core 2 and the CPU core 3, as shown in fig. 3.

The method comprises the steps of writing data generated in the execution process of a subtask 1 into a shared file 1 by using a Sim TB1, reading data written by the Sim TB1 from the shared file 1 by using a Sim TB2, writing data generated in the execution process of the subtask 2 into the shared file 2 and the shared file 3 by using the Sim TB2, reading data written by the Sim TB2 from the shared file 2 by using the Sim TB1, reading data written by the Sim TB12 from the shared file 3 by using the Sim TB3, writing data generated in the execution process of the subtask 3 into the shared file 4 by using the Sim TB3, and reading data written by the Sim TB3 from the shared file 4 by using the Sim TB 2.

In the embodiment of the application, when the bottom communication space is created, if the plurality of second CPU cores and the first CPU core are positioned on the same server, the problem of unstable data transmission caused by large transceiving time delay can be further solved, the resource utilization rate of the plurality of CPU cores of the server is maximized, the EDA verification efficiency of the LSF cluster is fully exerted, the simulation efficiency of EDA verification is improved, and the verification cost of the large-scale chip networking is reduced as a whole.

In some embodiments, in order to reduce delay jitter and ensure long-time stability of data delay, the embodiment of the present application further provides a time synchronization method, as shown in fig. 4, applied to the first CPU core, which may include the following steps;

Step S401, continuously obtaining simulation time of a plurality of second CPU cores;

in the embodiment of the application, the simulation time is the time in one simulation Cycle (Cycle). For example, a simulation period may have a duration of 100 picoseconds (ps), and the simulation time may be any value between 0ps and 100 ps.

During execution of the subtasks by the plurality of second CPU cores, each of the second CPU cores may periodically send the emulation time to the first CPU core. The first CPU core continuously acquires simulation time of a plurality of second CPU cores.

In order to facilitate the first CPU core to acquire the simulation time of each second CPU core. An underlying communication space is established between the first CPU core and the plurality of second CPU cores. In this way, each second CPU core may periodically write the emulation time of that second CPU core into the underlying communication space, and the first CPU core may periodically read the emulation time of each second CPU core from the underlying communication space. The second CPU cores are different, and the bottom communication spaces for writing the simulation time can be the same or different.

Step S402, when the difference value of the simulation time of the third CPU core and the simulation time of the fourth CPU core is more than or equal to a first preset duration, the third CPU core is instructed to stop executing the subtasks;

The difference of the performances of the CPU cores and the difference of the sizes of the data volumes of the subtasks executed by the CPU cores lead to different efficiencies of processing the subtasks by different CPU cores, namely, under the same system time (CPU running time), the subtasks are executed by some second CPU cores faster, the subtasks are executed by some second CPU cores slower, correspondingly, the simulation time of different second CPU cores is different, and the phenomenon of different simulation time occurs.

After the first CPU core obtains the simulation time of a plurality of second CPU cores each time, the second CPU core with the slowest simulation time is determined from the plurality of second CPU cores and used as a fourth CPU core, and the simulation time of other second CPU cores (such as a third CPU core) is compared with the simulation time of the fourth CPU core.

If the difference value of the simulation time of the third CPU core and the simulation time of the fourth CPU core is greater than or equal to the first preset duration, the fact that the simulation time of the third CPU core is not synchronous with the simulation time of the fourth CPU core is indicated, and the first CPU core can instruct the third CPU core to pause executing subtasks so as to avoid the problem that data transmission between the CPU cores is unstable due to the fact that the simulation time is not synchronous. For example, the first CPU core writes a first control signal indicating suspension into the underlying communication space, and the third CPU core reads the first control signal from the underlying communication space, and then suspends execution of the subtasks according to the first control signal.

If the difference value of the simulation time of the third CPU core and the simulation time of the fourth CPU core is smaller than the first preset duration, the simulation time of the third CPU core and the simulation time of the fourth CPU core are synchronous, and the first CPU core can not perform any processing on the third CPU core, namely the third CPU core can continue to execute subtasks.

Step S403, when the difference between the simulation times of the third CPU core and the fourth CPU core is less than or equal to the second preset duration, indicating that the third CPU core resumes executing the subtasks.

In the embodiment of the present application, the second preset duration may be less than or equal to the first preset duration.

And during the period that the third CPU core pauses to execute the subtasks, the fourth CPU core continues to execute the subtasks, and the difference value of the simulation time of the third CPU core and the simulation time of the fourth CPU core are gradually reduced. During this period, the first CPU core continuously acquires the simulation time of the fourth CPU core, and compares the acquired simulation time of the fourth CPU core with the simulation time when the third CPU core pauses executing the subtasks. When the difference value of the simulation time of the third CPU core and the simulation time of the fourth CPU core is smaller than or equal to the second preset duration, the simulation time of the third CPU core and the simulation time of the fourth CPU core are synchronous, and the first CPU core indicates the third CPU core to resume executing the subtasks. For example, the first CPU core writes a second control signal indicating restoration into the underlying communication space, and the third CPU core reads the second control signal from the underlying communication space, and then resumes executing the subtask according to the second control signal.

If the difference between the simulation time of the third CPU core and the simulation time of the fourth CPU core are greater than the second preset duration, the first CPU core may not perform any processing on the third CPU core, i.e. the third CPU core may continue to suspend execution of the subtasks.

In order to avoid frequently suspending the execution of the subtasks by the third CPU core, the smoothness of task execution is affected, the second preset time length is smaller than the first preset time length, and the difference value between the first preset time length and the second preset time length is larger than or equal to the preset difference value. The preset difference value can be set according to actual requirements. The preset difference value may ensure that the third CPU core is not suspended from executing the subtasks again for a certain period of time.

In the embodiment of the application, the first CPU core compares the simulation time of the two CPU cores, pauses the CPU cores with faster simulation to execute the subtasks, realizes the time synchronization between the two CPU cores, and effectively solves the problems of larger time delay jitter and unstable data transmission caused by long-time simulation even if the CPU cores simulate for a long time to execute the subtasks and the time delay jitter of the simulation time of the two CPU cores is controlled within the first preset time length. The technical scheme provided by the embodiment of the application is suitable for a chipset verification scene with higher requirement on system time synchronization.

In some embodiments, the step S403 may be that when the difference between the simulation times of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration and the simulation time of the third CPU core reaches a simulation period, the third CPU core is instructed to suspend executing the subtasks.

In the embodiment of the present application, the first CPU core may instruct the third CPU core to suspend executing the subtasks in any one of the following manners.

In one mode, after the first CPU core obtains the simulation time of the plurality of second CPU cores each time, the simulation time of the third CPU core is compared with the simulation time of the fourth CPU core. If the difference value of the simulation time of the third CPU core and the simulation time of the fourth CPU core are greater than or equal to the first preset duration, the first CPU core does not immediately instruct the third CPU core to pause executing the subtasks. The third CPU core continues to execute the subtasks. When the simulation time of the third CPU core obtained by the first CPU core reaches a simulation period, the first CPU core instructs the third CPU core to pause executing the subtask.

The second mode is that the first CPU core obtains simulation time of a plurality of second CPU cores each time, whether the second CPU cores reaching one simulation period exist or not is determined, if yes, the second CPU cores reaching one simulation period are third CPU cores, and the first CPU cores compare the simulation time of the third CPU cores with the simulation time of the fourth CPU cores. If the difference value of the simulation time of the third CPU core and the simulation time of the fourth CPU core are larger than or equal to the first preset duration, the first CPU core immediately indicates the third CPU core to stop executing the subtasks.

In the embodiment of the present application, the first CPU core performs the time synchronization operation once at a specified time (the time when the simulation cycle is reached), that is, step S403 described above. This simplifies the complexity of the time synchronization operation and also allows the time synchronization to be controlled at the simulation Cycle (Cycle) level. The performance difference between the CPU cores is small, and the time synchronization of the Cycle level can be enough to ensure the stability of the Buffer (Buffer) waterline of the underlying communication space.

In some embodiments, to ensure time synchronization between CPU cores to the greatest extent and to reduce the frequency of performing synchronization operations, the second preset duration may be zero. In this case, the embodiment of the present application further provides a time synchronization method, as shown in fig. 5, applied to the first CPU core, which may include the following steps.

Step S501 is to continuously obtain the simulation time of the plurality of second CPU cores, and is the same as step S401, and will not be repeated here.

In step S502, when the difference between the simulation times of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration and the simulation time of the third CPU core reaches a simulation period, the third CPU core is instructed to suspend executing the subtasks, the third CPU core is any one of the plurality of second CPU cores, and the fourth CPU core is the second CPU core with the slowest simulation time among the plurality of second CPU cores, which is specifically described in step S402 and will not be repeated herein.

In step S503, when the simulation time of the fourth CPU core reaches a simulation period, the third CPU core is instructed to resume executing the subtask.

In the embodiment of the application, when the third CPU core pauses to execute the subtasks, the simulation time of the third CPU core reaches one simulation period. After the third CPU core pauses to execute the subtasks, the fourth CPU core continues to execute the subtasks, the simulation time of the fourth CPU core is continuously increased, and correspondingly, the difference value of the simulation time of the fourth CPU core and the third CPU core is continuously reduced. When the simulation time of the fourth CPU core reaches one simulation period, the difference value of the simulation time of the fourth CPU core and the simulation time of the third CPU core is 0, and then the first CPU core indicates the third CPU core to resume executing the subtasks.

In the embodiment of the present application, the first CPU core performs the time synchronization operation once at a specified time (the time when the simulation cycle is reached), that is, step S403 described above. This simplifies the complexity of the time synchronization operation and also allows the time synchronization to be controlled at the simulation Cycle (Cycle) level. The performance difference between the CPU cores is small, and the time synchronization of the Cycle level can be enough to ensure the stability of the Buffer (Buffer) waterline of the underlying communication space. In addition, when the difference value of the simulation time between the fourth CPU core and the third CPU core is 0, that is, when the difference value of the simulation time between the fourth CPU core and the third CPU core is minimum, the third CPU core resumes executing the subtasks, which ensures the time synchronization between the CPU cores to the greatest extent, prolongs the duration of the difference value of the simulation time between the fourth CPU core and the third CPU core after the synchronization operation, and further reduces the frequency of executing the synchronization operation.

For example, the simulation tasks include subtask 1 through subtask 3. Subtask 1 is assigned CPU core 1 (i.e., the second CPU core), subtask 2 is assigned CPU core 2 (i.e., the second CPU core), and subtask 3 is assigned CPU core 3 (i.e., the second CPU core). The CPU core 1 executes the subtask 1 to form a simulation test platform Sim TB1, the CPU core 2 executes the subtask 2 to form a simulation test platform Sim TB2, and the CPU core 3 executes the subtask 3 to form a simulation test platform Sim TB3, as shown in fig. 6. The CPU core 0 performs a time synchronization task as a time synchronization Manager (Manager). The efficiency of processing subtasks by the CPU cores 1 to 3 is different, the processing efficiency of the CPU core 2 is greater than the processing efficiency of the CPU core 3, the processing efficiency of the CPU core 3 is greater than the processing efficiency of the CPU core 1, and correspondingly, the simulation duration of one simulation period of the CPU cores 1 to 3 is the same, but the consumed running time of the CPU is different, and in fig. 6, one high level and one low level form one simulation period. Taking a simulation period of 100ps, a first preset duration of 0 and a second preset duration of 0 as examples. t0 to t3 are CPU running time.

The CPU cores 1-3 start to execute the subtasks from the time t0, and in the process of executing the subtasks by the CPU cores 1-3, the CPU cores 1-3 can send simulation time to the CPU core 0 at intervals of certain simulation time (such as 10 ps). At time t1, CPU core 0 acquires the simulation time of CPU core 2 as 100ps, and the simulation time of CPU core 1 and the simulation time of CPU core 3 are not 100ps, then CPU core 0 instructs CPU core 2 to suspend executing subtask 2, at time t2, CPU core 0 acquires the simulation time of CPU core 3 as 100ps, and the simulation time of CPU core 3 is not 100ps, then CPU core 0 instructs CPU core 3 to suspend executing subtask 3, at time t3, CPU core 0 acquires the simulation time of CPU core 1 as 100ps, CPU core 1 is the CPU core with the slowest simulation time, at this time, CPU core 0 instructs CPU core 2 to resume executing subtask 2, and CPU core 3 resumes executing subtask 3. And the same goes for the rest, and no further description is given.

By adopting the technical scheme provided by the embodiment of the application, for the condition that the same simulation period is adopted but the running time of the CPU is inconsistent, the execution of the subtasks in each CPU core is dynamically adjusted, so that the subtasks in all the CPU cores can jump consistently under the same clock, and the system time synchronization state is achieved.

In some embodiments, in order to improve accuracy and flexibility of the chip verification process, the first CPU core may monitor the plurality of second CPU cores, and specifically may include detecting each second CPU core to obtain an execution status of a subtask in each second CPU core, and performing post-processing corresponding to the execution status of the subtask in each CPU core.

The execution conditions may include, but are not limited to, execution exceptions, exception causes, operation need parameters, execution ends, and the like. The post-processing differs according to the execution status.

For example, the second CPU core sends information indicating an execution abnormality to the first CPU core, and the first CPU core generates abnormality prompt information and inputs the abnormality prompt information, so that a user can locate an abnormality cause in time, and the quality of a chip is improved.

For another example, the first CPU core detects that the subtask executed by the second CPU core needs to increase the operation requirement parameter, and the first CPU core acquires the operation requirement parameter and writes the operation requirement parameter into the subtask executed by the second CPU core, so as to ensure execution of the subtask.

Through the monitoring to the second CPU core, the first CPU core can timely adjust the chip verification flow according to actual demands, and the flexibility of chip verification is improved.

The chip verification method provided by the embodiment of the application is described in detail below with reference to the chip networking shown in fig. 7. The chipset network shown in fig. 7 includes 22 chips, 6 switch cards and 16 line cards, respectively. The 16 line cards are divided into 8 groups, and each line card is connected to one AI card, which can communicate with the switch card through the line cards. The description will be given taking the underlying communication space as a shared file.

For the topology of the chipset network shown in fig. 7, the topology of the subtasks corresponding to the topology is shown in fig. 8. The verification Environments (ENVs) 1-ENV 1-6 correspond to 6 switch cards, and ENVs 2-1-ENV 2-16 correspond to 16 line cards. ENV 1-ENV 1-6, ENV 2-1-ENV 2-16 are subtasks for chipset network verification shown in fig. 7, respectively. Each AI card is abstracted to VIP.

The CPU core 0 on the server 1 acquires the topology of the chipset network shown in fig. 7, creating a process including a time synchronization thread, a control and inspection thread. Wherein the time synchronization thread, the control and the inspection thread can be regarded as a subtask, respectively. The control and inspection thread gives 22 sub-tasks of ENV1-1 to ENV1-6 and ENV2-1 to ENV2-16 to 22 idle CPU cores, such as CPU cores 1 to 22, on the server 1. The 22 CPU cores respectively create processes corresponding to the subtasks, and the CPU cores call the processes to execute the received subtasks.

In addition, the control and inspection threads create shared files for subtasks that need to interact with data according to the topology shown in FIG. 8. In fig. 8, the connection between the subtasks indicates that the subtasks need to communicate with each other to exchange data, and then the connection between the subtasks needs to communicate with each subtask in combination with the time synchronization thread to realize time synchronization, and the topology structure of the chipset network can be abstracted into the model shown in fig. 9. In fig. 9, the control and inspection thread may inspect and control execution of sub-tasks, such as creating shared files, etc., based on the corresponding messages.

The CPU core 1-22 sends the simulation time to the time synchronization thread through the shared file in the process of calling the process to execute the subtasks.

And when the simulation time of the slowest CPU core reaches one simulation period, restoring the process in the CPU core with the faster simulation time so as to continue executing the subtasks. Thus, the process of 22 CPU cores is consistent and jumped under the same system clock, and the system time synchronization is achieved.

In the embodiment of the application, 22 CPU cores execute 22 subtasks in parallel, the verification of the chip network composed of 22 chips is completed, the chip verification efficiency of EDA simulation is improved, and an expensive special processor is not needed, so that the verification cost of the large-scale chip network is reduced as a whole.

Corresponding to the above-mentioned chip verification method, the embodiment of the present application further provides a chip verification device, as shown in fig. 10, applied to the first CPU core, where the device includes:

a first obtaining module 1001, configured to obtain a simulation task for chip verification, where the simulation task includes a plurality of subtasks;

an allocation module 1002, configured to allocate an idle second CPU core for each sub-task, and create a bottom communication space for a plurality of sub-tasks;

And the sending module 1003 is configured to send the plurality of subtasks to the corresponding second CPU cores, so that each second CPU core executes the corresponding subtasks, and interact data generated in the execution process of the subtasks with other second CPU cores by using the bottom communication space.

In some embodiments, as shown in fig. 11, the chip verification device may further include:

A second obtaining module 1101, configured to continuously obtain simulation times of the plurality of second CPU cores;

The instruction module 1102 is configured to instruct the third CPU core to suspend executing the subtask when a difference between simulation times of the third CPU core and the fourth CPU core is greater than or equal to a first preset duration, the third CPU core is any one of the plurality of second CPU cores, the fourth CPU core is a second CPU core with a slowest simulation time among the plurality of second CPU cores, and instruct the third CPU core to resume executing the subtask when the difference between simulation times of the third CPU core and the fourth CPU core is less than or equal to the second preset duration.

In some embodiments, the indication module 1102 may be specifically configured to:

And when the difference value of the simulation time of the third CPU core and the simulation time of the fourth CPU core is larger than or equal to the first preset duration and the simulation time of the third CPU core reaches a simulation period, indicating the third CPU core to pause executing the subtasks.

In some embodiments, the second preset time period is zero;

the instruction module 1102 may be specifically configured to instruct the third CPU core to resume executing the subtask when the simulation time of the fourth CPU core reaches a simulation period.

In some embodiments, the allocation module 1002 may be specifically configured to:

an underlying communication space is created for the two second CPU cores.

In some embodiments, the chip verification apparatus may further include:

In some embodiments, the underlying communication space is a shared file, shared memory, or Unix domain socket.

Corresponding to the above chip verification method, the embodiment of the present application further provides an electronic device, as shown in fig. 12, which includes a processor 1201, a communication interface 1202, a memory 1203, and a communication bus 1204, where the processor 1201, the communication interface 1202, and the memory 1203 complete communication with each other through the communication bus 1204.

A memory 1203 for storing a computer program;

the processor 1201, when executing the program stored in the memory 1203, performs the following steps:

The communication bus mentioned above for the electronic device may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, etc. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.

The communication interface is used for communication between the electronic device and other devices.

The Memory may include random access Memory (Random Access Memory, RAM) or may include Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.

The Processor may be a general-purpose Processor including a central processing unit (Central Processing Unit, CPU), a network Processor (Network Processor, NP), etc., or may be a digital signal Processor (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components.

In yet another embodiment of the present application, there is also provided a computer readable storage medium having stored therein a computer program which, when executed by a processor, implements the steps of any of the chip authentication methods described above.

In yet another embodiment of the present application, there is also provided a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the chip authentication methods of the above embodiments.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk Solid STATE DISK (SSD)), etc.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for chip authentication apparatus, electronic devices, storage media and program product embodiments, the description is relatively simple as it is substantially similar to the method embodiments, as relevant see the section description of the method embodiments.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A chip verification method, characterized in that it is applied to a first CPU core, and the method comprises:

Acquire a simulation task for chip verification, wherein the simulation task includes multiple subtasks;

Allocate an idle second CPU core to each subtask respectively, and create an underlying communication space for the multiple subtasks;

Sending the multiple subtasks to corresponding second CPU cores so that each second CPU core executes the corresponding subtask, and using the underlying communication space to interact with other second CPU cores for data generated during the execution of the subtasks;

Continuously obtain the simulation time of multiple second CPU cores;

When the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration, instructing the third CPU core to suspend execution of the subtask; the third CPU core is any second CPU core among the multiple second CPU cores, and the fourth CPU core is the second CPU core with the slowest simulation time among the multiple second CPU cores;

When the difference between the simulation time of the third CPU core and the simulation time of the fourth CPU core is less than or equal to a second preset duration, the third CPU core is instructed to resume executing the subtask.

2. The method according to claim 1, characterized in that when the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to a first preset duration, the step of instructing the third CPU core to suspend execution of the subtask comprises:

When the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to the first preset duration, and the simulation time of the third CPU core reaches one simulation cycle, the third CPU core is instructed to suspend execution of the subtask.

3. The method according to claim 2, characterized in that the second preset duration is zero;

The step of instructing the third CPU core to resume executing the subtask when the difference between the simulation time of the third CPU core and the fourth CPU core is less than or equal to the second preset duration includes:

When the simulation time of the fourth CPU core reaches one simulation cycle, the third CPU core is instructed to resume executing the subtask.

4. The method according to claim 1, characterized in that the step of creating an underlying communication space for the plurality of subtasks comprises:

Determine, according to the topological structure of the multiple subtasks, two second CPU cores with which data interaction exists;

An underlying communication space is created for the two second CPU cores.

5. The method according to any one of claims 1 to 4, characterized in that the method further comprises:

Detect each second CPU core to obtain the execution status of the subtask in each second CPU core;

The subtasks in each CPU core are subjected to post-processing corresponding to the execution status.

6. The method according to any one of claims 1 to 4, characterized in that the underlying communication space is a shared file, a shared memory or a Unix domain socket.

7. The method according to any one of claims 1 to 4, characterized in that the first CPU core and the plurality of second CPU cores are located on the same server.

8. A chip verification device, characterized in that it is applied to a first CPU core, and the device comprises:

A first acquisition module is used to acquire a simulation task for chip verification, wherein the simulation task includes multiple subtasks;

An allocation module, used for respectively allocating an idle second CPU core to each subtask and creating an underlying communication space for the multiple subtasks;

A sending module, used to send the multiple subtasks to the corresponding second CPU cores, so that each second CPU core executes the corresponding subtask, and to interact with other second CPU cores using the underlying communication space to generate data during the execution of the subtasks;

A second acquisition module, used for continuously acquiring simulation time of multiple second CPU cores;

An indication module is used to instruct the third CPU core to suspend execution of a subtask when the difference between the simulation time of the third CPU core and the fourth CPU core is greater than or equal to a first preset duration; the third CPU core is any second CPU core among the multiple second CPU cores, and the fourth CPU core is the second CPU core with the slowest simulation time among the multiple second CPU cores; when the difference between the simulation time of the third CPU core and the fourth CPU core is less than or equal to a second preset duration, instruct the third CPU core to resume execution of the subtask.

9. The device according to claim 8, characterized in that the indication module is specifically used for:

10. The device according to claim 9, wherein the second preset duration is zero;

The instructing module is specifically used to instruct the third CPU core to resume executing the subtask when the simulation time of the fourth CPU core reaches one simulation cycle.

11. The device according to claim 8, characterized in that the allocation module is specifically used to:

An underlying communication space is created for the two second CPU cores.

12. The device according to any one of claims 8 to 11, characterized in that the device further comprises:

A detection module, used to detect each second CPU core to obtain the execution status of the subtask in each second CPU core;

The processing module is used to perform post-processing corresponding to the execution status on the subtasks in each CPU core.

13. The device according to any one of claims 8 to 11, characterized in that the underlying communication space is a shared file, a shared memory or a Unix domain socket.

14. The device according to any one of claims 8 to 11, characterized in that the first CPU core and the plurality of second CPU cores are located on the same server.

15. A server, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

Memory, used to store computer programs;

A processor, for implementing any of the methods described in claims 1-7 when executing a program stored in a memory.

16. A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.