CN118821675A - Chip verification method, device, equipment and medium - Google Patents

Abstract

The present disclosure provides a chip verification method and apparatus, device and medium, which relate to the field of computer technology, and in particular to the field of chip technology. The implementation scheme is: obtaining an initial instruction corresponding to each processing core in a plurality of processing cores, each initial instruction depends on at least one other initial instruction; based on a first dependency relationship between a plurality of initial instructions corresponding to the plurality of processing cores, determining a second dependency relationship between the plurality of processing cores; based on the second dependency relationship, determining at least one first dependent core that depends on the first processing core; determining a first newly added instruction for the first processing core from a plurality of candidate instructions, wherein the first newly added instruction does not depend on the initial instruction corresponding to at least one first dependent core; executing the plurality of initial instructions and the first newly added instruction using a chip; and determining a verification result for the chip based on the execution results of the plurality of initial instructions and the first newly added instruction.

Description

Chip verification method, device, equipment and medium

Technical Field

The present disclosure relates to the field of computer technology, in particular to the field of chip technology, and specifically to a chip verification method, device, electronic device, computer-readable storage medium, and computer program product.

Background Art

Artificial intelligence is a discipline that studies how to use computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.). It includes both hardware-level and software-level technologies. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, and big data processing; artificial intelligence software technologies mainly include computer vision technology, speech recognition technology, natural language processing technology, as well as machine learning/deep learning, big data processing technology, knowledge graph technology, and other major directions.

In order to adapt to the development of artificial intelligence technology, the chip scale and process used to execute artificial intelligence-based algorithms need to be further improved, and more accurate and efficient chip verification technology needs to be applied.

The methods described in this section are not necessarily methods that have been previously conceived or employed. Unless otherwise indicated, it should not be assumed that any method described in this section is considered to be prior art simply because it is included in this section. Similarly, unless otherwise indicated, the issues mentioned in this section should not be considered to have been recognized in any prior art.

Summary of the invention

The present disclosure provides a chip verification method, device, electronic device, computer-readable storage medium and computer program product.

According to one aspect of the present disclosure, a chip verification method is provided, wherein the chip includes multiple processing cores, and the method includes: for each processing core among the multiple processing cores, obtaining an initial instruction corresponding to the processing core, wherein each of the multiple initial instructions corresponding to the multiple processing cores depends on at least one other initial instruction among the multiple initial instructions; based on a first dependency relationship between the multiple initial instructions corresponding to the multiple processing cores, determining a second dependency relationship between the multiple processing cores; based on the second dependency relationship, determining at least one first dependent core that depends on the first processing core from the multiple processing cores; determining a first newly added instruction for the first processing core from multiple candidate instructions, wherein the first newly added instruction does not depend on the initial instruction corresponding to the at least one first dependent core; executing the multiple initial instructions and the first newly added instruction using the chip; and determining a verification result for the chip based on the execution results of the multiple initial instructions and the first newly added instruction.

According to another aspect of the present disclosure, a chip verification device is provided, wherein the chip includes multiple processing cores, and the device includes: an acquisition unit, configured to acquire, for each processing core among the multiple processing cores, an initial instruction corresponding to the processing core, wherein each of the multiple initial instructions corresponding to the multiple processing cores depends on at least one other initial instruction among the multiple initial instructions; a first determination unit, configured to determine a second dependency relationship between the multiple processing cores based on a first dependency relationship between the multiple initial instructions corresponding to the multiple processing cores; a second determination unit, configured to determine at least one first dependent core that depends on the first processing core from the multiple processing cores based on the second dependency relationship; a third determination unit, configured to determine a first newly added instruction for the first processing core from a plurality of candidate instructions, wherein the first newly added instruction does not depend on the initial instruction corresponding to the at least one first dependent core; an execution unit, configured to execute the multiple initial instructions and the first newly added instruction using the chip; and a verification unit, configured to determine a verification result for the chip based on the execution results of the multiple initial instructions and the first newly added instruction.

According to another aspect of the present disclosure, a chip is provided, comprising the chip verification device as described above.

According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned chip verification method.

According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the above chip verification method.

According to another aspect of the present disclosure, a computer program product is provided, including a computer program, wherein the computer program can implement the above chip verification method when executed by a processor.

According to one or more embodiments of the present disclosure, the efficiency and convenience of chip verification can be improved while ensuring the chip verification effect.

It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings exemplarily illustrate the embodiments and constitute a part of the specification, and together with the text description of the specification, are used to explain the exemplary implementation of the embodiments. The embodiments shown are for illustrative purposes only and do not limit the scope of the claims. In all drawings, the same reference numerals refer to similar but not necessarily identical elements.

FIG1 shows a schematic diagram of an exemplary system in which various methods described herein may be implemented according to an exemplary embodiment of the present disclosure;

FIG2 shows a flow chart of a chip verification method according to an exemplary embodiment of the present disclosure;

FIG. 3 is a schematic diagram showing multiple search trees according to an exemplary embodiment of the present disclosure.

FIG4 shows a block diagram of a chip verification device according to an exemplary embodiment of the present disclosure;

FIG. 5 shows a structural block diagram of an exemplary electronic device that can be used to implement an embodiment of the present disclosure.

DETAILED DESCRIPTION

The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

In the present disclosure, unless otherwise specified, the use of the terms "first", "second", etc. to describe various elements is not intended to limit the positional relationship, timing relationship, or importance relationship of these elements, and such terms are only used to distinguish one element from another element. In some examples, the first element and the second element may refer to the same instance of the element, and in some cases, based on the description of the context, they may also refer to different instances.

The terms used in the description of various examples in this disclosure are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element can be one or more. In addition, the term "and/or" used in this disclosure covers any one of the listed items and all possible combinations.

In actual application scenarios, the chip's instruction set to be verified usually contains a large number of instructions, that is, corresponding to a variety of different chip functions, or corresponding to different parameters under the same functional mode, such as data processing of different data sizes. Understandably, the cost of traversing the chip's instruction set to be verified is high, and it is difficult to achieve complete verification. Therefore, it is usually necessary to execute specific random configuration instructions to continuously randomly select target instructions from the instruction set to be verified to form a random instruction stream, so that the random instruction stream can be executed by the chip to be verified, and the verification result of the chip can be determined based on the execution result of the random instruction stream. It should be understood that when verifying a chip, the more chip functions are verified, that is, the higher the randomness of the random instruction stream, the more comprehensive and reliable the verification result obtained.

However, when a chip contains multiple processing cores, there are usually many constraints between the instructions corresponding to the multiple processing cores. In this case, when an instruction of a processing core depends on another instruction of the processing core, a dependency deadlock will occur, causing the instruction stream to fail to execute normally. In related technologies, the randomness of the verification instruction set is usually reduced to avoid the probability of dependency deadlock, but this method will affect the effect of chip verification.

Based on this, the present invention provides a chip verification method, which determines the dependency between processing cores based on the dependency between existing initial instructions. When generating new instructions for a certain processing core, the new instructions are determined based on the constraint principle that the new instructions do not depend on the initial instructions of the processing core itself. This can effectively avoid dependency deadlock between multiple processing cores, thereby improving verification efficiency while ensuring the verification effect.

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

FIG1 shows a schematic diagram of an exemplary system 100 in which various methods and apparatuses described herein may be implemented according to an embodiment of the present disclosure. Referring to FIG1 , the system 100 includes one or more client devices 101, 102, 103, 104, 105, and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. The client devices 101, 102, 103, 104, 105, and 106 may be configured to execute one or more applications.

In an embodiment of the present disclosure, the server 120 may run one or more services or software applications that enable the chip authentication method to be performed.

In some embodiments, server 120 may also provide other services or software applications, which may include non-virtualized environments and virtualized environments. In some embodiments, these services may be provided as web-based services or cloud services, such as provided to users of client devices 101, 102, 103, 104, 105, and/or 106 under a software as a service (SaaS) model.

In the configuration shown in FIG. 1 , server 120 may include one or more components that implement the functions performed by server 120. These components may include software components, hardware components, or a combination thereof that can be executed by one or more processors. Users operating client devices 101, 102, 103, 104, 105, and/or 106 may in turn utilize one or more client applications to interact with server 120 to utilize the services provided by these components. It should be understood that a variety of different system configurations are possible, which may be different from system 100. Therefore, FIG. 1 is an example of a system for implementing the various methods described herein and is not intended to be limiting.

The user may use client devices 101, 102, 103, 104, 105 and/or 106 to send initial instructions. The client device may provide an interface that enables a user of the client device to interact with the client device. The client device may also output information to the user via the interface. Although FIG. 1 depicts only six client devices, those skilled in the art will appreciate that the present disclosure may support any number of client devices.

Client devices 101, 102, 103, 104, 105 and/or 106 may include various categories of computer devices, such as portable handheld devices, general-purpose computers (such as personal computers and laptop computers), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, game systems, thin clients, various messaging devices, sensors or other sensing devices, etc. These computer devices may run various categories and versions of software applications and operating systems, such as MICROSOFT Windows, APPLE iOS, UNIX-like operating systems, Linux or Linux-like operating systems (such as GOOGLE Chrome OS); or include various mobile operating systems, such as MICROSOFT Windows Mobile OS, iOS, Windows Phone, Android. Portable handheld devices may include cellular phones, smart phones, tablet computers, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays (such as smart glasses) and other devices. Game systems may include various handheld game devices, Internet-enabled game devices, etc. The client device is capable of executing a variety of different applications, such as various Internet-related applications, communication applications (eg, email applications), short message service (SMS) applications, and may use various communication protocols.

The network 110 may be any type of network known to those skilled in the art that may support data communications using any of a variety of available protocols, including but not limited to TCP/IP, SNA, IPX, etc. By way of example only, one or more networks 110 may be a local area network (LAN), an Ethernet-based network, a token ring, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a blockchain network, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, WIFI), and/or any combination of these and/or other networks.

Server 120 may include one or more general purpose computers, dedicated server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and/or combination. Server 120 may include one or more virtual machines running virtual operating systems, or other computing architectures involving virtualization (e.g., one or more flexible pools of logical storage devices that may be virtualized to maintain a server's virtual storage device). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.

The computing units in the server 120 may run one or more operating systems including any of the above operating systems and any commercially available server operating systems. The server 120 may also run any of a variety of additional server applications and/or middle-tier applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

In some implementations, server 120 may include one or more applications to analyze and consolidate data feeds and/or event updates received from users of client devices 101, 102, 103, 104, 105, and 106. Server 120 may also include one or more applications to display data feeds and/or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105, and 106.

In some embodiments, the server 120 may be a server of a distributed system, or a server combined with a blockchain. The server 120 may also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. A cloud server is a host product in a cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and virtual private servers (VPS) services.

The system 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data and other information. For example, one or more of the databases 130 may be used to store information such as audio files and video files. The databases 130 may reside in various locations. For example, the database used by the server 120 may be local to the server 120, or may be remote from the server 120 and may communicate with the server 120 via a network-based or dedicated connection. The databases 130 may be of different categories. In some embodiments, the databases used by the server 120 may be, for example, relational databases. One or more of these databases may store, update, and retrieve data to and from the databases in response to commands.

In some embodiments, one or more of the databases 130 may also be used by applications to store application data. The databases used by the applications may be different categories of databases, such as a key-value store, an object store, or a conventional store backed by a file system.

The system 100 of FIG. 1 may be configured and operated in various ways to enable application of various methods and apparatuses described according to the present disclosure.

FIG2 shows a flow chart of a chip verification method 200 according to an exemplary embodiment of the present disclosure, wherein the chip includes multiple processing cores. As shown in FIG2 , the method 200 includes:

Step S201: for each processing core among the multiple processing cores, obtain an initial instruction corresponding to the processing core, wherein each initial instruction among the multiple initial instructions corresponding to the multiple processing cores depends on at least one other initial instruction among the multiple initial instructions;

Step S202, determining a second dependency relationship between the plurality of processing cores based on a first dependency relationship between a plurality of initial instructions corresponding to the plurality of processing cores;

Step S203: Based on the second dependency relationship, determine at least one first dependent core that is dependent on the first processing core from the multiple processing cores;

Step S204, determining a first newly added instruction for the first processing core from a plurality of candidate instructions, wherein the first newly added instruction does not depend on an initial instruction corresponding to the at least one first dependent core;

Step S205: using the chip to execute the multiple initial instructions and the first newly added instruction; and

Step S206: Determine a verification result for the chip based on the execution results of the multiple initial instructions and the first newly added instruction.

Therefore, the dependency between processing cores can be determined based on the dependency between existing initial instructions. When new instructions are generated for a certain processing core, the new instructions are determined based on the constraint principle that the new instructions do not depend on the initial instructions of the processing core itself. This can effectively avoid dependency deadlock between multiple processing cores, thereby improving verification efficiency while ensuring verification results.

In some examples, the first newly added instruction can be obtained by randomly selecting from a plurality of candidate instructions and then checking whether they satisfy the above-mentioned constraint rules, thereby achieving complete randomness within the legal space and improving the effect of chip verification.

In some examples, the initial instructions of each of the multiple processing cores can be configured in advance by relevant personnel according to verification requirements, and the dependencies between the initial instructions can be configured at the same time. It can be understood that each processing core can correspond to multiple initial instructions. In this case, the second dependency between the processing cores can be determined by traversing the first dependency between the instructions corresponding to each of the multiple initial instructions.

In some examples, the chip to be verified can be various types of chips, especially data processing chips, such as chips for executing deep learning algorithms, voice processing chips, image processing chips, etc.

In some examples, multiple candidate instructions can be extracted and configured by relevant personnel according to verification requirements. The initial instructions and candidate instructions can be data processing instructions, data transmission instructions, data read and write instructions, etc., to ensure that the chip to be verified can normally perform data processing, data transmission, data read and write and other functions.

In some examples, the first processing core may be any one of a plurality of processing cores. After determining the first newly added instruction for the first processing core, corresponding steps may be repeatedly performed for other processing cores to achieve comprehensive verification of the multi-core chip.

According to some embodiments, the method 200 further includes: in response to determining that the first newly added instruction depends on a third instruction among the multiple initial instructions, updating the second dependency relationship based on the third dependency relationship between the first newly added instruction and the third instruction; determining at least one second dependent core that depends on the second processing core from the multiple processing cores based on the updated second dependency relationship; and determining a second newly added instruction for the second processing core from the multiple candidate instructions, wherein the target instruction does not depend on the instruction corresponding to the at least one second dependent core, and wherein, in step S205, using the chip to execute the multiple initial instructions and the first newly added instruction includes: using the chip to execute the multiple initial instructions, the first newly added instruction, and the second newly added instruction, and in step S206, determining the verification result for the chip based on the execution results of the multiple initial instructions and the first newly added instruction includes: determining the verification result for the chip based on the execution results of the multiple initial instructions, the first newly added instruction, and the second newly added instruction. Thus, the dependency relationship between the processing cores can be updated based on the first newly added instruction, and then the newly added instructions for other processing cores can be determined based on the updated dependency relationship between the processing cores, and the verification instruction set for the multi-core processor can be obtained by analogy, thereby improving the verification effect.

In some examples, the execution of the multiple initial instructions and each newly added instruction by the chip in step S205 can be implemented in a software or hardware-based manner. For example, hardware description languages such as Verilog, VHDL (Veri-High-Speed Integrate Circuit Hardware Description Language, ultra-high-speed integrated circuit hardware description language) can be used in a software environment to design and configure the chip circuit, and after compiling and generating chip circuit netlist information that can be used for simulation, the simulation verification of the chip circuit is performed based on this. In some examples, the RTL (Register Transfer Level) code of the chip circuit to be verified can be obtained in the software environment to describe the data flow of the chip circuit, thereby realizing the RTL simulation for the chip. In some examples, other languages (such as C language) can also be used to write and generate the corresponding code of the hardware description language, thereby obtaining the chip circuit netlist information that can be used for simulation. For another example, the corresponding hardware circuit can also be implemented according to the hardware description language or circuit netlist information, and the hardware circuit can be verified.

In some examples, when the chip to be verified is a data processing chip, the verification result for the chip is determined based on the execution results of the multiple initial instructions and each newly added instruction in step S206, which can be achieved by using the following steps: after obtaining multiple initial instructions and each newly added instruction by executing steps S201-S205, the input data and the target output data corresponding to the input data are determined based on the multiple initial instructions and each newly added instruction; the multiple initial instructions and each newly added instruction are executed by the chip to be verified to realize data processing based on the input data, so as to obtain the output data to be verified output by the chip; and the verification result for the chip is determined based on the target output data and the output data to be verified. In some examples, a model capable of realizing the corresponding data processing function can be written by using a computer program, and the target output data is obtained by using the model. Thus, the target output data can be used to indicate whether the output data to be verified is accurate, thereby obtaining the verification result for the chip to be verified.

According to some embodiments, determining the second dependency relationship between the multiple processing cores based on the first dependency relationship between the multiple initial instructions corresponding to the multiple processing cores includes: establishing multiple search trees with the multiple processing cores as root nodes based on the first dependency relationship between the multiple initial instructions corresponding to the multiple processing cores, wherein there is a dependency relationship between the processing cores corresponding to any two adjacent nodes in the multiple search trees, and wherein determining the first new instruction for the first processing core from multiple candidate instructions includes: in response to determining that a first candidate instruction among the multiple candidate instructions depends on a second dependent instruction among the multiple initial instructions, based on the first dependency relationship between the first candidate instruction and the second dependent instruction, determining the new node for the multiple search trees; traversing the multiple search trees including the new node using a tree search algorithm; and in response to determining that each leaf node in the multiple search trees including the new node is different from the root node corresponding to the leaf node, determining the first candidate instruction as the first new instruction. In this way, the dependency relationship between multiple cores can be abstracted into multiple search trees, and a tree search algorithm can be executed to determine whether the first new instruction for the first processing core depends on the initial instruction of the first processing core itself, thereby conveniently and effectively avoiding dependency deadlock, improving instruction generation efficiency, and further improving chip verification efficiency.

According to some embodiments, the tree search algorithm includes a depth-first tree search algorithm. As described above, the first newly added instruction can be obtained by randomly selecting from a plurality of candidate instructions and then checking whether they satisfy the above-mentioned constraint rules. By executing the depth-first tree search algorithm, each branch in the search tree can be quickly checked. When it is determined that a candidate instruction does not satisfy the above-mentioned constraint rules, the check is promptly terminated and other candidate instructions are selected to improve the instruction generation efficiency.

In some examples, the tree search algorithm may also include a breadth-first tree search algorithm. Thus, it is also possible to effectively check whether each leaf node in a plurality of search trees is the same as the root node corresponding to the leaf node, so as to avoid dependency deadlock between processing cores and improve chip verification efficiency.

According to some embodiments, method 200 further includes: in response to determining that the first candidate instruction is the first newly added instruction, updating the multiple search trees based on the newly added nodes; and determining the third newly added instruction for the third processing core from the multiple candidate instructions based on the updated multiple search trees. Thus, after determining the first newly added instruction, the search tree including the corresponding newly added node can be easily and efficiently determined as the updated search tree, and the updated search tree can be used to indicate the second dependency relationship between the multiple processing cores at the current moment, so as to further determine the newly added instructions for other processing cores and improve the verification efficiency.

FIG3 shows a schematic diagram of multiple search trees according to an exemplary embodiment of the present disclosure. As shown in FIG3, in this example, the chip to be verified includes processing core A, processing core B, processing core C, processing core D, and processing core E, so that a search tree with A, B, C, D, and E as root nodes can be obtained. By abstracting the dependency relationship between multiple processing cores into multiple search trees, it is possible to determine whether the newly added instructions for each processing core are dependent on the processing core itself by executing a tree search algorithm, thereby being able to conveniently and effectively avoid dependency deadlock, improve instruction generation efficiency, and thus improve chip verification efficiency.

According to another aspect of the present disclosure, a chip verification device is also provided. FIG. 4 shows a block diagram of a chip verification device 400 according to an exemplary embodiment of the present disclosure, wherein the chip includes multiple processing cores. As shown in FIG. 4 , the device 400 includes:

The acquisition unit 401 is configured to acquire, for each processing core among the plurality of processing cores, an initial instruction corresponding to the processing core, wherein each initial instruction among the plurality of initial instructions corresponding to the plurality of processing cores depends on at least one other initial instruction among the plurality of initial instructions;

A first determining unit 402 is configured to determine a second dependency relationship between the plurality of processing cores based on a first dependency relationship between a plurality of initial instructions corresponding to the plurality of processing cores;

A second determining unit 403 is configured to determine at least one first dependent core that is dependent on the first processing core from the plurality of processing cores based on the second dependency relationship;

A third determining unit 404 is configured to determine a first newly added instruction for the first processing core from a plurality of candidate instructions, wherein the first newly added instruction does not depend on an initial instruction corresponding to the at least one first dependent core;

An execution unit 405 is configured to execute the plurality of initial instructions and the first newly added instruction using the chip;

The verification unit 406 is configured to determine a verification result for the chip based on the execution results of the multiple initial instructions and the first newly added instruction.

According to some embodiments, the device 400 also includes: a first update unit, configured to update the second dependency relationship based on the third dependency relationship between the first newly added instruction and the third instruction in response to determining that the first newly added instruction depends on the third instruction among the multiple initial instructions, and wherein the second determination unit 403 is also configured to determine at least one second dependent core that depends on the second processing core from the multiple processing cores based on the updated second dependency relationship, and the third determination unit 404 is also configured to determine the second newly added instruction for the second processing core from the multiple candidate instructions, wherein the target instruction does not depend on the instruction corresponding to the at least one second dependent core, the execution unit 405 is configured to use the chip to execute the multiple initial instructions, the first newly added instruction and the second newly added instruction, and the verification unit 406 is configured to determine the verification result for the chip based on the execution results of the multiple initial instructions, the first newly added instruction and the second newly added instruction.

According to some embodiments, the second determination unit 403 is configured to: establish multiple search trees with the multiple processing cores as root nodes based on the first dependency relationship between the multiple initial instructions corresponding to the multiple processing cores, wherein there is a dependency relationship between the processing cores corresponding to any two adjacent nodes in the multiple search trees, and wherein the third determination unit 404 includes: a first determination sub-unit, configured to determine, in response to determining that a first candidate instruction among the multiple candidate instructions depends on a second dependent instruction among the multiple initial instructions, based on the first dependency relationship between the first candidate instruction and the second dependent instruction, a new node for the multiple search trees; a search sub-unit, configured to traverse the multiple search trees including the new nodes using a tree search algorithm; and a second determination sub-unit, configured to determine that the first candidate instruction is the first new instruction in response to determining that each leaf node in the multiple search trees including the new nodes is different from the root node corresponding to the leaf node.

According to some embodiments, the tree search algorithm comprises a depth-first tree search algorithm.

According to some embodiments, the device 400 also includes: a second update unit, configured to update the multiple search trees based on the newly added nodes in response to determining that the first candidate instruction is the first newly added instruction, and wherein the third determination unit 404 is also configured to determine the third newly added instruction for the third processing core from the multiple candidate instructions based on the updated multiple search trees.

According to another aspect of the present disclosure, a chip is further provided, comprising the chip verification device 400 as described above.

According to another aspect of the present disclosure, an electronic device is also provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned chip verification method.

According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is further provided, wherein the computer instructions are used to enable the computer to execute the above-mentioned chip verification method.

According to another aspect of the present disclosure, a computer program product is also provided, including a computer program, wherein the computer program implements the above chip verification method when executed by a processor.

With reference to Fig. 5, the structural block diagram of the electronic device 500 that can be used as the server or client of the present disclosure will now be described, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer equipment, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples, and are not intended to limit the implementation of the present disclosure described and/or required herein.

As shown in FIG5 , the device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input/output (I/O) interface 505 is also connected to the bus 504.

Multiple components in the device 500 are connected to the I/O interface 505, including: an input unit 506, an output unit 507, a storage unit 508, and a communication unit 509. The input unit 506 can be any type of device that can input information to the device 500. The input unit 506 can receive input digital or character information and generate key signal input related to user settings and/or function control of the electronic device, and can include but is not limited to a mouse, a keyboard, a touch screen, a track pad, a track ball, a joystick, a microphone, and/or a remote controller. The output unit 507 can be any type of device that can present information, and can include but is not limited to a display, a speaker, a video/audio output terminal, a vibrator, and/or a printer. The storage unit 508 can include but is not limited to a disk, an optical disk. The communication unit 509 allows the device 500 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks, and can include but is not limited to a modem, a network card, an infrared communication device, a wireless communication transceiver, and/or a chipset, such as a Bluetooth device, an 802.11 device, a WiFi device, a WiMax device, a cellular communication device, and/or the like.

The computing unit 501 may be a variety of general and/or special processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 501 performs the various methods and processes described above, such as a chip verification method. For example, in some embodiments, the chip verification method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 508. In some embodiments, part or all of the computer program may be loaded and/or installed on the device 500 via ROM 502 and/or communication unit 509. When the computer program is loaded into RAM 503 and executed by the computing unit 501, one or more steps of the chip verification method described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform the chip verification method in any other appropriate manner (e.g., by means of firmware).

Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and/or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions/operations specified in the flow chart and/or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), the Internet, and a blockchain network.

A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be performed in parallel, sequentially or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document is not limited here.

Although the embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it should be understood that the above-mentioned methods, systems and devices are merely exemplary embodiments or examples, and the scope of the present invention is not limited by these embodiments or examples. Various elements in the embodiments or examples may be omitted or may be replaced by their equivalent elements. In addition, each step may be performed in an order different from that described in the present disclosure. Further, the various elements in the embodiments or examples may be combined in various ways. It is important that with the evolution of technology, many elements described herein may be replaced by equivalent elements that appear after the present disclosure.

Claims (14)

1. A chip verification method, wherein the chip comprises a plurality of processing cores, the method comprising:

For each of the plurality of processing cores, obtaining an initial instruction corresponding to the processing core, wherein each of the plurality of initial instructions corresponding to the plurality of processing cores is dependent on at least one other of the plurality of initial instructions;

Determining a second dependency relationship between the plurality of processing cores based on a first dependency relationship between a plurality of initial instructions corresponding to the plurality of processing cores;

Determining at least one first dependency core dependent on a first processing core from the plurality of processing cores based on the second dependency relationship;

determining a first new instruction for the first processing core from a plurality of candidate instructions, wherein the first new instruction is independent of an initial instruction corresponding to the at least one first dependent core;

Executing the plurality of initial instructions and the first new instruction with the chip; and

And determining a verification result for the chip based on the execution results of the plurality of initial instructions and the first new instruction.

2. The method of claim 1, further comprising:

In response to determining that the first new instruction depends on a third instruction of the plurality of initial instructions, updating the second dependency based on a third dependency between the first new instruction and the third instruction;

Determining at least one second dependent core from the plurality of processing cores that is dependent on a second processing core based on the updated second dependent relationship; and

Determining a second newly added instruction for the second processing core from the plurality of candidate instructions, wherein the target instruction is independent of an instruction corresponding to the at least one second dependent core,

And wherein said executing said plurality of initial instructions and said first newly added instruction with said chip comprises: executing the plurality of initial instructions, the first new instruction, and the second new instruction with the chip,

The determining, based on the execution results of the plurality of initial instructions and the first new instruction, a verification result for the chip includes:

And determining a verification result for the chip based on the execution results of the plurality of initial instructions, the first new instruction and the second new instruction.

3. The method of claim 1, wherein the determining a second dependency between the plurality of processing cores based on a first dependency between a plurality of initial instructions corresponding to the plurality of processing cores comprises:

Based on a first dependency relationship among a plurality of initial instructions corresponding to the plurality of processing cores, a plurality of search trees taking the plurality of processing cores as root nodes are established, wherein the dependency relationship is arranged between the processing cores corresponding to any two adjacent nodes in the plurality of search trees,

And wherein said determining a first new instruction for said first processing core from a plurality of candidate instructions comprises:

Responsive to determining that a first candidate instruction of the plurality of candidate instructions depends on a second dependent instruction of the plurality of initial instructions, determining newly added nodes for the plurality of search trees based on a first dependency relationship between the first candidate instruction and the second dependent instruction;

Traversing the plurality of search trees including the newly added node using a tree search algorithm; and

And in response to determining that each leaf node in the plurality of search trees including the newly added node is not identical to a root node corresponding to the leaf node, determining that the first candidate instruction is the first newly added instruction.

4. A method as claimed in claim 3, wherein the tree search algorithm comprises a depth-first tree search algorithm.

5. The method of claim 3 or 4, further comprising:

In response to determining that the first candidate instruction is the first newly added instruction, updating the plurality of search trees based on the newly added node; and

Based on the updated plurality of search trees, a third newly added instruction for a third processing core is determined from the plurality of candidate instructions.

6. A chip authentication apparatus, wherein the chip includes a plurality of processing cores, the apparatus comprising:

An acquisition unit configured to acquire, for each of the plurality of processing cores, an initial instruction corresponding to the processing core, wherein each of the plurality of initial instructions corresponding to the plurality of processing cores depends on at least one other of the plurality of initial instructions;

a first determination unit configured to determine a second dependency relationship between the plurality of processing cores based on a first dependency relationship between a plurality of initial instructions corresponding to the plurality of processing cores;

A second determining unit configured to determine at least one first dependent core depending on the first processing core from the plurality of processing cores based on the second dependent relationship;

A third determination unit configured to determine a first newly added instruction for the first processing core from a plurality of candidate instructions, wherein the first newly added instruction is independent of an initial instruction corresponding to the at least one first dependent core;

an execution unit configured to execute the plurality of initial instructions and the first newly added instruction using the chip; and

And a verification unit configured to determine a verification result for the chip based on the execution results of the plurality of initial instructions and the first additional instruction.

7. The apparatus of claim 6, further comprising:

A first updating unit configured to update the second dependency relationship based on a third dependency relationship between the first new instruction and a third instruction in the plurality of initial instructions in response to determining that the first new instruction depends on the third instruction, and wherein,

The second determining unit is further configured to determine at least one second dependency core depending on a second processing core from the plurality of processing cores based on the updated second dependency relationship,

The third determination unit is further configured to determine a second newly-added instruction for the second processing core from the plurality of candidate instructions, wherein the target instruction is independent of an instruction corresponding to the at least one second dependent core,

The execution unit is configured to execute the plurality of initial instructions, the first add instruction, and the second add instruction with the chip,

The verification unit is configured to determine a verification result for the chip based on execution results of the plurality of initial instructions, the first newly-added instruction, and the second newly-added instruction.

8. The apparatus of claim 6, wherein the second determination unit is configured to:

Based on a first dependency relationship among a plurality of initial instructions corresponding to the plurality of processing cores, a plurality of search trees taking the plurality of processing cores as root nodes are established, wherein the dependency relationship is arranged between the processing cores corresponding to any two adjacent nodes in the plurality of search trees,

And wherein the third determination unit includes:

A first determination subunit configured to determine, in response to determining that a first candidate instruction of the plurality of candidate instructions depends on a second dependent instruction of the plurality of initial instructions, a newly added node for the plurality of search trees based on a first dependency relationship between the first candidate instruction and the second dependent instruction;

a search subunit configured to traverse the plurality of search trees including the newly added node using a tree search algorithm; and

And a second determining subunit configured to determine, in response to determining that each leaf node in the plurality of search trees including the new node is not identical to a root node corresponding to the leaf node, the first candidate instruction as the first new instruction.

9. The apparatus of claim 8, wherein the tree search algorithm comprises a depth-first tree search algorithm.

10. The apparatus of claim 8 or 9, further comprising:

A second updating unit configured to update the plurality of search trees based on the newly added node in response to determining that the first candidate instruction is the first newly added instruction, and wherein,

The third determination unit is further configured to determine a third newly added instruction for a third processing core from the plurality of candidate instructions based on the updated plurality of search trees.

11. A chip comprising the apparatus of any one of claims 6-10.

12. An electronic device, comprising:

At least one processor; and

A memory communicatively coupled to the at least one processor; wherein the method comprises the steps of

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

13. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-5.

14. A computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the method according to any of claims 1-5.