CN118841056A - Verification method and device for soft decoding function, storage medium and electronic equipment - Google Patents

Abstract

The embodiments of the present application provide a method and device for verifying a soft decoding function, a storage medium and an electronic device, which relate to the field of computers, and include: instructing a non-volatile flash memory NAND Flash controller in a solid-state drive (SSD) to use a low-density parity check code (LDPC) to write target data into a specified storage block in the NAND Flash; instructing the NAND Flash controller to obtain specified data from the specified storage block, the specified data including: original data, soft bit data and paired page data; the original data is data stored in a target page in the specified storage block after being encoded using LDPC, the soft bit data is data generated in the process of NAND Flash storing the original data, and the paired page data is data stored in a page adjacent to the target page in the specified storage block; performing error annotation on the original data to obtain error data; instructing the NAND Flash controller to soft-decode the error data according to the soft bit data and the paired page data to obtain a soft decoding result; and verifying the soft decoding function of the NAND Flash controller according to the soft decoding result.

Description

Soft decoding function verification method and device, storage medium and electronic device

Technical Field

The embodiments of the present application relate to the field of computers, and more specifically, to a method and device for verifying a soft decoding function, a storage medium, and an electronic device.

Background Art

Solid State Disk (SSD), also known as solid state drive, is a hard disk made of solid-state electronic storage chip array. SSD consists of a control unit and a storage unit, where the storage unit includes but is not limited to: Flash chip, Dram chip. Flash-based solid state disk is the main category of solid state disk. Its main body is a printed circuit board (PCB). The basic components on the PCB are control chip, cache chip and flash memory chip for storing data.

The storage medium used by most SSDs is computer flash memory devices (Nand Flash), which is a non-volatile memory. Since the basic storage unit of Nand Flash is a floating gate transistor, and due to its physical structure, it has physical characteristics such as charge leakage and oxide layer aging, which causes Nand Flash to be affected by drift effect, over-programming effect, read operation interference, temperature and other factors during use, resulting in read errors, programming failures or erase programming failures, and bit inversion. In order to solve this problem, the related technology uses low-density parity-check code (LDPC) soft decoding in SSD to protect the data stored in the SSD from bit errors.

However, at present, there is only a soft decoding error handling process. There is no suitable method to verify the soft decoding function when testing the module during the Nand Flash controller development phase. In the system testing process, the soft decoding process can only be performed passively when an error occurs and other previous error handling processes fail. It is impossible to actively and quickly check whether the data error correction and recovery functions of the soft decoding hardware and code modules are available, which increases the R&D and testing costs and is not conducive to efficient testing.

With regard to the problem in the related art that the soft decoding function in the SSD cannot be actively verified, no effective solution has been proposed yet.

Summary of the invention

The embodiments of the present application provide a method and device for verifying a soft decoding function, a storage medium, and an electronic device, so as to at least solve the problem that the soft decoding function in the SSD cannot be actively verified.

According to an embodiment of the present application, a method for verifying a soft decoding function is provided, comprising: instructing a non-volatile flash memory NAND Flash controller in a solid state drive (SSD) to write target data into a designated storage block in the NAND Flash using a low-density parity check code (LDPC); instructing the NAND Flash controller to obtain designated data from the designated storage block, wherein the designated data comprises: original data, soft bit data and paired page data; the original data is data stored in a target page in the designated storage block after being encoded using the LDPC, the soft bit data is data generated in the process of the NAND Flash storing the original data, and the paired page data is data stored in a page in the designated storage block adjacent to the target page; performing error annotation on the original data to obtain error data; instructing the NAND Flash controller to soft-decode the error data according to the soft bit data and the paired page data to obtain a soft decoding result; and verifying the soft decoding function of the NAND Flash controller according to the soft decoding result.

In an exemplary embodiment, before instructing a non-volatile flash memory NAND Flash controller in a solid state drive SSD to use a low-density parity check code LDPC to write target data into a designated storage block in the NAND Flash, the method further includes: obtaining data stored in a first type of register in the NAND Flash controller, and determining that the first type of register in the NAND Flash controller is not abnormal if the data stored in the first type of register meets a first preset condition, wherein the data contained in the first type of register is preset and cannot be modified; and/or writing first preset data to a second type of register in the NAND Flash controller; obtaining data stored in the second type of register in the NAND Flash controller, and determining that the second type of register in the NAND Flash controller is not abnormal if the data stored in the second type of register is the first preset data, wherein the second type of register allows data to be written and allows the data stored therein to be read; and/or writing second preset data to a third type of register in the NAND Flash controller; obtaining data stored in the third type of register in the NAND Flash controller, and determining that the NAND Flash controller is abnormal if the data stored in the third type of register is the third preset data. There is no abnormality in the third type of register in the Flash controller, wherein after the second preset data is written into the third type of register, the corresponding bit of the third type of register will be cleared.

In an exemplary embodiment, before instructing a non-volatile flash memory NAND Flash controller in a solid state drive SSD to use a low-density parity-check code LDPC to write target data to a designated storage block in the NAND Flash, the method further includes: instructing the NAND Flash controller to erase data stored in the designated storage block; instructing the non-volatile flash memory NAND Flash controller in the solid state drive SSD to use a low-density parity-check code LDPC to write target data to a designated storage block in the NAND Flash includes: instructing the NAND Flash controller to use LDPC to write the target data to one or more designated pages in the designated storage block in the NAND Flash, wherein the one or more designated pages include the target page.

In an exemplary embodiment, instructing the NAND Flash controller to obtain the specified data from the specified storage block includes: sending a soft decoding instruction to the NAND Flash controller to instruct the NAND Flash controller to obtain the specified data from the specified storage block.

In an exemplary embodiment, the instructing the NAND Flash controller to obtain the specified data from the specified storage block includes: instructing the NAND Flash controller to send a read instruction to the NAND Flash to read target sub-data from the specified storage block, wherein the target sub-data is data obtained after decoding the original data using the LDPC; when the status data sent by the NAND Flash in response to the read instruction is obtained, the value of the target bit in the status data is set to a preset value, wherein the value of the target bit is the preset value for indicating that an error has occurred in the read data, and when the NAND Flash controller determines that the value of the target bit in the status data is the preset value, the NAND Flash controller obtains the specified data from the specified storage block.

In an exemplary embodiment, the method of performing error injection on the original data to obtain erroneous data includes: determining N target bits from the original data, wherein the original data has M bits, the M bits include the N target bits, and a ratio of N to M is less than a preset threshold; and flipping the data at each target bit of the N target bits of the original data.

In an exemplary embodiment, verifying the soft decoding function of the NAND Flash controller according to the soft decoding result includes: when a cyclic redundancy check CRC check value and an error correction code ECC check value in the soft decoding result are both zero, determining that the soft decoding function of the NAND Flash controller is normal; when the CRC check value in the soft decoding result is not zero, determining that the soft decoding function of the NAND Flash controller is abnormal; when the ECC check value in the soft decoding result is not zero, determining that the soft decoding function of the NAND Flash controller is abnormal.

According to another embodiment of the embodiment of the present application, a verification device for a soft decoding function is also provided, including: a writing module, used to instruct a non-volatile flash memory NAND Flash controller in a solid state drive SSD to use a low-density parity check code LDPC to write target data into a specified storage block in the NAND Flash; an acquisition module, used to instruct the NAND Flash controller to obtain specified data from the specified storage block, wherein the specified data includes: original data, soft bit data and paired page data; the original data is the data stored in the target page in the specified storage block after using the LDPC encoding, the soft bit data is the data generated in the process of the NAND Flash storing the original data, and the paired page data is the data stored in the page adjacent to the target page in the specified storage block; an error injection module, used to perform error injection on the original data to obtain error data; a soft decoding module, used to instruct the NAND Flash controller to perform soft decoding on the error data according to the soft bit data and the paired page data to obtain a soft decoding result; and a verification module, used to verify the soft decoding function of the NAND Flash controller according to the soft decoding result.

According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

According to another embodiment of the present application, a computer program product is provided. The computer program product includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

Through this application, the NAND Flash controller is instructed to first write the target data into the NAND Flash, then obtain the original data, soft bit data and paired page data from the NAND Flash (i.e., actively trigger the soft decoding function of the NAND Flash controller), make errors in the original data, obtain error data, and then instruct the NAND Flash controller to soft-decode the error data according to the soft bit data and paired page data, so as to verify whether the soft decoding function of the NAND Flash controller is correct according to the decoding result. That is, this application can actively trigger the soft decoding function of the NAND Flash controller, and then verify whether the soft decoding function of the NAND Flash controller is normal, which solves the problem that the soft decoding function in the SSD cannot be actively verified.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

FIG1 is a hardware structure block diagram of a server device of a method for verifying a soft decoding function according to an embodiment of the present application;

FIG2 is a flow chart of a method for verifying a soft decoding function according to an embodiment of the present application;

FIG3 is a schematic diagram of a flow chart of an optional soft decoding function according to an embodiment of the present application;

FIG4 is a schematic diagram of another optional soft decoding function flow according to an embodiment of the present application;

FIG5 is a structural block diagram of a verification device for a soft decoding function according to an embodiment of the present application;

FIG6 is a schematic diagram of the structure of an optional electronic device according to an embodiment of the present application.

DETAILED DESCRIPTION

The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

The verification method embodiment of the soft decoding function provided in the embodiment of the present application can be executed in a server device or a similar computing device. Taking operation on a server device as an example, FIG. 1 is a hardware structure block diagram of a server device of a verification method of a soft decoding function in an embodiment of the present application. As shown in FIG. 1 , the server device may include one or more (only one is shown in FIG. 1 ) processors 1 02 (the processor 1 02 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 1 04 for storing data, wherein the above-mentioned server device may also include a transmission device 1 06 and an input-output device 1 08 for a communication function. It can be understood by those skilled in the art that the structure shown in FIG. 1 is only for illustration, and it does not limit the structure of the above-mentioned server device. For example, the server device may also include more or fewer components than those shown in FIG. 1 , or have a configuration different from that shown in FIG. 1 .

The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the verification method of the soft decoding function in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

For a better understanding, the following is a detailed description of soft decoding: Soft decoding is a method of decoding LDPC using soft information of the received signal. The main functions of LDPC soft decoding are:

Error detection and correction: LDPC code is a powerful forward error correction code that can detect and correct a certain number of errors and maintain data integrity even when the storage unit begins to degrade. Its principle is to encode the original data through the encoder before data transmission to generate a set of check bits, which are sent to the receiving end together with the original data. After the receiving end receives the data, it decodes the received data through the decoder and detects and corrects errors through the check bits. It has high error correction performance and low encoding and decoding complexity.

Soft information utilization: Different from traditional hard decoding (which only determines the bit value based on a threshold), soft decoding takes into account the soft information of the read signal, such as log-likelihood ratio (LLR) or probability value, which provides a more accurate estimate of the bit correctness.

Improve data reliability: Through soft decoding, the SSD controller can more effectively correct single or multiple bit errors when reading data, thereby improving data reliability and overall storage system stability.

Optimizing performance: Soft decoding algorithms, such as Belief Propagation or Sum-Product Algorithm, can continuously improve the decoding accuracy over multiple iterations, thus achieving better performance in practical applications.

Adaptability: The LDPC soft decoding algorithm can be adjusted according to the characteristics and operating conditions of the NAND flash memory in the SSD to adapt to different error modes and signal-to-noise ratios, thereby optimizing error correction performance.

In SSDs, LDPC soft decoding is often tightly integrated with hardware and firmware to achieve efficient error detection and correction. This integration ensures that data remains intact even when the storage media begins to age or fail, thereby extending the life of the SSD and improving overall performance.

In order to solve the above problems existing in the related art, a method for verifying a soft decoding function is provided in the present embodiment, wherein the execution subject includes but is not limited to a soft decoding function verification module, wherein the soft decoding function verification module has a test script, and the soft decoding function verification module performs corresponding operations according to the running logic in the test script. As shown in FIG. 2, the process includes the following steps S202-S210:

Step S202: instructing a non-volatile flash memory NAND Flash controller in the solid state drive SSD to write target data into a designated storage block in the NAND Flash using a low-density parity check code LDPC;

Optionally, the NAND Flash controller may be instructed to encode the target data using LDPC, and then write the encoded data into a specified storage block in the NAND Flash.

In an exemplary embodiment, before the above step S202, the method further includes the following steps S21 and/or, step S22 and/or, step S23:

Step S21: acquiring data stored in a first type of register in the NAND Flash controller, and determining that no abnormality occurs in the first type of register in the NAND Flash controller when the data stored in the first type of register meets a first preset condition, wherein the data contained in the first type of register is preset and cannot be modified;

Optionally, the first type of register is a read-only register (Read-Only Register, referred to as RO register for short), and the first preset condition includes: the value of the register is 0.

That is, the soft decoding function verification module can read the values stored in each RO register in the NAND Flash controller in sequence. If the read value is 0, it is determined that there is no abnormality in the corresponding RO register.

It should be noted that the data contained in the RO registers are preset by the system or hardware, and their contents cannot be modified by users or software.

Step S22: writing first preset data to a second type of register in the NAND Flash controller; acquiring data stored in the second type of register in the NAND Flash controller, and determining that no abnormality occurs in the second type of register in the NAND Flash controller when the data stored in the second type of register is the first preset data, wherein the second type of register allows data to be written and allows data stored therein to be read;

Optionally, the second type of register is a read-write register (Read-Write Register, referred to as RW register for short).

That is to say, the soft decoding function verification module can write the first preset data (optionally, the first preset data is 1) to the binary digit (bit) of each RW register, and then read the value of each RW register. If the bit of each RW register read is 1, the corresponding RW register has no abnormality.

It should be noted that the RW register is a register in computer hardware that allows the user not only to read the data stored therein but also to write data therein.

Step S23: writing second preset data to a third type of register in the NAND Flash controller; obtaining data stored in the third type of register in the NAND Flash controller, and determining that no abnormality occurs to the third type of register in the NAND Flash controller when the data stored in the third type of register is the third preset data, wherein after writing the second preset data to the third type of register, the corresponding bit of the third type of register will be cleared.

Optionally, the third type of register is a read-write-clear register (Read-Write-1-Clear register, referred to as RW1C register).

That is to say, the soft decoding function verification module can write the second preset data (optionally, the second preset data is 1) to the bit of each RW1C register, and then read the value of each RW1C register. If the data stored in each RW1C register read is the third preset data (optionally, the second preset data is 0), the corresponding RW1C register has no abnormality.

It should be noted that the RW1C register combines the features of read, write and clear, and can be read and written, but when 1 is written, the corresponding bit of the register will be cleared (ie, set to 0).

Optionally, the first type, the second type and the third type of registers in the above-mentioned NAND Flash controller are registers required for the NAND Flash controller to implement a soft decoding function.

In this embodiment, through the above steps S21-S23, it can be accurately determined whether there is an abnormality in the register supporting the soft decoding function in the NAND Flash controller.

It should be noted that before verifying the soft decoding function of the NAND Flash controller, it is necessary to first determine whether there is an abnormality in the register supporting the soft decoding function in the NAND Flash controller. If there is an abnormality in the register supporting the soft decoding function in the NAND Flash controller, the soft decoding function of the NAND Flash controller must be abnormal. If there is no abnormality in the register supporting the soft decoding function in the NAND Flash controller, continue to use steps S202-S210 to verify the soft decoding function of the NAND Flash controller.

In an exemplary embodiment, before the above step S202, the method further includes the following step S31:

Step S3 1: instructing the NAND Flash controller to erase the data stored in the designated storage block;

It should be noted that a data block is the largest data erasure unit in an SSD. In an SSD, data is erased and programmed in blocks, and each block contains multiple pages.

It should be noted that Page is the basic read and write unit in SSD. Within the block of SSD, data is read and written in units of Page.

In an exemplary embodiment, the above step S202 can be implemented by the following step S32:

Step S32: instructing the NAND Flash controller to write the target data into one or more designated pages in a designated storage block in the NAND Flash using LDPC, wherein the one or more designated pages include the target page.

It should be noted that, in this embodiment, before writing the target data into one or more designated pages in the designated storage block, the data stored in the designated storage block needs to be erased first, so as to avoid data writing errors.

Step S204: instructing the NAND Flash controller to obtain designated data from the designated storage block, wherein the designated data includes: original data, soft bit data and paired page data; the original data is the data stored in the target page in the designated storage block after using the LDPC encoding, the soft bit data is the data generated in the process of the NAND Flash storing the original data, and the paired page data is the data stored in the page adjacent to the target page in the designated storage block;

It should be noted that instructing the NAND Flash controller to obtain designated data from the designated storage block is equivalent to instructing the NAND Flash controller to trigger a soft decoding function.

It should be noted that raw data refers to the received bit sequence ready for soft decoding;

It should be noted that soft bit data (Soft bit) refers to data containing bit decisions and corresponding reliability information. Soft bit data is an intermediate data form used in NAND Flash memory to manage and protect original data. By processing and correcting the original data, the reliability and reliability of the data in the memory are ensured.

Soft bit data usually includes the following: 1. ECC check code: Soft bit data contains error correction code (ECC) for error detection and correction to ensure the integrity of data during reading and writing. 2. Physical location information: Soft bit data may contain information about the physical location of data in the NAND Flash chip to help the system read and write data correctly. 3. Page status information: Soft bit data may contain status information about the data page, such as whether it has been erased or written with new data. 4. Data conversion information: Soft bit data may contain information about data encoding and conversion to ensure that data is correctly represented and interpreted in the memory.

It should be noted that the paired page data (Couple page) refers to the related pages required for soft decoding of a page.

In an exemplary embodiment, the above step S204 can be implemented by the following steps S41:

Step S41: Send a soft decoding instruction to the NAND Flash controller to instruct the NAND Flash controller to obtain designated data from the designated storage block.

That is to say, in this embodiment, the soft decoding function of the NAND Flash controller can be directly triggered by means of instructions, that is, a soft decoding instruction is directly sent to the NAND Flash controller, thereby triggering the soft decoding function of the NAND Flash controller. That is, through the above step S41, the soft decoding hardware of the SSD (that is, the NAND Flash controller) can be tested.

In an exemplary embodiment, the above step S204 can also be implemented by the following steps S51-S52:

Step S51: instructing the NAND Flash controller to send a read instruction to the NAND Flash to read target sub-data from the designated storage block, wherein the target sub-data is data obtained after decoding the original data using the LDPC;

Step S52: when the status data sent by the NAND Flash in response to the read instruction is obtained, the value of the target bit in the status data is set to a preset value, wherein the value of the target bit is the preset value and is used to indicate that an error has occurred in the read data. When the NAND Flash controller determines that the value of the target bit in the status data is the preset value, the NAND Flash controller obtains the specified data from the specified storage block.

In the related art, after the NAND Flash controller sends a read instruction to the NAND Flash, the NAND Flash will return a status data, and then the NAND Flash controller can determine whether to trigger the soft decoding function according to the value of the target bit in the status data. If the NAND Flash controller determines that the value of the target bit in the status data is a preset value, the NAND Flash controller will trigger the soft decoding function.

Furthermore, in the embodiment of the present application, the value of the target bit in the status data returned by the NAND Flash can be actively set to a preset value, thereby triggering the soft decoding function of the NAND Flash controller, and then the entire soft decoding module of the NAND Flash controller can be tested through the above steps S51-S52.

Step S206: Annotate the original data to obtain error data;

In an exemplary embodiment, the above step S206 can be implemented by the following steps S61-S62:

Step S61: determining N target bits from the original data, wherein the original data has M bits, the M bits include the N target bits, and a ratio of N to M is less than a preset threshold;

It should be noted that N is a positive integer greater than zero, and M is a positive integer greater than or equal to N.

Step S62: Flip the data of each target bit of the original data in the N target bits.

Optionally, if the data on the target bit is 1, the data on the target bit is 0 after the data is flipped; if the data on the target bit is 0, the data on the target bit is 1 after the data is flipped.

It should be noted that, through the above steps S61-S62, the original data can be quickly annotated.

Step S208: instructing the NAND Flash controller to soft-decode the error data according to the soft bit data and the paired page data to obtain a soft decoding result;

Optionally, the soft decoding result includes but is not limited to: a check value of a cyclic redundancy check (CRC) and a check value of an error correction code (ECC).

It should be noted that CRC is a technology mainly used to detect errors in data transmission or storage, and ECC is a coding technology used to detect and automatically correct errors in data.

Step S210: verifying the soft decoding function of the NAND Flash controller according to the soft decoding result.

In an exemplary embodiment, the above step S210 can be implemented by the following steps S71-S73:

Step S7 1: When the cyclic redundancy check CRC check value and the error correction code ECC check value in the soft decoding result are both zero, it is determined that the soft decoding function of the NAND Flash controller is normal;

Step S72: when the CRC check value in the soft decoding result is not zero, determining that the soft decoding function of the NAND Flash controller is abnormal;

Step S73: when the ECC check value in the soft decoding result is not zero, it is determined that the soft decoding function of the NAND Flash controller is abnormal.

It should be noted that a CRC check value of 0 indicates that no error was found during data transmission or storage. After soft decoding, if CRC is 0, it means that no transmission error or data damage occurred during data processing, and data integrity is guaranteed. An ECC check value of 0 indicates that no error was found or all errors were successfully corrected after error correction. After soft decoding, if ECC is 0, it means that the error correction code successfully corrected all error bits and the data has been correctly recovered.

It should be noted that, through the above steps S71-S73, the soft decoding function of the NAND Flash controller can be verified quickly and accurately.

It should be noted that the above steps S71-S73 are steps executed in different situations and there is no specific execution order.

The above steps S202-S210 instruct the NAND Flash controller to first write the target data into the NAND Flash, then obtain the original data, soft bit data and paired page data from the NAND Flash (i.e., actively trigger the soft decoding function of the NAND Flash controller), perform error injection on the original data to obtain error data, and then instruct the NAND Flash controller to soft-decode the error data according to the soft bit data and paired page data, thereby verifying whether the soft decoding function of the NAND Flash controller is correct according to the decoding result. That is, the present application can actively trigger the soft decoding function of the NAND Flash controller, and then verify whether the soft decoding function of the NAND Flash controller is normal, thereby solving the problem that the soft decoding function in the SSD cannot be actively verified.

Obviously, the above-described embodiments are only embodiments of a part of the present invention, rather than all embodiments. In order to better understand the above method, the above process is described below in conjunction with embodiments, but it is not intended to limit the technical solutions of the embodiments of the present invention, specifically:

This application is divided into three levels of testing, namely register testing, soft hardware testing and soft function testing. The above three levels of testing can be completed by writing corresponding test scripts, and then executing the NandFlash controller to perform corresponding operations according to the test scripts, thereby completing the test tasks.

1. Register test: For RO type registers, read out the value of each register in turn, and the normal value is 0; for RW type registers, write 1 to the bit of each register in turn, and then read out the value of each register. All bits are 1, indicating that the RW register test is normal; for RW1C type bits, after writing 1, read out as 0, indicating that the bit of this register is normal.

2. Soft decoding hardware test: The host sends a message to operate the Nand Flash controller to erase the specified block, and then writes the page initial data (i.e. the target data mentioned above); then sends a message to read the data, and the Nand Flash controller reads the raw data, soft bit data, and couple page data from the NAND flash memory to the specified address. As shown in Figure 3, the Nand Flash controller first erases the specified Block data in the storage block, then writes the Page initial data to the Nand, and then reads the specified data, starts the soft decoding (including configuring the soft decoding mode) through the serial port command, injects errors into the raw data, and obtains the soft decoding result through the soft decoding process. Finally, it is determined whether the CRC and ECC in the soft decoding result are 0 to determine whether the soft decoding function of the Nand Flash controller is normal.

3. Soft decoding function test: including testing the soft decoding state machine and hardware. As shown in Figure 4, the user inputs the soft decoding module test command through the serial port to start the test of the soft decoding module. The Nand Flash controller first erases the specified Block data in the storage block, then writes the Page initial data to the Nand, and sends a read command to read the target sub-data. The host forces the error bitmap in the status returned by the read command to be set to 1, and then the Nand Flash controller starts the soft decoding state machine to read out the raw data, soft bit data, and couple page data, and annotates the error in the raw data, starts the soft decoding driver to obtain the soft decoding result, and finally determines whether the CRC and ECC in the soft decoding result are 0 to determine whether the soft decoding function of the Nand Flash controller is normal.

For a better understanding, the following is a detailed description of register test, software solution hardware test, and software solution function test:

1. Register test: (1) Set the test type in the code to soft decode register test; (2) Power on after compiling;

(3) View the test results through the log.

2. Soft decoding hardware test: (1) Set the test type to soft decoding hardware test in the code; (2) After compiling, power on, erase the specified block through the serial port command, and then write the page initial data; (3) Read raw data, soft bit data, and couple page data through the serial port command, and annotate the raw data; (4) Start soft decoding through the serial port command; (5) Check that the CRC and ECC of the soft decoding results are 0.

3. Soft decoding function test: (1) Set the test type to soft decoding function test in the code; (2) After compiling, power on, write a data to the specified address and read it through the serial port command; (3) Set the read return status Errorbitmap to 1 through the serial port command to start the soft decoding state machine; (4) Annotate the raw data with errors through the serial port command; (5) Check that the CRC and ECC of the soft decoding results are 0.

It should be noted that the application proposes a SSD software error test function based on the soft decoding and error correction method performed when the Nand Flash controller reads NAND data. This function is designed to conduct a comprehensive and detailed test on the soft decoding module from hardware to software to ensure that the soft decoding module can run stably and accurately in a complex and changing working environment.

It should be noted that when applying the error injection test method of this application, errors can be injected into different stages and links of the SSD software to simulate various abnormal situations that may occur during actual use. In this way, it can be effectively verified whether the hardware functions of the software solution module meet the design requirements and whether it can correctly correct and recover when errors occur.

It should be noted that this application also has the ability to actively verify and test firmware code. By injecting errors into the firmware code, potential problems in the code can be discovered in a timely manner, such as logic errors, memory leaks, etc., so that they can be repaired and optimized at an early stage to avoid larger problems in subsequent development and use.

Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

In this embodiment, a verification device for soft decoding function is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and/or hardware of a predetermined function. Although the modules described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

FIG5 is a structural block diagram of a verification device for a soft decoding function according to an embodiment of the present application, the device comprising:

The writing module 502 is used to instruct the non-volatile flash memory NAND Flash controller in the solid state drive SSD to write the target data into a designated storage block in the NAND Flash using a low-density parity check code LDPC;

The acquisition module 504 is used to instruct the NAND Flash controller to acquire designated data from the designated storage block, wherein the designated data includes: original data, soft bit data and paired page data; the original data is the data stored in the target page in the designated storage block after using the LDPC encoding, the soft bit data is the data generated in the process of the NAND Flash storing the original data, and the paired page data is the data stored in the page adjacent to the target page in the designated storage block;

An error annotation module 506 is used to perform error annotation on the original data to obtain error data;

A soft decoding module 508, configured to instruct the NAND Flash controller to perform soft decoding on the error data according to the soft bit data and the paired page data to obtain a soft decoding result;

The verification module 510 is used to verify the soft decoding function of the NAND Flash controller according to the soft decoding result.

The above device instructs the NAND Flash controller to first write the target data into the NAND Flash, then obtains the original data, soft bit data and paired page data from the NAND Flash (i.e., actively triggers the soft decoding function of the NAND Flash controller), injects errors into the original data to obtain error data, and then instructs the NAND Flash controller to soft-decode the error data according to the soft bit data and paired page data, thereby verifying whether the soft decoding function of the NAND Flash controller is correct according to the decoding result. That is, the present application can actively trigger the soft decoding function of the NAND Flash controller, and then verify whether the soft decoding function of the NAND Flash controller is normal, which solves the problem that the soft decoding function in the SSD cannot be actively verified.

In an exemplary embodiment, the above-mentioned device also includes: a determination module, which is used to obtain data stored in a first type of register in the NAND Flash controller before instructing the non-volatile flash memory NAND Flash controller in the solid state drive SSD to use a low-density parity check code LDPC to write the target data to a designated storage block in the NAND Flash, and determine that the first type of register in the NAND Flash controller has no abnormality when the data stored in the first type of register meets a first preset condition, wherein the data contained in the first type of register is preset and cannot be modified; and/or write first preset data to a second type of register in the NAND Flash controller; obtain data stored in the second type of register in the NAND Flash controller, and determine that the second type of register in the NAND Flash controller has no abnormality when the data stored in the second type of register is the first preset data, wherein the second type of register allows data to be written and allows the data stored therein to be read; and/or write second preset data to a third type of register in the NAND Flash controller; obtain data stored in the third type of register in the NAND Flash controller, and determine that the NAND Flash controller has no abnormality when the data stored in the third type of register is the third preset data. There is no abnormality in the third type of register in the Flash controller, wherein after the second preset data is written into the third type of register, the corresponding bit of the third type of register will be cleared.

In an exemplary embodiment, the above-mentioned device also includes: an erase module, which is used to instruct the non-volatile flash memory NAND Flash controller in the solid state drive SSD to erase the data stored in the specified storage block before instructing the NAND Flash controller to use a low-density parity check code LDPC to write the target data to the specified storage block in the NAND Flash; a write module 502, which is used to instruct the NAND Flash controller to use LDPC to write the target data to one or more specified pages in the specified storage block in the NAND Flash, wherein the one or more specified pages include the target page.

In an exemplary embodiment, the acquisition module 504 is used to instruct the NAND Flash controller to obtain the specified data from the specified storage block in the following manner: sending a soft decoding instruction to the NAND Flash controller to instruct the NAND Flash controller to obtain the specified data from the specified storage block.

In an exemplary embodiment, the acquisition module 504 is also used to instruct the NAND Flash controller to acquire specified data from the specified storage block in the following manner: instruct the NAND Flash controller to send a read instruction to the NAND Flash to read target sub-data from the specified storage block, wherein the target sub-data is data obtained after decoding the original data using the LDPC; when the status data sent by the NAND Flash in response to the read instruction is acquired, the value of the target bit in the status data is set to a preset value, wherein the value of the target bit is the preset value used to indicate that an error has occurred in the read data, and when the NAND Flash controller determines that the value of the target bit in the status data is the preset value, the NAND Flash controller acquires the specified data from the specified storage block.

In an exemplary embodiment, the error injection module 506 is used to perform error injection on the original data to obtain erroneous data in the following manner: determine N target bits from the original data, wherein the original data has M bits, the M bits include the N target bits, and the ratio of N to M is less than a preset threshold; and flip the data at each target bit of the N target bits of the original data.

In an exemplary embodiment, the verification module 510 is used to verify the soft decoding function of the NAND Flash controller according to the soft decoding result in the following manner: when the cyclic redundancy check CRC check value and the error correction code ECC check value in the soft decoding result are both zero, it is determined that the soft decoding function of the NAND Flash controller is normal; when the CRC check value in the soft decoding result is not zero, it is determined that the soft decoding function of the NAND Flash controller is abnormal; when the ECC check value in the soft decoding result is not zero, it is determined that the soft decoding function of the NAND Flash controller is abnormal.

It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

Optionally, in this embodiment, the computer program may be configured to perform the following steps by means of the computer program:

S 1, instructing the non-volatile flash memory NAND Flash controller in the solid state drive SSD to write the target data into a specified storage block in the NAND Flash using a low-density parity check code LDPC;

S2, instructing the NAND Flash controller to obtain designated data from the designated storage block, wherein the designated data includes: original data, soft bit data and paired page data; the original data is the data stored in the target page in the designated storage block after using the LDPC encoding, the soft bit data is the data generated in the process of the NAND Flash storing the original data, and the paired page data is the data stored in the page adjacent to the target page in the designated storage block;

S3, performing error annotation on the original data to obtain error data;

S4, instructing the NAND Flash controller to soft-decode the error data according to the soft bit data and the paired page data to obtain a soft decoding result;

S5: Verify the soft decoding function of the NAND Flash controller according to the soft decoding result.

In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

An embodiment of the present application further provides an electronic device, as shown in FIG6 , the electronic device includes a memory 602 and a processor 604 , the memory 602 stores a computer program, and the processor 604 is configured to execute the steps in any of the above method embodiments through the computer program.

Optionally, in this embodiment, the processor 604 may be configured to perform the following steps through a computer program:

S 1, instructing the non-volatile flash memory NAND Flash controller in the solid state drive SSD to write the target data into a specified storage block in the NAND Flash using a low-density parity check code LDPC;

S2, instructing the NAND Flash controller to obtain designated data from the designated storage block, wherein the designated data includes: original data, soft bit data and paired page data; the original data is the data stored in the target page in the designated storage block after using the LDPC encoding, the soft bit data is the data generated in the process of the NAND Flash storing the original data, and the paired page data is the data stored in the page adjacent to the target page in the designated storage block;

S3, performing error annotation on the original data to obtain error data;

S4, instructing the NAND Flash controller to soft-decode the error data according to the soft bit data and the paired page data to obtain a soft decoding result;

S5: Verify the soft decoding function of the NAND Flash controller according to the soft decoding result.

For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

Alternatively, those skilled in the art will appreciate that the structure shown in FIG6 is for illustration only, and FIG6 does not limit the structure of the electronic device. For example, the electronic device may include more or fewer components (such as network interfaces, etc.) than those shown in FIG6, or may have a configuration different from that shown in FIG6.

Among them, the memory 602 can be used to store software programs and modules, such as the program instructions/modules corresponding to the verification method of the soft decoding function and the verification device of the soft decoding function in the embodiment of the present application. The processor 604 executes various functional applications and data processing by running the software programs and modules stored in the memory 602, that is, the verification method of the soft decoding function mentioned above is realized. The memory 602 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 602 may further include a memory remotely arranged relative to the processor 604, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. Among them, the memory 602 may be specifically used for storing information such as system configuration files, but is not limited to it. As an example, as shown in Figure 6, the above-mentioned memory 602 may include but is not limited to the writing module 502, the acquisition module 504, the error injection module 506, the soft decoding module 508, and the verification module 510 in the verification device of the above-mentioned soft decoding function. In addition, other module units in the verification device may also be included but not limited to the above-mentioned soft decoding function, which will not be described in detail in this example.

Optionally, the transmission device 606 is used to receive or send data via a network. Specific examples of the network may include a wired network and a wireless network. In one example, the transmission device 606 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices and routers via a network cable so as to communicate with the Internet or a local area network. In one example, the transmission device 606 is a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

In addition, the electronic device further includes: a display 608; and a connection bus 610, which is used to connect various module components in the electronic device.

In other embodiments, the electronic device may be a node in a distributed system, wherein the distributed system may be a blockchain system, and the blockchain system may be a distributed system formed by connecting the multiple nodes in the form of network communication. Among them, the nodes may form a peer-to-peer (P2P) network, and any form of computing device, such as a server, terminal, or other electronic device, may become a node in the blockchain system by joining the peer-to-peer network.

An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

The embodiments of the present application also provide a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any one of the above method embodiments.

Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A verification method of soft decoding function is characterized in that,

Comprising the following steps:

Instructing a nonvolatile flash memory NAND FLASH controller in the solid state disk SSD to write the target data to the specified memory block in NAND FLASH using the low density parity check code LDPC;

instructing the NANDFlash controller to acquire specified data from the specified storage block, wherein the specified data comprises: raw data, soft bit data and paired page data; the original data is data after the LDPC coding stored in a target page in the specified storage block, the soft bit data is data generated in the process of storing the original data by NAND FLASH, and the pair-page data is data stored in a page adjacent to the target page in the specified storage block;

Performing error injection on the original data to obtain error data;

instructing the NAND FLASH controller to perform soft decoding on the error data according to the soft bit data and the paired page data to obtain a soft decoding result;

and verifying the soft decoding function of the NAND FLASH controller according to the soft decoding result.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The method further includes, before the instructing the nonvolatile flash memory NAND FLASH controller in the solid-state disk SSD to write the target data to the specified storage block in NAND FLASH using the low-density parity-check code LDPC:

Acquiring data stored in a first type of register in the NAND FLASH controller, and determining that no abnormality occurs in the first type of register in the NAND FLASH controller when the data stored in the first type of register meets a first preset condition, wherein the data contained in the first type of register is preset and cannot be modified; and/or

Writing first preset data into a second type of register in the NAND FLASH controller; acquiring data stored in a second type of register in the NANDFlash controller, and determining that no abnormality occurs in the second type of register in the NAND FLASH controller if the data stored in the second type of register is the first preset data, wherein the second type of register allows data to be written and allows the data stored therein to be read; and/or

Writing second preset data into a third type of register in the NAND FLASH controller; acquiring data stored in the third type of register in the NANDFlash controller, and determining that no abnormality occurs in the third type of register in the NAND FLASH controller if the data stored in the third type of register is third preset data, wherein the corresponding bit of the third type of register is cleared after the third type of register is written in the second preset data.

3. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The method further includes, before the instructing the nonvolatile flash memory NAND FLASH controller in the solid-state disk SSD to write the target data to the specified storage block in NAND FLASH using the low-density parity-check code LDPC:

instruct the NAND FLASH controller to erase the data stored in the specified storage block;

The instructing the nonvolatile flash memory NAND FLASH controller in the solid state disk SSD to write the target data into the specified storage block in NAND FLASH using the low density parity check code LDPC includes:

the NAND FLASH controller is instructed to write target data to one or more specified pages in a specified memory block in the NAND FLASH using LDPC, wherein the one or more specified pages include the target page.

4. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The instructing the NAND FLASH controller to obtain the specified data from the specified storage block includes:

And sending a soft solution instruction to the NAND FLASH controller to instruct the NAND FLASH controller to acquire specified data from the specified storage block.

5. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The instructing the NAND FLASH controller to obtain the specified data from the specified storage block includes:

Instruct the NAND FLASH controller to send a read instruction to the NAND FLASH to read target sub-data from the specified storage block, where the target sub-data is data obtained after decoding the original data using the LDPC;

Setting a target bit value in the state data to a preset value under the condition that the state data sent by the NAND FLASH in response to the read instruction is acquired, wherein the target bit value is the preset value and is used for indicating that the read data is wrong, and acquiring the specified data from the specified storage block by the NANDflash controller under the condition that the NANDflash controller determines that the target bit value in the state data is the preset value.

6. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The step of performing error injection on the original data to obtain error data comprises the following steps:

determining N target bits from the original data, wherein the original data has M bits, the M bits comprise the N target bits, and the ratio of N to M is smaller than a preset threshold;

And carrying out data inversion on the data of the original data on each target bit in the N target bits.

7. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The verifying the soft decoding function of the NAND FLASH controller according to the soft decoding result includes:

Under the condition that the Cyclic Redundancy Check (CRC) check value and the Error Correction Code (ECC) check value in the soft decoding result are both zero, determining that the soft decoding function of the NAND FLASH controller is normal;

Determining that the soft decoding function of the NAND FLASH controller is abnormal under the condition that the CRC value in the soft decoding result is not zero;

And determining that the soft decoding function of the NAND FLASH controller is abnormal under the condition that the ECC check value in the soft decoding result is not zero.

8. A soft decoding function verifying device is characterized in that,

Comprising the following steps:

a writing module, configured to instruct a nonvolatile flash memory NAND FLASH controller in a solid state disk SSD to write target data into a specified storage block in NAND FLASH using a low-density parity-check code LDPC;

The acquiring module is configured to instruct the NANDFlash controller to acquire specified data from the specified storage block, where the specified data includes: raw data, soft bit data and paired page data; the original data is data after the LDPC coding stored in a target page in the specified storage block, the soft bit data is data generated in the process of storing the original data by NAND FLASH, and the pair-page data is data stored in a page adjacent to the target page in the specified storage block;

The error injection module is used for performing error injection on the original data to obtain error data;

The soft decoding module is used for indicating the NAND FLASH controller to carry out soft decoding on the error data according to the soft bit data and the paired page data to obtain a soft decoding result;

and the verification module is used for verifying the soft decoding function of the NAND FLASH controller according to the soft decoding result.

9. A computer-readable storage medium comprising,

The computer readable storage medium has stored therein a computer program, wherein the computer program when executed by a processor realizes the steps of the method as claimed in any of claims 1 to 7.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that,

The processor, when executing the computer program, implements the steps of the method as claimed in any one of claims 1 to 7.