CN118897183B - Side scan circuit and chip based on special scan chain architecture characteristics - Google Patents
Side scan circuit and chip based on special scan chain architecture characteristicsInfo
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- CN118897183B CN118897183B CN202410913241.9A CN202410913241A CN118897183B CN 118897183 B CN118897183 B CN 118897183B CN 202410913241 A CN202410913241 A CN 202410913241A CN 118897183 B CN118897183 B CN 118897183B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31901—Analysis of tester Performance; Tester characterization
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31915—In-circuit Testers
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- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
本发明主要用于数字电路技术领域。本发明公开了一种基于特殊扫描链架构特征的边路扫描电路及芯片，该边路扫描电路包括连接组件以及多个扫描链；每个扫描链均包括至少一个处于第一状态或第二状态的节点连接端；每个扫描链的处于第一状态的节点连接端按照预设连接关系相互连接；每个扫描链的处于第二状态的节点连接端，通过连接组件，与目标扫描链的处于第一状态或第二状态的节点连接端连接。本发明的技术方案能够为实现边路扫描链故障诊断提供新的硬件电路解决方案，从而更灵活地进行故障诊断。
The present invention is mainly used in the field of digital circuit technology. The present invention discloses a side scan circuit and chip based on special scan chain architecture features. The side scan circuit includes a connection component and multiple scan chains; each scan chain includes at least one node connection end in a first state or a second state; the node connection ends in the first state of each scan chain are interconnected according to a preset connection relationship; the node connection ends in the second state of each scan chain are connected to the node connection ends in the first state or the second state of the target scan chain through the connection component. The technical solution of the present invention can provide a new hardware circuit solution for implementing side scan chain fault diagnosis, thereby performing fault diagnosis more flexibly.
Description
Technical Field
The invention relates to the technical field of digital circuits, in particular to an edge scanning circuit and a chip based on special scanning chain architecture characteristics.
Background
In the existing fault diagnosis scheme of the side-path scan chain, the side-path scan chain can be divided into a plurality of groups according to the constraint of clock domains or layout and wiring. By inserting a circulating side path transmission path on the scan chain in each group, it is ensured that the test vector of each scan chain with a fault (short for bad chain) can be transmitted to one or more scan chains without a fault (short for good chain), and the bad chain also captures the test vector transmitted by the good chain. The scheme realizes manageable hardware overhead, efficient and accurate fault diagnosis and flexible self-adaptive diagnosis.
In the side-path scanning circuit composed of a plurality of side-path scanning chains, the number of the scanning chains is limited in a specific way according to the optimal circuit design, and the length of each scanning chain is the same, so that a circulating transmission path is formed at the joint of each unit without adding an additional circuit. However, an actual side-scan circuit cannot fully realize an optimal circuit design. How to provide an edge scan circuit that can achieve fault diagnosis is still a problem that one skilled in the art needs to solve when the optimal circuit design cannot be achieved due to the objective conditions.
Disclosure of Invention
The invention provides an edge scanning circuit and a chip based on special scanning chain architecture characteristics, which can provide a new hardware circuit solution for realizing the fault diagnosis of an edge scanning chain, thereby more flexibly carrying out the fault diagnosis.
In order to achieve the above object, in a first aspect, the present invention provides an edge scan circuit based on a special scan chain architecture feature, where the edge scan circuit includes a connection component and a plurality of scan chains;
Each scan chain comprises at least one node connection in a first state or a second state;
the node connecting ends of each scanning chain in the first state are connected with each other according to a preset connection relation;
And the node connecting end of each scanning chain in the second state is connected with the node connecting end of the target scanning chain in the first state or the second state through the connecting component.
Optionally, the number of the scanning chains in the side path scanning circuit takes any odd number larger than 1;
the connection assembly includes at least one first inverter;
The node connecting end of the scanning chain in the second state is connected with the node connecting end of the target scanning chain in the first state through the first phase inverter.
Optionally, the connection assembly includes a plurality of first inverters;
Each scanning chain comprises a plurality of scanning units connected in series, and each scanning unit comprises a first connecting end and a second connecting end;
The first connecting end of the scanning unit in the scanning chain is used as a node connecting end of the scanning chain in a first state, and the second connecting end of the scanning unit in the scanning chain is used as a node connecting end of the scanning chain in a second state;
the input end of each first inverter is used for being connected with the second connecting end of the target scanning unit, and the output end of each first inverter is used for being connected with the first connecting end of the target scanning unit.
Optionally, each scan chain includes a first node connection in a first state or a second state, and a second node connection in the first state or the second state;
Each scanning chain is ordered according to a first preset sequence;
The first node connecting end of the last scanning chain in the first preset sequence in the first state is connected with the second node connecting end of the previous scanning chain in the first state;
The second node connecting end of the last scanning chain in the second state in the first preset sequence is connected with the input end of the first phase inverter;
the output end of the first inverter is connected with the first node connecting end of the first scanning chain in the first preset sequence, wherein the first node connecting end is in a first state.
Optionally, the side-path scanning circuit includes a long scanning chain and a short scanning chain, the length of the long scanning chain is greater than the length of the short scanning chain;
the long scan chain comprises a node connection end in a first state and a node connection end in a second state;
Each node connecting end in the short scanning chain is a node connecting end in a first state;
and the node connecting end of the long scanning chain in the second state is used for being connected with the node connecting end of the short scanning chain in the first state through the connecting component.
Optionally, the connection component includes at least one exclusive or gate logic operator;
The long scanning chain or the short scanning chain comprises a plurality of scanning units which are connected in series, and each scanning unit comprises a first connecting end and a second connecting end;
the second connecting end of the target scanning unit in the long scanning chain is used as a node connecting end of the long scanning chain in a second state and is connected with the input end of the exclusive-or gate logic arithmetic unit;
The first connecting end of each scanning unit in the short scanning chain is used as a node connecting end of the short scanning chain in a first state;
the output end of the exclusive-or gate logic operator is connected with the first connecting end of the target scanning unit in the short scanning chain.
Optionally, each scan chain is ordered according to a second preset sequence, and each scan unit in the scan chain is ordered according to a third preset sequence;
in the second preset sequence, the previous scanning chain is a long scanning chain, the next scanning chain is a short scanning chain, and the second connecting ends of the last three scanning units in the previous scanning chain, which are ordered according to the third preset sequence, are all connected with the first connecting end of the last scanning unit in the next scanning chain, which is ordered according to the third preset sequence, through the exclusive-or gate logic arithmetic unit, or,
In the second preset sequence, the former scanning chain is a short scanning chain, the latter scanning chain is a long scanning chain, and the second connecting end of the last scanning unit sequenced according to the third preset sequence in the former scanning chain is connected with the first connecting ends of the last two scanning units sequenced according to the third preset sequence in the latter scanning chain.
Optionally, the side path scanning circuit further comprises a plurality of long scanning chains;
the node connecting end of the long scanning chain in the second state is also used for being connected with the node connecting end of the target long scanning chain in the second state through the connecting component;
The connection assembly comprises at least one second inverter;
each long scanning chain comprises a plurality of scanning units connected in series, and each scanning unit comprises a first connecting end and a second connecting end;
The second connecting end of the target scanning unit in the long scanning chain is used as a node connecting end of the long scanning chain in a second state and is connected with the input end of the second phase inverter;
And a first connecting end of a target scanning unit in the target long scanning chain is used as a node connecting end of the target long scanning chain in a second state and is connected with the output end of the second phase inverter.
Optionally, each scan chain is ordered according to a fourth preset sequence, and each scan unit in the scan chain is ordered according to a fifth preset sequence;
in the fourth preset sequence, at least one short scan chain is arranged between two long scan chains, and the second connection end of the last scan unit in the previous long scan chain arranged according to the fifth preset sequence is connected with the first connection end of the last scan unit in the next long scan chain arranged according to the fifth preset sequence through the second inverter.
In a second aspect, the present invention further provides a chip, including any one of the above-mentioned side-scan circuits based on special scan chain architecture features.
The invention has at least the following beneficial effects:
The technical scheme of the application provides an edge scanning circuit based on special scanning chain architecture characteristics, which comprises a connecting component and a plurality of scanning chains, wherein each scanning chain comprises at least one node connecting end in a first state or a second state, the node connecting ends in the first state of each scanning chain are mutually connected according to a preset connection relation, and the node connecting end in the second state of each scanning chain is connected with the node connecting end in the first state or the second state of a target scanning chain through the connecting component. Therefore, the novel side-path scanning circuit provided by the technical scheme of the application has the advantages of less devices, contribution to reducing hardware cost, simple connection relation among devices, contribution to simplifying wiring, capability of transmitting input signals for diagnosing faults between each scanning chain and the connecting component, and capability of accurately identifying and positioning faults according to the input signals which are freely transmitted without barriers in any part of any scanning chain under the condition that any part of any scanning chain breaks down, thereby realizing fault diagnosis of the side-path scanning chain.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate and do not limit the invention.
FIG. 1 is a schematic diagram of an edge scan circuit based on special scan chain architecture features;
FIG. 2 is a schematic diagram of a first side scan circuit including a plurality of scan cells;
FIG. 3 is a schematic diagram of a first side scan circuit including a single bit flip-flop and a connector;
FIG. 4 is a schematic diagram of a second side-scan circuit including a plurality of scan cells;
FIG. 5 is a schematic diagram of a second side scan circuit including a single bit flip-flop and a connector;
FIG. 6 is a schematic diagram of a third side scan circuit including a plurality of scan cells;
FIG. 7 is a schematic diagram of a third side-scan circuit including a single bit flip-flop and a connector;
FIG. 8 is a schematic diagram of a chip including a side-scan circuit based on special scan chain architecture features.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Before describing embodiments of the present application in detail, some of the terms and expressions that are referred to in the embodiments of the present application will be described first, and the terms and expressions that are referred to in the embodiments of the present application are applicable to the following explanation.
In an edge scan circuit composed of a plurality of edge scan chains, when the edge scan architecture divides the plurality of scan chains into a plurality of scan chain groups, the following suggestions should be preferably followed in order to ensure the maximization of the test coverage:
all chains in a group should have the same length so that the circular transmission path at each cell index can be easily implemented without adding additional circuitry.
The number of chains per chain set should be even and equal to or greater than 4.
This circuit design facilitates the formation of a cyclical transmission path at each cell junction without the addition of additional circuitry. However, an actual side-scan circuit cannot fully realize an optimal circuit design. How to provide an edge scan circuit that can achieve fault diagnosis is still a problem that one skilled in the art needs to solve when the optimal circuit design cannot be achieved due to the objective conditions.
In order to solve the problems, the technical scheme of the application provides an edge scanning circuit based on special scanning chain architecture characteristics, which comprises a connecting component and a plurality of scanning chains, wherein each scanning chain comprises at least one node connecting end in a first state or a second state, the node connecting ends in the first state of each scanning chain are mutually connected according to a preset connection relation, and the node connecting end in the second state of each scanning chain is connected with the node connecting end in the first state or the second state of a target scanning chain through the connecting component. Therefore, the novel side-path scanning circuit provided by the technical scheme of the application has the advantages of less devices, contribution to reducing hardware cost, simple connection relation among devices, contribution to simplifying wiring, capability of transmitting input signals for diagnosing faults between each scanning chain and the connecting component, and capability of accurately identifying and positioning faults according to the input signals which are freely transmitted without barriers in any part of any scanning chain under the condition that any part of any scanning chain breaks down, thereby realizing fault diagnosis of the side-path scanning chain.
The embodiments provided by the technical scheme of the application are as follows:
referring to fig. 1, fig. 1 is a schematic diagram of a side-path scanning circuit based on special scan chain architecture features.
In a first aspect, the present invention provides an embodiment, where the embodiment provides an edge scan circuit based on a special scan chain architecture feature, where the edge scan circuit includes a connection component and a plurality of scan chains, each scan chain includes at least one node connection end in a first state or a second state, the node connection ends in the first state of each scan chain are connected to each other according to a preset connection relationship, and the node connection end in the second state of each scan chain is connected to the node connection end in the first state or the second state of the target scan chain through the connection component.
In this embodiment, the first state refers to a state in which the current node connection end has a corresponding connection relationship with another node connection end and can be normally connected, and the second state refers to a state in which the current node connection end has no corresponding connection relationship with other node connection ends and can not be normally connected when being connected with other node connection ends.
In a specific embodiment, the side-path scanning circuit includes a connection component and 3 scan chains, where all node connection ends in two scan chains are in a first state, and each node connection end in the two scan chains is in a corresponding relationship, for example, each of the three scan chains has only one node connection end, and then the node connection end of the first scan chain is connected to the second scan chain, and the node connection end of the second scan chain is connected to the third scan chain. In this embodiment, the node connection end of the third scan chain is a node connection end in the second state, and after the node connection end of the third scan chain is connected to the connection component, the connection component is connected to the first scan chain or the second scan chain.
In some embodiments, the number of scan chains in the side scan circuit is any odd number greater than 1, the connection component comprises at least one first inverter, and the node connection end of the scan chain in the second state is connected with the node connection end of the target scan chain in the first state through the first inverter.
In some embodiments, the side-scan circuit includes three scan chains, the node connection of the first scan chain in the second state is connected to one end of the first inverter, the other end of the first inverter is connected to the node connection of the second scan chain in the first state, and the node connection of the third scan chain is connected to the second scan chain.
It can be appreciated that, compared with a complex xor gate structure, the present embodiment adopts an inverter as a connection component, which reduces hardware overhead, simplifies wiring, reduces signal delay and interference, improves signal integrity, and further reduces power consumption.
In some embodiments, the scan chain has a plurality of node connections, e.g., node connection A1 in scan chain A is connected to node connection B1 in scan chain B, node connection A2 in scan chain A is connected to node connection B2 in scan chain B, and so on, each node connection on scan chain A, B is connected in the connection described above. If each node connection end in the scan chain C is a node connection end in the second state, each node connection end in the scan chain C needs to be connected with a plurality of inverters in one-to-one correspondence, and then each inverter is connected with each node connection end in the scan chain a or B in one-to-one correspondence. For example, the node connection terminal C1 in the scan chain C is connected to the inverter D1, the node connection terminal C2 in the scan chain C is connected to the inverter D2, and so on, each node connection terminal in the scan chain C is connected to the corresponding inverter, then the inverter D1 is connected to the node connection terminal A1 in the scan chain a or the node connection terminal B1 in the scan chain B, the inverter D2 is connected to the node connection terminal A2 in the scan chain a or the node connection terminal B2 in the scan chain B, and so on, until each node connection terminal in the scan chain C is connected to the node connection terminal of the scan chain a or the scan chain B through the inverter.
In some embodiments, each scan chain includes a first node connection in a first state or a second state and a second node connection in the first state or the second state, each scan chain is ordered according to a first preset order, the first node connection in the first state of the last scan chain in the first preset order is connected with the second node connection in the first state of the previous scan chain, the second node connection in the second state of the last scan chain in the first preset order is connected with the input of a first inverter, and the output of the first inverter is connected with the first node connection in the first state of the first scan chain in the first preset order.
In some embodiments, the connection assembly comprises a plurality of first inverters, each scan chain comprises a plurality of scan cells connected in series, each scan cell comprises a first connection end and a second connection end, the first connection ends of the scan cells in the scan chain serve as node connection ends of the scan chain in a first state, the second connection ends of the scan cells in the scan chain serve as node connection ends of the scan chain in a second state, the input ends of the first inverters are used for being connected with the second connection ends of target scan cells, and the output ends of the first inverters are used for being connected with the first connection ends of the target scan cells.
It will be appreciated that in a scan chain, each series of scan cells is arranged in a series order. For example, there are five scan cells in a scan chain, which are connected in series in such a way that the output of the previous scan cell is connected to the input of the next scan cell. In this order, the input of the first scan cell serves as the input of the scan chain, the input signal is input by the input of the scan chain, then sequentially transmitted to each scan cell, and finally, the input signal is output from the output of the last scan cell, i.e., from the output of the scan chain.
It can be understood that in this embodiment, the scan chain is divided into a plurality of scan cells, and the first connection end and the second connection end of each scan cell are both used as node connection ends of the scan chain, and meanwhile, an equal number of inverters are configured based on the correspondence between the scan cells and the inverters, which is beneficial to locking the faulty portion of the scan chain more easily by detecting the faulty scan cell during the transmission process of the input signal in each scan cell of the scan chain.
Referring to fig. 2, the side-path scanning circuit in the present embodiment includes 5 scan chains, which are sequentially arranged from top to bottom according to a first predetermined sequence, respectively a scanning Chain10, a scanning Chain11 scan Chain12, scan Chain13 scan Chain14.Scan_in0, scan_in1, scan_in2, scan_in3, scan_in4 are input to Scan Chain Chain10, respectively Scan Chain11, scan Chain12, scan Chain13 the signal of Scan Chain14 for fault diagnosis, scan_en and side_tr are respectively an enable signal and a side select signal transmitted to each Scan cell. Each scan chain comprises 8 scan cells, as seen from the left to right direction, the input end of the first scan cell is used as the input end of the scan chain, the output end of the former scan cell is connected with the input end of the latter scan cell, and the output end of the last scan cell is used as the output end of the scan chain, so that each scan cell is connected in series. Each scan chain includes a plurality of first node connection terminals and a plurality of second node connection terminals, the first connection terminal of each scan cell is used as the first node connection terminal, and the second connection terminal of each scan cell is used as the second node connection terminal. Scan Chain10, scan Chain11 scan Chain12 the first node connection and the second node connection of scan Chain13 are all in a first state, only the first node connection of scan Chain14 is in the first state and the second node connection of scan Chain14 is in the second state. As shown in the top-down direction, the second node connection of the first scan Chain10 is connected to the first node connection of scan Chain11, and so on, the second node connection end of the last scan Chain14 is connected with the first node connection end of the first scan Chain10 through the first inverter.
It will be appreciated that in this embodiment, since each scan chain and each scan cell are arranged in order, when a portion (scan cell) of the scan chain fails, it is easier to lock the position where the failure occurs.
In some embodiments, each scanning unit comprises a single-bit trigger and a connector, wherein an input end of the single-bit trigger is connected with an output end of the connector, the input end of the single-bit trigger is used as a second connection end of the scanning unit, and the input end of the connector is used as a first connection end of the scanning unit.
Referring to fig. 3, fig. 3 is a schematic diagram of a first side scan circuit including a single bit flip-flop and a connector.
The application also provides a specific embodiment for realizing fault diagnosis by utilizing the side-path scanning circuit shown in fig. 3. In this embodiment, the side scan circuit includes five scan chains with equal length, denoted as scan chain 0, scan chain 1, scan chain 2, scan chain 3, and scan chain 4, each of which includes 8 scan cells. Scan_in0, scan_in1, scan_in2, scan_in3, scan_in4 are test vectors for fault diagnosis input to 5 Scan chains, respectively, and scan_en, side_tr are enable signals and side select signals transmitted to each Scan cell, respectively. In which an inverter is inserted in the side transmission path of the scan chain 4 to the scan chain 1. To verify the validity of this structure, it is assumed that a Stuck-at 0 fault occurs in the scan cell 3 of the scan chain 4, this position being affected by the inverter on its path at the time of the edge transmission. Then, the fault diagnosis is performed by using the method in the prior art scheme. The individual process test vectors are shown in table 1. From the correlation deductions, the results prove that the faults can be accurately diagnosed and positioned.
TABLE 1 test vector table for first failure diagnosis case
In some embodiments, the side-path scanning circuit comprises a long scanning chain and a short scanning chain, wherein the length of the long scanning chain is larger than that of the short scanning chain, the long scanning chain comprises a node connecting end in a first state and a node connecting end in a second state, each node connecting end in the short scanning chain is a node connecting end in the first state, and the node connecting end in the second state of the long scanning chain is used for being connected with the node connecting end in the first state of the short scanning chain through a connecting component.
In a specific embodiment, the side-path scanning circuit includes a connection component and 3 scan chains, where two scan chains are long scan chains, and one scan chain is a short scan chain, and all node connection ends are in a first state, where each node connection end of the two long scan chains is in a corresponding relationship, for example, the three scan chains have only one node connection end, and the node connection end of the first long scan chain is a node connection end in the first state and is connected to the second long scan chain, and the node connection end of the second long scan chain is a node connection end in the second state and is connected to the short scan chain through the connection component, where the node connection end of the short scan chain is connected to the first long scan chain.
It can be understood that the side-path scanning circuit of the embodiment is a scheme for optimizing the structure for processing the scan chains with different lengths in the prior art, occupies less chip area in physical implementation, reduces hardware overhead, simplifies the layout and wiring of the circuit, and reduces potential signal delay and interference problems, thereby improving signal integrity.
In some embodiments, the connection assembly comprises at least one exclusive-or gate logic operator, the long scan chain or the short scan chain each comprises a plurality of scan cells connected in series, each scan cell comprises a first connection end and a second connection end, the second connection end of the target scan cell in the long scan chain is used as a node connection end of the long scan chain in a second state and is connected with the input end of the exclusive-or gate logic operator, the first connection end of each scan cell in the short scan chain is used as a node connection end of the short scan chain in a first state, and the output end of the exclusive-or gate logic operator is connected with the first connection end of the target scan cell in the short scan chain.
In one embodiment, the side-scan circuit includes 4 scan chains, long scan chain A, long scan chain B, short scan chain C, and short scan chain D, respectively. The first connection end of each scanning unit is used as a first node connection end of the scanning chain, the second connection end of each scanning unit is used as a second node connection end of the scanning chain, for example, in a long scanning chain A, first node connection ends A11, A12 and A13 are used, has second node connection terminals A21, A22 a23. the long scan chain a node connection a11 is connected to the long scan chain B node connection B11, the node connection a12 in the long scan chain a is connected to the node connection B12 in the long scan chain B, and so on, each node connection on the long scan chain A, B is connected according to the connection relationship described above. The node connection end B21 in the long scan chain B is connected with the node connection end C11 in the short scan chain C, the node connection end B22 in the long scan chain B is connected with the node connection end C12 in the short scan chain C, and so on, since the long scan chain B and the short scan chain C are different in length, there are more scan cells in the long scan chain B than the short scan chain C, and therefore, there are scan cells in the long scan chain B that cannot be connected with the scan cells in the short scan chain in the above manner, it is required that the scan cells that cannot be individually connected in the above manner are target scan cells, and the second connection end of the target scan cells is the node connection end in the second state, and is connected with the first node connection end in the short scan chain C through the exclusive nor gate logic operator. Since the lengths of the short scan chain C and the short scan chain D are the same, and the scan cells in the chains are the same, the connection is performed in the above manner, and thus, the description is not repeated.
It can be appreciated that, compared with the complex xor gate structure, the embodiment adopts the xor gate logic operator as the connection component, the hardware cost is reduced, the wiring is simplified, the signal delay and the interference are reduced, the signal integrity is improved, and the power consumption is further reduced.
In some embodiments, each scan chain is ordered according to a second preset order, and each scan unit in the scan chain is ordered according to a third preset order, in the second preset order, the previous scan chain is a long scan chain, the next scan chain is a short scan chain, and the second connection ends of the last three scan units ordered according to the third preset order in the previous scan chain are all connected to the first connection end of the last scan unit ordered according to the third preset order in the next scan chain through an exclusive or gate logic operator, or in the second preset order, the previous scan chain is a short scan chain, the next scan chain is a long scan chain, and the second connection end of the last scan unit ordered according to the third preset order in the previous scan chain is connected to the first connection end of the last two scan units ordered according to the third preset order in the next scan chain.
Preferably, the exclusive-or gate logic operator is a three-input exclusive-or gate logic operator.
Referring to fig. 4, the side-path scanning circuit of the present embodiment includes 4 scan chains, according to a second predetermined sequence, the 4 scan chains are sequentially arranged from top to bottom and are respectively a scan Chain20, a scan Chain21, a scan Chain22 and a scan Chain23. Each scan chain comprises 8 scan cells, as seen from the left to right direction, the input end of the first scan cell is used as the input end of the scan chain, the output end of the former scan cell is connected with the input end of the latter scan cell, and the output end of the last scan cell is used as the output end of the scan chain, so that each scan cell is connected in series. Each scan chain includes a plurality of first node connection terminals and a plurality of second node connection terminals, the first connection terminal of each scan cell is used as the first node connection terminal, and the second connection terminal of each scan cell is used as the second node connection terminal. In particular, scan Chain20, scan Chain21, scan Chain23 are all long scan chains, scan Chain22 is a short scan Chain. In the scan Chain21, the second connecting ends of the last three scan units (namely, the last three scan units from left to right in the second row in the figure) are used as node connecting ends of the scan Chain21 in the second state and are connected with the input ends of three input exclusive-or gate logic operators, and the output ends of the exclusive-or gate logic operators are connected with the first connecting ends of the last scan unit of the scan Chain22 (namely, the last three scan units from left to right in the figure); the second connection end of the last scanning unit of the scanning Chain22 is respectively connected with the first connection ends of the last two scanning units (namely the last scanning unit of the fourth row from left to right in the figure), the first connection ends of the last two scanning units of the scanning Chain23 serve as node connection ends of the scanning Chain23 in a second state.
It will be appreciated that in this embodiment, since each scan chain and each scan cell are arranged in order, when a portion (scan cell) of the scan chain fails, it is easier to lock the position where the failure occurs.
In some embodiments, each scanning unit comprises a single-bit trigger and a connector, wherein an input end of the single-bit trigger is connected with an output end of the connector, the input end of the single-bit trigger is used as a second connection end of the scanning unit, and the input end of the connector is used as a first connection end of the scanning unit.
Referring to fig. 5, fig. 5 is a schematic diagram of a second side scan circuit including a single bit flip-flop and a connector.
The application also provides a specific embodiment for realizing fault diagnosis by utilizing the side-path scanning circuit shown in fig. 5. In this embodiment, the side-path scanning circuit of this embodiment includes four scan chains, which are denoted as scan chain 0, scan chain 1, scan chain 2, scan chain 3, and scan chain 4. Wherein each of the scan chains 0,1, and 3 includes 8 scan cells, and the scan chain 2 includes 7 scan cells. Scan_in0, scan_in1, scan_in2, scan_in3 are test vectors for fault diagnosis input to 4 Scan chains, respectively, and scan_en, side_tr are enable signals and side select signals transmitted to each Scan cell, respectively. A three-input exclusive-or gate logic arithmetic unit is added to the side transmission path of the last scanning unit of the short scanning chain 2 from the last three scanning units of the long scanning chain 1. To verify the validity of this structure, it is assumed that a Stuck-at 0 fault occurs in the scan cells of scan chain 1, this location being connected to an intervening three-input exclusive-or gate, the signals of the scan cells of short scan chain 2 may be transmitted to long scan chain 3 when transmitted by short scan chain 2 to long scan chain 3. Then, the fault diagnosis is performed by using the method in the prior art scheme. The associated individual process test vectors are shown in table 2. From the correlation derivation (edge failure when three intersections occur, only three intersection sets are taken at the moment), and the result proves that faults can be accurately diagnosed and positioned.
TABLE 2 test vector table for the second failure diagnosis case
In some embodiments, the side-path scan circuit further comprises a plurality of long scan chains, the node connection end of the long scan chain in the second state is further used for being connected with the node connection end of the target long scan chain in the second state through a connection component, the connection component comprises at least one second inverter, each long scan chain comprises a plurality of scan units connected in series, each scan unit comprises a first connection end and a second connection end, the second connection end of the target scan unit in the long scan chain is used as the node connection end of the long scan chain in the second state and is connected with the input end of the second inverter, and the first connection end of the target scan unit in the target long scan chain is used as the node connection end of the target long scan chain in the second state and is connected with the output end of the second inverter.
In a specific embodiment, the side-path scan circuit includes 4 scan chains, namely a long scan chain a, a short scan chain B, a short scan chain C, and a long scan chain D. The first connection end of each scanning unit is used as a first node connection end of the scanning chain, the second connection end of each scanning unit is used as a second node connection end of the scanning chain, for example, in a long scanning chain A, first node connection ends A11, A12 and A13 are used, has second node connection terminals A21, A22 a23. the long scan chain a has node connection a11 connected to node connection B11 in the short scan chain B, the node connection a12 in the long scan chain a is connected to the node connection B12 in the short scan chain B, and so on, each node connection on the long scan chain A, B is connected according to the connection relationship described above. Since the length of the long scan chain a is greater than that of the short scan chain B. Therefore, the second connection end of at least one scanning unit in the long scanning chain a cannot be connected with the first connection end of the scanning unit in the short scanning chain B according to the connection relationship, and the second connection end of the scanning unit of the long scanning chain a is the node connection end of the long scanning chain a in the second state, and the scanning unit of the long scanning chain a is used as the target scanning unit of the long scanning chain a. Similarly, there is also at least one first connection end of the scan cell in the long scan chain D that cannot be connected to the second connection end of the scan cell in the short scan chain B according to the connection relationship, where the first connection end of the scan cell is used as a node connection end of the long scan chain D in the second state, and the scan cell of the long scan chain D is used as a target scan cell of the long scan chain D. The second connection end of the target scanning unit of the long scanning chain A is connected with the first connection end of the target scanning unit of the long scanning chain D through a second inverter.
It can be appreciated that, compared with a complex xor gate structure, the present embodiment adopts an inverter as a connection component, which reduces hardware overhead, simplifies wiring, reduces signal delay and interference, improves signal integrity, and further reduces power consumption.
In some embodiments, each scan chain is ordered according to a fourth preset order, and each scan unit in the scan chain is ordered according to a fifth preset order, in the fourth preset order, at least one short scan chain is ordered between two long scan chains, and the second connection end of the last scan unit in the previous long scan chain ordered according to the fifth preset order is connected with the first connection end of the last scan unit in the next long scan chain ordered according to the fifth preset order through a second inverter.
Referring to fig. 6, the side-path scanning circuit of the present embodiment includes 4 scan chains, according to a second predetermined sequence, the 4 scan chains are sequentially arranged from top to bottom and are respectively a scan Chain30, a scan Chain31, a scan Chain32 and a scan Chain33. Each scan chain comprises 8 scan cells, as seen from the left to right direction, the input end of the first scan cell is used as the input end of the scan chain, the output end of the former scan cell is connected with the input end of the latter scan cell, and the output end of the last scan cell is used as the output end of the scan chain, so that each scan cell is connected in series. Each scan chain includes a plurality of first node connection terminals and a plurality of second node connection terminals, the first connection terminal of each scan cell is used as the first node connection terminal, and the second connection terminal of each scan cell is used as the second node connection terminal. In particular, scan Chain30, scan Chain31, scan Chain33 are all long scan chains, scan Chain32 is a short scan Chain. In the scan Chain31, the second connection end of the last scan unit (i.e., the first last scan unit in the second row from left to right in the figure) connected in series according to the third preset sequence is used as the node connection end of the scan Chain31 in the second state, and is connected with the input end of the second inverter, and the output end of the second inverter is connected with the first connection end of the last scan unit of the scan Chain33 (i.e., the first last scan unit in the fourth row from left to right in the figure).
It will be appreciated that in this embodiment, since each scan chain and each scan cell are arranged in order, when a portion (scan cell) of the scan chain fails, it is easier to lock the position where the failure occurs.
In some embodiments, each scanning unit comprises a single-bit trigger and a connector, wherein an input end of the single-bit trigger is connected with an output end of the connector, the input end of the single-bit trigger is used as a second connection end of the scanning unit, and the input end of the connector is used as a first connection end of the scanning unit.
Referring to fig. 7, fig. 7 is a schematic diagram of a third side scan circuit including a single bit flip-flop and a connector.
The application also provides a specific embodiment for realizing fault diagnosis by utilizing the side-path scanning circuit shown in fig. 7. In this embodiment, the side-path scanning circuit of this embodiment includes four scan chains, which are denoted as scan chain 0, scan chain 1, scan chain 2, and scan chain 3. Wherein each of the scan chains 0, 1, and 3 includes 8 scan cells, and the scan chain 2 includes 7 scan cells. Scan_in0, scan_in1, scan_in2, scan_in3 are test vectors for fault diagnosis input to 4 Scan chains, respectively, and scan_en, side_tr are enable signals and side select signals transmitted to each Scan cell, respectively. When signals are transmitted from the short scanning chain 2 to the long scanning chain 3, the signals of the short scanning units can be transmitted to the scanning units of the long scanning chain 3, when the long scanning chain 1 carries out side-path transmission to the short scanning chain 2, 7 scanning units in the long scanning chain 1 are respectively connected with the 7 scanning units of the short scanning chain, and the last scanning unit in the long scanning chain 1 skips the short scanning chain 2 and is connected with the last scanning unit of the next long scanning chain 3 with equal length through a second inverter. To verify the validity of this structure, it is assumed that a Stuck-at 0 fault occurs in the scan cell of scan chain 1, which is connected to the inserted inverter.
When the method in the prior art scheme is applied to fault diagnosis, partial change is needed, if the long scanning chain 1 is identified to have faults, two complementary test vectors which are transmitted and carried out by the side path are normal, and then the fault can be judged to be at the last scanning unit of the long scanning chain. The associated individual process test vectors are shown in table 3. The results prove that the faults can be accurately diagnosed and positioned.
TABLE 3 test vector table for third failure diagnosis case
In a second aspect, referring to fig. 8, fig. 8 is a schematic diagram of a chip including an edge scan circuit based on special scan chain architecture features.
The present embodiment provides a chip, including the edge scan circuit based on the special scan chain architecture feature of any one of the above embodiments.
It can be understood that the content of the above-mentioned circuit embodiment is applicable to the present chip embodiment, and the specific functions of the present chip embodiment are the same as those of the above-mentioned circuit embodiment, and the achieved beneficial effects are the same as those of the above-mentioned circuit embodiment.
The terms "first," "second," "third," "fourth," and the like in the description of the application and in the above figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "and/or" is used to describe an association relationship of an associated object, and indicates that three relationships may exist, for example, "a and/or B" may indicate that only a exists, only B exists, and three cases of a and B exist simultaneously, where a and B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one of a, b or c may represent a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
While the present application has been described in considerable detail and with particularity with respect to several described embodiments, it is not intended to be limited to any such detail or embodiments or any particular embodiment, but is to be considered as providing a broad interpretation of such claims by reference to the appended claims in light of the prior art and thus effectively covering the intended scope of the application. Furthermore, the foregoing description of the application has been presented in its embodiments contemplated by the inventors for the purpose of providing a useful description, and for the purposes of providing a non-essential modification of the application that may not be presently contemplated, may represent an equivalent modification of the application.
Claims (9)
1. An edge scanning circuit based on special scanning chain architecture features is characterized by comprising a connecting component and a plurality of scanning chains;
Each scanning chain comprises at least one node connecting end in a first state or a second state, wherein the first state is a normal connecting state in which the current node connecting end and the other node connecting end have corresponding connection relations;
the node connecting ends of each scanning chain in the first state are connected with each other according to a preset connection relation;
the node connecting end of each scanning chain in the second state is connected with the node connecting end of the target scanning chain in the first state or the second state through the connecting component;
the number of the scanning chains in the side path scanning circuit is any odd number which is larger than 1;
the connection assembly includes at least one first inverter;
The node connecting end of the scanning chain in the second state is connected with the node connecting end of the target scanning chain in the first state through the first phase inverter.
2. The side-scan circuit based on a special scan chain architecture feature of claim 1, wherein the connection component comprises a plurality of first inverters;
Each scanning chain comprises a plurality of scanning units connected in series, and each scanning unit comprises a first connecting end and a second connecting end;
The first connecting end of the scanning unit in the scanning chain is used as a node connecting end of the scanning chain in a first state, and the second connecting end of the scanning unit in the scanning chain is used as a node connecting end of the scanning chain in a second state;
the input end of each first inverter is used for being connected with the second connecting end of the target scanning unit, and the output end of each first inverter is used for being connected with the first connecting end of the target scanning unit.
3. An edge scan circuit based on a special scan chain architecture according to claim 1 or 2, wherein each scan chain comprises a first node connection in a first state or a second state, and a second node connection in the first state or the second state;
Each scanning chain is ordered according to a first preset sequence;
The first node connecting end of the last scanning chain in the first preset sequence in the first state is connected with the second node connecting end of the previous scanning chain in the first state;
The second node connecting end of the last scanning chain in the second state in the first preset sequence is connected with the input end of the first phase inverter;
the output end of the first inverter is connected with the first node connecting end of the first scanning chain in the first preset sequence, wherein the first node connecting end is in a first state.
4. The side-by-side scan circuit based on special scan chain architecture features of claim 1, wherein the side-by-side scan circuit comprises a long scan chain and a short scan chain, the long scan chain having a length greater than a length of the short scan chain;
the long scan chain comprises a node connection end in a first state and a node connection end in a second state;
Each node connecting end in the short scanning chain is a node connecting end in a first state;
and the node connecting end of the long scanning chain in the second state is used for being connected with the node connecting end of the short scanning chain in the first state through the connecting component.
5. The side-scan circuit based on a special scan chain architecture according to claim 4, wherein the connection component comprises at least one exclusive or gate logic operator;
The long scanning chain or the short scanning chain comprises a plurality of scanning units which are connected in series, and each scanning unit comprises a first connecting end and a second connecting end;
the second connecting end of the target scanning unit in the long scanning chain is used as a node connecting end of the long scanning chain in a second state and is connected with the input end of the exclusive-or gate logic arithmetic unit;
The first connecting end of each scanning unit in the short scanning chain is used as a node connecting end of the short scanning chain in a first state;
the output end of the exclusive-or gate logic operator is connected with the first connecting end of the target scanning unit in the short scanning chain.
6. The side-scan circuit based on special scan chain architecture according to claim 5, wherein each of the scan chains is ordered according to a second predetermined order, and each of the scan cells in the scan chain is ordered according to a third predetermined order;
in the second preset sequence, the previous scanning chain is a long scanning chain, the next scanning chain is a short scanning chain, and the second connecting ends of the last three scanning units in the previous scanning chain, which are ordered according to the third preset sequence, are all connected with the first connecting end of the last scanning unit in the next scanning chain, which is ordered according to the third preset sequence, through the exclusive-or gate logic arithmetic unit, or,
In the second preset sequence, the former scanning chain is a short scanning chain, the latter scanning chain is a long scanning chain, and the second connecting end of the last scanning unit sequenced according to the third preset sequence in the former scanning chain is connected with the first connecting ends of the last two scanning units sequenced according to the third preset sequence in the latter scanning chain.
7. The side-scan circuit based on special scan chain architecture features of claim 4, further comprising a plurality of said long scan chains;
the node connecting end of the long scanning chain in the second state is also used for being connected with the node connecting end of the target long scanning chain in the second state through the connecting component;
The connection assembly comprises at least one second inverter;
each long scanning chain comprises a plurality of scanning units connected in series, and each scanning unit comprises a first connecting end and a second connecting end;
The second connecting end of the target scanning unit in the long scanning chain is used as a node connecting end of the long scanning chain in a second state and is connected with the input end of the second phase inverter;
And a first connecting end of a target scanning unit in the target long scanning chain is used as a node connecting end of the target long scanning chain in a second state and is connected with the output end of the second phase inverter.
8. The side-scan circuit based on special scan chain architecture according to claim 7, wherein each of the scan chains is ordered according to a fourth predetermined order, and each of the scan cells in the scan chain is ordered according to a fifth predetermined order;
in the fourth preset sequence, at least one short scan chain is arranged between two long scan chains, and the second connection end of the last scan unit in the previous long scan chain arranged according to the fifth preset sequence is connected with the first connection end of the last scan unit in the next long scan chain arranged according to the fifth preset sequence through the second inverter.
9. A chip comprising the special scan chain architecture feature-based side-scan circuit of any one of claims 1 to 8.
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| CN101251580A (en) * | 2008-04-17 | 2008-08-27 | 中国科学院计算技术研究所 | A circuit device capable of diagnosing scan chain faults and its diagnosis method |
| CN116774021A (en) * | 2023-06-28 | 2023-09-19 | 深圳市微特精密科技股份有限公司 | Boundary scan chain self-detection logic circuit and self-detection method |
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| CN103262148B (en) * | 2011-04-08 | 2014-12-17 | 夏普株式会社 | Scanning signal line driving circuit and display device having same |
| US8793546B2 (en) * | 2011-06-20 | 2014-07-29 | Lsi Corporation | Integrated circuit comprising scan test circuitry with parallel reordered scan chains |
| JP6988156B2 (en) * | 2017-05-11 | 2022-01-05 | 富士通株式会社 | Diagnostic circuit and control method of diagnostic circuit |
| CN110751929B (en) * | 2019-11-29 | 2022-12-02 | 厦门天马微电子有限公司 | Display panel and display device |
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| CN101251580A (en) * | 2008-04-17 | 2008-08-27 | 中国科学院计算技术研究所 | A circuit device capable of diagnosing scan chain faults and its diagnosis method |
| CN116774021A (en) * | 2023-06-28 | 2023-09-19 | 深圳市微特精密科技股份有限公司 | Boundary scan chain self-detection logic circuit and self-detection method |
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