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CN118920858B - A built-in high-side charge pump circuit - Google Patents

A built-in high-side charge pump circuit Download PDF

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Publication number
CN118920858B
CN118920858B CN202411423311.9A CN202411423311A CN118920858B CN 118920858 B CN118920858 B CN 118920858B CN 202411423311 A CN202411423311 A CN 202411423311A CN 118920858 B CN118920858 B CN 118920858B
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inverter
nand gate
gate
power supply
source
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CN118920858A (en
Inventor
唐宁
李威
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention relates to a built-in high-side charge pump circuit, and belongs to the field of design of single-chip bridge circuit driving circuits. The device mainly comprises a clock control circuit, a pump circuit and a limiting circuit. The clock control circuit is composed of a non-overlapping clock generation circuit and a control tube, and generates two paths of non-overlapping clock signals by using a square wave signal CLK with a certain amplitude, the pump circuit mainly comprises a capacitor and a switch tube, the working frequency of the switch tube determines the charge and discharge time of the capacitor, and the high-side floating HS is pumped up to control the power supply voltage VDD to output a high-side power supply potential HB by using the charge conservation law of the capacitor. The amplitude limiting circuit mainly comprises a voltage stabilizing tube and a diode cascade connection, so that the voltage of the charge pump is stably output. The high-low side double-path driving chip is internally provided with the high-side charge pump circuit, so that the problem of charge supplement of continuous on-state operation of the high-side driving circuit powered by the external bootstrap capacitor when outputting a high-level driving signal is solved, and a stable high-side power supply is provided.

Description

Built-in high-side charge pump circuit
Technical Field
The invention belongs to the field of design of single-chip bridge circuit driving circuits, and particularly relates to a built-in high-side charge pump circuit.
Background
With the proposal of the concepts of miniaturization, high reliability and the like of a direct current motor driving system, a higher level requirement is also put forward for the working mode of a single-chip bridge circuit driving circuit. The DC motor driving system mainly comprises three topological structures of a high-side double-circuit, a low-side double-circuit, an H-bridge and a three-phase bridge, and is formed by combining a single-chip bridge driving circuit with a high-side and low-side totem pole type N-type power switching tube. When in operation, sufficient gate-source voltage and switching speed are needed to drive the high-side N-type power switch tube and the low-side N-type power switch tube to be turned on and off.
In the existing high-low side two-way driving circuit, when the high-side power tube is turned off and the low-side power tube is turned on, one end HS of the bootstrap capacitor is switched to the common ground, the other end HB of the bootstrap capacitor is charged by the VDD power supply through the bootstrap diode and simultaneously supplies power for the turn-off state of the high-side driving chip, and when the high-side power tube is turned on and the low-side power tube is turned off, one end HS of the bootstrap capacitor is switched to the power supply, and the other end HB of the bootstrap capacitor is bootstrapped to boost a VDD voltage to supply power for the turn-on state of the high-side driving chip. The circuit structure has the defects that when the high-side driving circuit is in a high-side power tube conducting state, the external bootstrap capacitor is used for supplying power, and along with the power consumption of the high-side driving circuit and the requirements of the grid capacitor of the power switch tube, the stored charge of the bootstrap capacitor is transferred in a large quantity, if the sufficient grid source voltage of the high-side power tube is required to be ensured, the bootstrap capacitor needs to be charged periodically, namely, the bridge circuit driving circuit works in a Pulse Width Modulation (PWM) mode to drive the high-side power tube and the low-side power tube to be alternately switched. When the low-frequency drive or the high-side drive circuit is in a high duty ratio, the bootstrap capacitor cannot obtain an effective charging period, the stored charge cannot ensure reasonable high-side drive on-state output, and even the low-voltage threshold value of the high-side drive circuit power supply (HB-HS) is lower than the low-voltage threshold value, and the high-side power switch tube cannot be effectively opened. Its application in motor drive systems is severely limited.
Disclosure of Invention
The invention aims to provide a built-in high-side charge pump circuit design. As shown in FIG. 2, when the high-side drive on state is realized by the built-in high-side charge pump, the current output capability of 100uA is provided to charge supplement the external bootstrap capacitor, so that the external bootstrap capacitor is ensured to have a stable HB-HS voltage, and the problem of application of a motor drive system with a low-frequency drive or high-side drive circuit at a duty ratio of up to 100% is solved. As a common application technology, the high-side grid electrode driving circuit is ensured to continuously and stably work, and stable high-side power supply is provided for motor driving systems with various topological structures.
The technical scheme adopted by the invention for achieving the purpose is as follows:
the built-in high-side charge pump circuit comprises a clock control circuit, a pump circuit and a limiting circuit, wherein the clock control circuit is of a non-overlapping clock generation circuit, a certain square wave signal CLK is generated to generate two non-overlapping clock signals and is transmitted to the pump circuit, the pump circuit is used for alternately charging and discharging a secondary capacitor for switching a switching tube so as to further realize HS potential boosting and transmitting the HS potential boosting to the limiting circuit, and the limiting circuit is formed by cascading a voltage stabilizing tube and a diode so as to realize HB-HS voltage stable output.
The clock control circuit specifically comprises an inverter 001, an inverter 002, an inverter 003 and an inverter 004, a NAND gate 001, a NAND gate 002, a NAND gate 003, NMMOS tubes NMOS8 and NMOS12 and PMOS tubes PMOS8 and PMOS12, wherein the specific connection modes are as follows:
The power supply of the inverter 001 is connected with VDD, the ground of the inverter 001 is connected with VSS, the input end of the inverter 001 is connected with an EN enabling signal, and the output end of the inverter 001 is connected with the input end A of the NAND gate 001;
the power supply of the NAND gate 001 is connected with VDD, the ground of the NAND gate 001 is connected with VSS, the input end B of the NAND gate 001 is connected with a square wave signal CLK, and the output end of the NAND gate 001 is connected with the input end of the inverter 002 and the input end A of the NAND gate 003;
The power supply of the inverter 002 is connected with VDD, the ground of the inverter 002 is connected with VSS, and the output end of the inverter 002 is connected with the input end A of the NAND gate 002;
The power supply of the NAND gate 002 is connected with VDD, the ground of the NAND gate 002 is connected with VSS, the input end B of the NAND gate 002 is connected with the output end of the NAND gate 003, and the output end of the NAND gate 002 is connected with the input end of the inverter 003 and the input end A of the NAND gate 003;
the power supply of the inverter 003 is connected with VDD, the ground of the inverter 003 is connected with VSS, and the output end of the inverter 003 is connected with the grid electrode of the NMOS 8;
The source electrode of the NMOS8 is grounded VSS, the source electrode of the PMOS8 is connected with a power supply VDD, the grid electrode of the PMOS8 is connected to the output end of the NAND gate 003, and the drain electrode of the NMOS8 and the drain electrode of the PMOS8 are in short circuit and are connected to the pump circuit as the output end Y2 of the clock control circuit;
The power supply of the NAND gate 003 is connected with VDD, the ground of the NAND gate 003 is connected with VSS, and the output end of the NAND gate 003 is connected with the input end of the inverter 004;
The power supply of the inverter 004 is connected with VDD, the ground of the inverter 004 is connected with VSS, and the output end of the inverter 004 is connected with the grid electrode of the NMOS 12;
The source of NMOS12 is grounded VSS, the source of PMOS12 is connected to power supply VDD, the grid of PMOS12 is connected to the output end of NAND gate 002, the drain short circuits of NMOS12 and PMOS12 are connected to the pump circuit as clock control circuit output end Y1.
The pump circuit comprises capacitors C1 and C2, NPN transistors Q1, Q2 and Q3, wherein an upper polar plate of the C1 is connected with an output end Y1 of the clock control circuit, a lower polar plate of the C1 is connected with a base electrode and a collector electrode of the Q1, an emitter electrode of the Q2 is connected with a pin HB of a high-side driving suspension power supply, an upper polar plate of the C2 is connected with an output end Y2 of the clock control circuit, a lower polar plate of the C2 is connected with the base electrode and the collector electrode of the Q2, and an emitter electrode of the Q3 is connected with a pin HS of the high-side driving suspension ground.
The limiting circuit comprises zener diodes D0 and D1, a capacitor C3 and N forward conduction diodes DN which are connected in series, wherein the anode of DN is connected to a HB pin, the cathode of DN is connected to the cathode of D0, the anode of D0 is connected to the cathode of D1, the anode of D1 is connected to a HS pin, the upper polar plate of C3 is connected to the HB pin, and the lower polar plate of C3 is connected to the HS pin.
The EN input end control method is that the EN end is applied with high level 1, the clock control circuit is in a disabled state, and the whole built-in high-side charge pump circuit does not work. The EN terminal is applied with low level 0, the clock control circuit is in an enabling state, square wave signals CLK with amplitude of 0-VDD and frequency of 1MHz are generated into two non-overlapping clock signals, and capacitor potential is periodically switched through a switching tube.
Compared with the prior art, the invention has the following beneficial effects and advantages:
1. The characteristic that the built-in high-side charge pump circuit is used as an auxiliary power supply is fully utilized, the charge loss during power supply of the external bootstrap capacitor is supplemented, and the topological structure of the external device of the chip is not affected.
2. The invention can be applied to the high-side gate drive chip to conduct PWM at low frequency or high duty ratio, even in a constant conduction working mode, and effectively solves the problem of power supply stability when the high-side gate drive outputs a conduction state.
3. The built-in high-side charge pump circuit designed by the invention has the advantages of simple structure, clear principle and good process compatibility, can realize monolithic integration with the existing high-side gate driver, and can be widely used in high-side gate driving chips of bridge drivers with different topological structures.
Drawings
FIG. 1 is a topology diagram of a conventional high-low side driver chip;
FIG. 2 is a topology diagram of a high-low side driver chip of the present invention;
FIG. 3 is a block diagram of a high Bian Dianhe pump circuit of the present invention;
FIG. 4 is a diagram of a clock control circuit of the present invention;
FIG. 5 is a circuit diagram of a pump of the present invention;
fig. 6 is a limiting circuit diagram of the present invention.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit or scope of the invention, which is therefore not limited to the specific embodiments disclosed below.
The invention discloses a built-in high-side charge pump circuit, which is shown in fig. 3 and comprises a clock control circuit, a pump circuit and a limiting circuit. The clock control circuit is structurally characterized in that a non-overlapping clock generating circuit generates two non-overlapping clock signals by a certain square wave signal CLK, a pump circuit alternately charges and discharges a secondary capacitor for switching a switching tube so as to further realize HS potential boosting, and a limiting circuit limits the output of a charge pump so as to realize HB-HS voltage stable output.
Specifically, as shown in fig. 4, the clock control circuit comprises a PMOS transistor PMOS1, a PMOS transistor PMOS2, a PMOS transistor PMOS3, a PMOS transistor PMOS4, a PMOS transistor PMOS5, a PMOS transistor PMOS6, a PMOS transistor PMOS7, a PMOS transistor PMOS8, a PMOS transistor PMOS9, a PMOS transistor PMOS10, a PMOS transistor PMOS11, a PMOS transistor PMOS12, an NMOS transistor NMOS1, an NMOS transistor NMOS2, an NMOS transistor NMOS3, an NMOS transistor NMOS4, an NMOS transistor NMOS5, an NMOS transistor NMOS6, an NMOS transistor NMOS7, an NMOS transistor NMOS8, an NMOS transistor NMOS9, an NMOS transistor NMOS10, an NMOS transistor NMOS11, and an NMOS transistor NMOS12.
The connection mode is that a PMOS1 and an NMOS1 form an inverter 001, the source electrode of the PMOS1 is used as a power supply of the inverter 001 to be connected with VDD, the source electrode of the NMOS1 is used as a ground of the inverter 001 to be connected with VSS, the gate of the PMOS1 and the gate of the NMOS1 are in short connection with each other to be used as an input end of the inverter 001 to be connected with an EN enabling signal, and the drain electrode of the PMOS1 and the drain electrode of the NMOS1 are in short connection with each other to be used as an output end of the inverter 001 to be connected with an input end A of the NAND gate 001.
PMOS2, PMOS3, NMOS2 and NMOS3 form a NAND gate 001, the sources of PMOS2 and PMOS3 are used as a power supply of the NAND gate 001 to be connected with VDD, the sources of NMOS3 and the drain of NMOS2, the source of NMOS2 is connected with ground of the NAND gate 001 to be connected with VSS, the gate short circuit of PMOS2 and NMOS2 is used as an input end A of the NAND gate 001 to be connected with the output end of the inverter 001, the gate short circuit of PMOS3 and NMOS3 is used as an input end B of the NAND gate 001 to be connected with a square wave signal CLK, and the drain short circuits of PMOS2, PMOS3 and NMOS3 are used as the output ends of the NAND gate 001 to be connected with the input end 002 of the inverter 003 and the input end A of the NAND gate 003.
The PMOS4 and the NMOS4 form an inverter 002, the source electrode of the PMOS4 is used as a power supply of the inverter 002 and connected with VDD, the source electrode of the NMOS4 is used as a ground of the inverter 002 and connected with VSS, the gate electrode of the PMOS4 and the gate short circuit of the NMOS4 are used as input ends of the inverter 002 and connected with the output end of the NAND gate 001, and the drain electrode of the PMOS4 and the drain short circuit of the NMOS4 are used as output ends of the inverter 002 and connected with the input end A of the NAND gate 002.
PMOS5, PMOS6, NMOS5 and NMOS6 form a NAND gate 002, the sources of the PMOS5 and the PMOS6 are used as a power supply of the NAND gate 002 to be connected with VDD, the sources of the NMOS6 and the drain of the NMOS5, the source short circuit of the NMOS5 is used as the ground of the NAND gate 002 to be connected with VSS, the gate short circuits of the PMOS5 and the NMOS5 are used as an input end A of the NAND gate 002 to be connected with an output end of the inverter 002, the gate short circuits of the PMOS6 and the NMOS6 are used as an input end B of the NAND gate 002 to be connected with an output end of the NAND gate 003, and the drain short circuits of the PMOS5, the PMOS6 and the NMOS6 are used as the output ends of the NAND gate 002 to be connected with the input end of the inverter 003 and the input end A of the NAND gate 003.
The PMOS7 and the NMOS7 form an inverter 003, the source of the PMOS7 is used as a power supply of the inverter 003 and connected with VDD, the source of the NMOS7 is used as a ground of the inverter 003 and connected with VSS, the gate of the MOS7 and the gate of the NMOS7 are in short circuit, the input end of the inverter 003 is connected with the output end of the NAND gate 002, and the drain of the PMOS7 and the drain of the NMOS7 are in short circuit, and the output end of the inverter 003 is connected with the gate of the NMOS 8.
The source electrode of the NMOS8 is grounded to VSS, the grid electrode of the NMOS8 is connected with the output end of the inverter 003, the source electrode of the PMOS8 is connected with the power supply VDD, the grid electrode of the PMOS8 is connected to the output end of the NAND gate 003, and the drain electrode short circuits of the NMOS8 and the PMOS8 are used as the output end Y2 of the clock control circuit to be connected to the upper polar plate of the capacitor C2 in the pump circuit.
The PMOS9, the PMOS10, the NMOS9 and the NMOS10 form a NAND gate 003, the sources of the PMOS9 and the PMOS10 are used as a power supply of the NAND gate 003 to be connected with VDD, the sources of the NMOS10 and the drain of the NMOS9 are used as a ground of the NAND gate 003 to be connected with VSS, the gate short circuit of the PMOS9 and the NMOS9 is used as an input end A of the NAND gate 003 to be connected with an output end of the NAND gate 002, the gate short circuit of the PMOS10 and the NMOS10 is used as an input end B of the NAND gate 003 to be connected with an output end of the NAND gate 001, and the drain short circuits of the PMOS9, the PMOS10 and the NMOS10 are used as output ends of the NAND gate 003 to be connected with an input end 004 of the inverter 004 and an input end B of the NAND gate 002.
The PMOS11 and the NMOS11 form an inverter 004, the source electrode of the PMOS11 is used as a power supply of the inverter 004 and connected with VDD, the source electrode of the NMOS11 is used as a ground of the inverter 004 and connected with VSS, the gate electrode of the PMOS11 and the gate electrode of the NMOS11 are in short circuit, used as input ends of the inverter 004 and connected with the output end of the NAND gate 003, and the drain electrode of the PMOS11 and the drain electrode of the NMOS11 are in short circuit, used as output ends of the inverter 004 and connected with the gate electrode of the NMOS 12.
The source electrode of the NMOS12 is grounded to VSS, the grid electrode of the NMOS12 is connected to the output end of the inverter 004, the source electrode of the PMOS12 is connected to the power supply VDD, the grid electrode of the PMOS12 is connected to the output end of the NAND gate 002, and the drain electrode short circuits of the NMOS12 and the PMOS12 are used as the output end Y1 of the clock control circuit to be connected to the upper electrode plate of the capacitor C1 in the pump circuit.
The EN input end enables the working state of the whole circuit, EN and a square wave signal CLK are applied to a clock control circuit as 2-way input of a nand gate 001, a positive phase inversion two-way signal is output through an inverter 002 and enters a trigger circuit formed by nand gates 002 and 003 at the later stage, two non-overlapping clock signals are generated, and respective phase inversion signals are output through inverters 003 and 004 respectively.
Specifically, as shown in the left diagram of fig. 5, the pump circuit includes capacitors C1, C2, and NPN transistors Q1, Q2, Q3. The upper polar plate of C1 is connected with the output end Y1 of the clock control circuit, the lower polar plate of C1 is connected with the base electrode and the collector electrode of Q1, the emitter electrode of Q2 is connected to the pin of a high-side driving suspension power supply (HB). The upper polar plate of C2 is connected with the output end Y2 of the clock control circuit, the lower polar plate of C2 is connected with the base electrode and the collector electrode of Q2, the emitter electrode of Q3 is connected to a high-side driving floating ground (HS) pin.
The pump circuit adopts C1 and C2 as pump capacitors, two paths of non-overlapping clock signals output by the clock control circuit control the switches of the switching tubes PMOS12, NMOS12, PMOS8 and NMOS8, so that the pole plates of the pump capacitors are alternately connected to VDD or VSS to realize charge transfer between the capacitors, and meanwhile, the cascade structure of NPN transistors (bc junction short circuit) Q1, Q2 and Q3 connected by three diodes is used as forward transmission and reverse phase cut-off to realize boosting to HB of a suspension potential HS, provide current output capacity of 100uA and supplement charge loss of an external capacitor.
Specifically, as shown in fig. 6, the clipping circuit includes zener diodes D0 and D1, a capacitor C3, and N forward conduction diodes DN connected in series, where n=1 in this embodiment. DN is connected to HB pin, DN is connected to D0, D0 is connected to D1, and D1 is connected to HS pin. The C3 upper polar plate is connected to HB pin, and the C3 lower polar plate is connected to HS pin.
The amplitude limiting circuit adopts voltage stabilizing tubes D1 and D0 and a forward diode DN to be cascaded between HB and HS, the voltage stabilizing value V m of the voltage stabilizing tube is 4.8V, and N forward diodes are required to be connected in series according to the value of the power supply voltage HB-HS, whereinWhere VBE is forward diode drop.
As shown in fig. 4, the enable signal EN enables the clock control circuit to work, when EN is low level "0", the nand gate 001 inverts the square wave signal CLK, and as the clock control signal of the two logic circuits, the clock signal is generated through the latch formed by the nand gate 002 and the nand gate 003, and is divided into 4 square wave signals through the inverter 003 and the inverter 004, so as to respectively control the gates of the 4 switching transistors PMOS12, NMOS12, PMOS8 and NMOS 8. With the periodic variation of the phase of the 4-way square wave signal, 4 switching transistors are switched to be connected to VDD or VSS.
As shown in the right diagram of fig. 5, when the HS pin is switched from the external circuit to the common ground, HB is fed from VDD through the bootstrap diode, and the pump circuit does not function. When the HS pin is switched to a power supply from an external circuit, HB is lifted through an external bootstrap capacitor and reversely biased with a bootstrap diode between VDD, the pump circuit alternately works under the periodic variation of two phases (phase 1 and phase 2) provided by the clock control circuit, and voltage drop generated by the connection of the NPN diode is ignored, when the phase1 is periodic, as shown by an upper right graph line of fig. 5, the upper C2 polar plate is switched to VSS, when the upper C1 polar plate is switched to VDD=12V, HS charges the upper C1 polar plate and the upper C2 polar plate through Q1 and Q2 respectively, the voltage drop of the C2 is about HS, and the voltage drop of the C2 is reversely cut off for the Q2 after the charging of the C1, so that the voltage drop is output to HB through Q3. In the Phase2 period, as shown in the lower right line of fig. 5, the upper plate of C2 is switched to VDD, the upper plate of C1 is switched to VSS, the potential of the lower plate of C2 is suddenly changed to hs+vdd, and C2 charges C1, and the potential of the lower plate of C1 is hs+. After several cycles of clock alternation, hb=hs+vdd output.
As shown in FIG. 6, the zener diodes D0 and D1 are connected in series with the forward conduction diode DN to realize the clipping of HB-HS voltage, and the output voltage of the charge pump can be provided by programming the number of forward conduction diodes DN connected in series, so as to provide a leakage path for redundant voltage. Capacitor C3 filters the HB-HS output voltage.

Claims (3)

1.一种内置高边电荷泵电路，其特征在于，包括时钟控制电路、泵电路、限幅电路；所述时钟控制电路结构为不交叠时钟产生电路，将方波信号CLK产生两个不交叠时钟信号传送给泵电路，所述泵电路为开关管切换对二级电容交替充电和放电进而实现HS电位升压并传送至限幅电路，所述限幅电路由稳压管以及二极管级联组成，实现HB-HS电压稳定输出；其中HB为高边供电电源，HS为高边地；1. A built-in high-side charge pump circuit, characterized in that it includes a clock control circuit, a pump circuit, and a limiter circuit; the clock control circuit structure is a non-overlapping clock generation circuit, which generates two non-overlapping clock signals from a square wave signal CLK and transmits them to the pump circuit, the pump circuit is a switch tube that switches to alternately charge and discharge the secondary capacitor to achieve HS potential boost and transmit it to the limiter circuit, the limiter circuit is composed of a voltage regulator tube and a diode cascade to achieve HB-HS voltage stable output; wherein HB is a high-side power supply, and HS is a high-side ground; 所述时钟控制电路具体包括反相器001、反相器002、反相器003、反相器004，与非门001、与非门002、与非门003，NMOS管NMOS8、NMOS12，PMOS管PMOS8、PMOS12；具体连接方式如下：The clock control circuit specifically includes inverter 001, inverter 002, inverter 003, inverter 004, NAND gate 001, NAND gate 002, NAND gate 003, NMOS tubes NMOS8, NMOS12, PMOS tubes PMOS8, PMOS12; the specific connection method is as follows: 反相器001的电源接VDD，反相器001的地接VSS，反相器001的输入端接EN使能信号，反相器001的输出端接与非门001的输入端A；The power supply of the inverter 001 is connected to VDD, the ground of the inverter 001 is connected to VSS, the input terminal of the inverter 001 is connected to the EN enable signal, and the output terminal of the inverter 001 is connected to the input terminal A of the NAND gate 001; 与非门001的电源接VDD，与非门001的地接VSS，与非门001的输入端B接方波信号CLK，与非门001的输出端接反相器002输入端和与非门003的输入端A；The power supply of the NAND gate 001 is connected to VDD, the ground of the NAND gate 001 is connected to VSS, the input terminal B of the NAND gate 001 is connected to the square wave signal CLK, and the output terminal of the NAND gate 001 is connected to the input terminal of the inverter 002 and the input terminal A of the NAND gate 003; 反相器002的电源接VDD，反相器002的地接VSS，反相器002的输出端接与非门002的输入端A；The power supply of the inverter 002 is connected to VDD, the ground of the inverter 002 is connected to VSS, and the output terminal of the inverter 002 is connected to the input terminal A of the NAND gate 002; 与非门002的电源接VDD，与非门002的地接VSS，与非门002的输入端B接与非门003输出端，与非门002的输出端接反相器003的输入端和与非门003的输入端A；The power supply of the NAND gate 002 is connected to VDD, the ground of the NAND gate 002 is connected to VSS, the input terminal B of the NAND gate 002 is connected to the output terminal of the NAND gate 003, and the output terminal of the NAND gate 002 is connected to the input terminal of the inverter 003 and the input terminal A of the NAND gate 003; 反相器003的电源接VDD，反相器003的地接VSS，反相器003的输出端接NMOS8的栅极；The power supply of the inverter 003 is connected to VDD, the ground of the inverter 003 is connected to VSS, and the output terminal of the inverter 003 is connected to the gate of the NMOS 8; NMOS8的源极接地VSS，PMOS8的源极接电源VDD，PMOS8的栅极连接至与非门003的输出端，NMOS8和PMOS8的漏极短接作为时钟控制电路输出端Y2接至泵电路；The source of NMOS8 is connected to the ground VSS, the source of PMOS8 is connected to the power supply VDD, the gate of PMOS8 is connected to the output end of the NAND gate 003, and the drains of NMOS8 and PMOS8 are short-circuited as the output end Y2 of the clock control circuit connected to the pump circuit; 与非门003的电源接VDD，与非门003的地接VSS，与非门003的输出端接反相器004的输入端；The power supply of the NAND gate 003 is connected to VDD, the ground of the NAND gate 003 is connected to VSS, and the output terminal of the NAND gate 003 is connected to the input terminal of the inverter 004; 反相器004的电源接VDD，反相器004的地接VSS，反相器004的输出端接NMOS12的栅极；The power supply of the inverter 004 is connected to VDD, the ground of the inverter 004 is connected to VSS, and the output terminal of the inverter 004 is connected to the gate of the NMOS 12; NMOS12的源极接地VSS，PMOS12的源极接电源VDD，PMOS12的栅极连接至与非门002的输出端，NMOS12和PMOS12的漏极短接作为时钟控制电路输出端Y1接至泵电路；The source of NMOS12 is connected to the ground VSS, the source of PMOS12 is connected to the power supply VDD, the gate of PMOS12 is connected to the output end of NAND gate 002, and the drains of NMOS12 and PMOS12 are short-circuited as the output end Y1 of the clock control circuit connected to the pump circuit; 所述泵电路包括电容C1、C2，NPN管Q1、Q2、Q3；C1上极板连接时钟控制电路输出端Y1，C1下极板与Q1的基极、集电极，Q2的发射极连接在一起，Q1的发射极连接至高边驱动悬浮电源HB引脚；C2上极板连接时钟控制电路输出端Y2，C2下极板与Q2的基极、集电极，Q3的发射极连接在一起，Q3的集电极连接至高边驱动悬浮地HS引脚；The pump circuit includes capacitors C1 and C2, and NPN tubes Q1, Q2, and Q3; the upper plate of C1 is connected to the output terminal Y1 of the clock control circuit, the lower plate of C1 is connected to the base and collector of Q1, and the emitter of Q2, and the emitter of Q1 is connected to the high-side drive floating power supply HB pin; the upper plate of C2 is connected to the output terminal Y2 of the clock control circuit, the lower plate of C2 is connected to the base and collector of Q2, and the emitter of Q3, and the collector of Q3 is connected to the high-side drive floating ground HS pin; 所述限幅电路包括齐纳二极管D0、D1，电容C3，N个串联的正向导通二极管DN；DN的阳极连接至HB引脚，DN的阴极连接至D0的阴极，D0的阳极连接至D1的阴极，D1的阳极连接至HS引脚；C3上极板连接至HB引脚，C3下极板连接至HS引脚。The limiting circuit includes Zener diodes D0 and D1, a capacitor C3, and N forward conducting diodes DN connected in series; the anode of DN is connected to the HB pin, the cathode of DN is connected to the cathode of D0, the anode of D0 is connected to the cathode of D1, and the anode of D1 is connected to the HS pin; the upper plate of C3 is connected to the HB pin, and the lower plate of C3 is connected to the HS pin. 2.根据权利要求1所述的一种内置高边电荷泵电路，其特征在于，所述时钟控制电路包括PMOS管PMOS1，PMOS管PMOS2，PMOS管PMOS3，PMOS管PMOS4，PMOS管PMOS5，PMOS管PMOS6，PMOS管PMOS7，PMOS管PMOS8，PMOS管PMOS9，PMOS管PMOS10，PMOS管PMOS11，PMOS管PMOS12；NMOS管NMOS1，NMOS管NMOS2，NMOS管NMOS3，NMOS管NMOS4，NMOS管NMOS5，NMOS管NMOS6，NMOS管NMOS7，NMOS管NMOS8，NMOS管NMOS9，NMOS管NMOS10，NMOS管NMOS11，NMOS管NMOS12；连接方式如下：PMOS1和NMOS1组成反相器001，PMOS1的源极作为反相器001的电源接VDD，NMOS1的源极作为反相器001的地接VSS，PMOS1的栅极和NMOS1的栅极短接作为反相器001的输入端接EN使能信号，PMOS1的漏极和NMOS1的漏极短接作为反相器001的输出端接与非门001的输入端A；2. A built-in high-side charge pump circuit according to claim 1, characterized in that the clock control circuit comprises PMOS tubes PMOS1, PMOS tubes PMOS2, PMOS tubes PMOS3, PMOS tubes PMOS4, PMOS tubes PMOS5, PMOS tubes PMOS6, PMOS tubes PMOS7, PMOS tubes PMOS8, PMOS tubes PMOS9, PMOS tubes PMOS10, PMOS tubes PMOS11, and PMOS tubes PMOS12; NMOS tubes NMOS1, NMOS tubes NMOS2, NMOS tubes NMOS3, NMOS tubes NMOS4, NMOS tubes NMOS5, and NMOS S tube NMOS6, NMOS tube NMOS7, NMOS tube NMOS8, NMOS tube NMOS9, NMOS tube NMOS10, NMOS tube NMOS11, NMOS tube NMOS12; the connection method is as follows: PMOS1 and NMOS1 form an inverter 001, the source of PMOS1 is connected to VDD as the power supply of the inverter 001, the source of NMOS1 is connected to VSS as the ground of the inverter 001, the gate of PMOS1 and the gate of NMOS1 are short-circuited as the input terminal of the inverter 001 connected to the EN enable signal, and the drain of PMOS1 and the drain of NMOS1 are short-circuited as the output terminal of the inverter 001 connected to the input terminal A of the NAND gate 001; PMOS2、PMOS3和NMOS2、NMOS3组成与非门001，PMOS2和PMOS3的源极作为与非门001的电源接VDD，NMOS3的源极与NMOS2的漏极连接，NMOS2的源极作为与非门001的地接VSS，PMOS2和NMOS2的栅级短接作为与非门001的输入端A接反相器001的输出端，PMOS3和NMOS3的栅级短接作为与非门001的输入端B接方波信号CLK，PMOS2、PMOS3和NMOS3的漏极短接作为与非门001的输出端接反相器002输入端和与非门003的输入端A；PMOS2, PMOS3 and NMOS2, NMOS3 form a NAND gate 001, the source of PMOS2 and PMOS3 is connected to VDD as the power supply of the NAND gate 001, the source of NMOS3 is connected to the drain of NMOS2, the source of NMOS2 is connected to VSS as the ground of the NAND gate 001, the gates of PMOS2 and NMOS2 are short-circuited as the input terminal A of the NAND gate 001 connected to the output terminal of the inverter 001, the gates of PMOS3 and NMOS3 are short-circuited as the input terminal B of the NAND gate 001 connected to the square wave signal CLK, the drains of PMOS2, PMOS3 and NMOS3 are short-circuited as the output terminal of the NAND gate 001 connected to the input terminal of the inverter 002 and the input terminal A of the NAND gate 003; PMOS4和NMOS4组成反相器002，PMOS4的源极作为反相器002的电源接VDD，NMOS4的源极作为反相器002的地接VSS，PMOS4的栅极和NMOS4的栅极短接作为反相器002的输入端接至与非门001的输出端，PMOS4的漏极和NMOS4的漏极短接作为反相器002的输出端接与非门002的输入端A；PMOS4 and NMOS4 form an inverter 002, the source of PMOS4 is connected to VDD as the power supply of the inverter 002, the source of NMOS4 is connected to VSS as the ground of the inverter 002, the gate of PMOS4 and the gate of NMOS4 are short-circuited as the input end of the inverter 002 connected to the output end of the NAND gate 001, and the drain of PMOS4 and the drain of NMOS4 are short-circuited as the output end of the inverter 002 connected to the input end A of the NAND gate 002; PMOS5、PMOS6和NMOS5、NMOS6组成与非门002，PMOS5和PMOS6的源极作为与非门002的电源接VDD，NMOS6的源极、NMOS5的漏极相连，NMOS5的源极作为与非门002的地接VSS，PMOS5和NMOS5的栅级短接作为与非门002的输入端A接反相器002的输出端，PMOS6和NMOS6的栅级短接作为与非门002的输入端B接与非门003输出端，PMOS5、PMOS6和NMOS6的漏极短接作为与非门002的输出端接反相器003的输入端和与非门003的输入端A；PMOS5, PMOS6 and NMOS5, NMOS6 form a NAND gate 002, the sources of PMOS5 and PMOS6 are connected to VDD as the power supply of the NAND gate 002, the source of NMOS6 and the drain of NMOS5 are connected, the source of NMOS5 is connected to VSS as the ground of the NAND gate 002, the gates of PMOS5 and NMOS5 are short-circuited as the input terminal A of the NAND gate 002 connected to the output terminal of the inverter 002, the gates of PMOS6 and NMOS6 are short-circuited as the input terminal B of the NAND gate 002 connected to the output terminal of the NAND gate 003, and the drains of PMOS5, PMOS6 and NMOS6 are short-circuited as the output terminal of the NAND gate 002 connected to the input terminal of the inverter 003 and the input terminal A of the NAND gate 003; PMOS7和NMOS7组成反相器003，PMOS7的源极作为反相器003的电源接VDD，NMOS7的源极作为反相器003的地接VSS，MOS7的栅极和NMOS7的栅极短接作为反相器003的输入端接与非门002的输出端，PMOS7的漏极和NMOS7的漏极短接作为反相器003的输出端接NMOS8的栅极；PMOS7 and NMOS7 form an inverter 003, the source of PMOS7 is connected to VDD as the power supply of the inverter 003, the source of NMOS7 is connected to VSS as the ground of the inverter 003, the gate of MOS7 and the gate of NMOS7 are short-circuited as the input terminal of the inverter 003 connected to the output terminal of the NAND gate 002, and the drain of PMOS7 and the drain of NMOS7 are short-circuited as the output terminal of the inverter 003 connected to the gate of NMOS8; NMOS8的源极接地VSS，NMOS8的栅极接反相器003的输出端，PMOS8的源极接电源VDD，PMOS8的栅极连接至与非门003的输出端，NMOS8和PMOS8的漏极短接作为时钟控制电路输出端Y2接至泵电路中电容C2的上极板；The source of NMOS8 is connected to the ground VSS, the gate of NMOS8 is connected to the output of the inverter 003, the source of PMOS8 is connected to the power supply VDD, the gate of PMOS8 is connected to the output of the NAND gate 003, and the drains of NMOS8 and PMOS8 are short-circuited as the output terminal Y2 of the clock control circuit connected to the upper plate of the capacitor C2 in the pump circuit; PMOS9、PMOS10和NMOS9、NMOS10组成与非门003，PMOS9和PMOS10的源极作为与非门003的电源接VDD，NMOS10的源极、NMOS9的漏极相连，NMOS9的源极作为与非门003的地接VSS，PMOS9和NMOS9的栅级短接作为与非门003的输入端A接与非门002输出端，PMOS10和NMOS10的栅级短接作为与非门003的输入端B接与非门001的输出端，PMOS9、PMOS10和NMOS10的漏极短接作为与非门003的输出端接反相器004的输入和与非门002的输入端B；PMOS9, PMOS10 and NMOS9, NMOS10 form a NAND gate 003, the source of PMOS9 and PMOS10 are connected to VDD as the power supply of the NAND gate 003, the source of NMOS10 and the drain of NMOS9 are connected, the source of NMOS9 is connected to VSS as the ground of the NAND gate 003, the gates of PMOS9 and NMOS9 are short-circuited as the input terminal A of the NAND gate 003 connected to the output terminal of the NAND gate 002, the gates of PMOS10 and NMOS10 are short-circuited as the input terminal B of the NAND gate 003 connected to the output terminal of the NAND gate 001, and the drains of PMOS9, PMOS10 and NMOS10 are short-circuited as the output terminal of the NAND gate 003 connected to the input of the inverter 004 and the input terminal B of the NAND gate 002; PMOS11和NMOS11组成反相器004，PMOS11的源极作为反相器004的电源接VDD，NMOS11的源极作为反相器004的地接VSS，PMOS11的栅极和NMOS11的栅极短接作为反相器004的输入端接至与非门003的输出端，PMOS11的漏极和NMOS11的漏极短接作为反相器004的输出端接NMOS12的栅极；PMOS11 and NMOS11 form an inverter 004, the source of PMOS11 is connected to VDD as the power supply of the inverter 004, the source of NMOS11 is connected to VSS as the ground of the inverter 004, the gate of PMOS11 and the gate of NMOS11 are short-circuited as the input end of the inverter 004 and connected to the output end of the NAND gate 003, the drain of PMOS11 and the drain of NMOS11 are short-circuited as the output end of the inverter 004 and connected to the gate of NMOS12; NMOS12的源极接地VSS，NMOS12的栅极接反相器004的输出端，PMOS12的源极接电源VDD，PMOS12的栅极连接至与非门002的输出端，NMOS12和PMOS12的漏极短接作为时钟控制电路输出端Y1接至泵电路中电容C1的上极板。The source of NMOS12 is connected to the ground VSS, the gate of NMOS12 is connected to the output of inverter 004, the source of PMOS12 is connected to the power supply VDD, the gate of PMOS12 is connected to the output of NAND gate 002, and the drains of NMOS12 and PMOS12 are short-circuited as the output terminal Y1 of the clock control circuit connected to the upper plate of capacitor C1 in the pump circuit. 3.根据权利要求2所述的一种内置高边电荷泵电路，其特征在于，所述N个串联的正向导通二极管DN在串联时，N＝(HB-HS-Vm*2)/VBE，其中Vm为稳压管电压值，VBE为正向二极管压降。3. A built-in high-side charge pump circuit according to claim 2, characterized in that when the N series-connected forward conducting diodes DN are connected in series, N=(HB-HS-V m *2)/VBE, wherein V m is the voltage value of the voltage regulator tube, and VBE is the forward diode voltage drop.
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CN108418420A (en) * 2018-04-27 2018-08-17 电子科技大学 A charge pump circuit based on multiple non-overlapping clocks
CN112688541A (en) * 2020-12-23 2021-04-20 西安拓尔微电子有限责任公司 High-side high-voltage NMOS (N-channel metal oxide semiconductor) control method and drive circuit

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CN112688541A (en) * 2020-12-23 2021-04-20 西安拓尔微电子有限责任公司 High-side high-voltage NMOS (N-channel metal oxide semiconductor) control method and drive circuit

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