CN118965367B - BIOS startup method and device, storage medium and electronic device - Google Patents

Abstract

The embodiment of the application provides a BIOS starting method and device, a storage medium and electronic equipment, and relates to the field of computers, wherein the BIOS starting method comprises the steps of executing a first operation through a CPLD (complex programmable logic device) under the condition that the CPLD is connected to a power supply and first indication information sent by the BMC is obtained, wherein the first indication information is information sent by the BMC after the BMC verifies Flash, and after the first operation is executed, the state of a server is changed from a first state to a second state, wherein the first state is that the server is in a state of not being connected with the power supply, and the second state is that the server is in a state of being connected with the power supply and waiting for a starting instruction; under the condition that the CPLD acquires second indication information sent by the BMC, a reset signal is sent to the CPU through the CPLD, wherein the second indication information is information sent after the BMC verifies the appointed data stored in the CPU, the appointed data is information acquired by the CPU from Flash, and the reset signal is used for indicating the CPU to initialize according to a preset flow and starting the BIOS.

Description

BIOS (basic input output System) starting method and device, storage medium and electronic equipment

Technical Field

The embodiment of the application relates to the field of computers, in particular to a BIOS (basic input output system) starting method and device, a storage medium and electronic equipment.

Background

The Basic Input/Output System (BIOS) is a solidified software program started by the computer System, and is responsible for initializing computer hardware equipment, detecting whether the System hardware is normal and loading an operating System and the like, and is the basis for starting and running the computer System. Boot Guard (e.g., intel Boot Guard) is a root of trust based on CPU hardware, intended to ensure that a known and good BIOS is used to Boot the platform. Boot Guard cryptographically verifies the initial Boot block (Initial Boot Block, abbreviated IBB) of the BIOS to give control to the BIOS before the BIOS runs using an authentication code module (Authentication Code Module, abbreviated ACM). Under the condition that the IBB verification fails, boot Guard prevents the platform from starting to avoid the running of a potential and malicious BIOS, wherein the Boot Guard is realized through an Intel platform control hub (Platform Controller Hub, abbreviated as PCH), however, an Intel new generation platform BirchStream does not have PCH, so that functions which originally depend on PCH need to be realized by other chips or CPUs, namely, boot Guard functions which are originally executed by PCH need to be realized by other components.

In the related art, boot Guard is made by an Intel Platform firmware reliability (Platform FIRMWARE RESILIENCE, abbreviated as PFR) chip, but the PFR chip is not a necessary configuration of a product, and for a product with a non-PFR configuration, how to implement the Boot Guard requires system design consideration.

Aiming at the problem that a server without a PFR has no start-up protection function in the related art, no effective solution is proposed at present.

Disclosure of Invention

The embodiment of the application provides a BIOS starting method and device, a storage medium and electronic equipment, which at least solve the problem that a server without a PFR does not have a starting protection function.

According to one embodiment of the application, a BIOS starting method is provided, and is applied to a server, wherein the server comprises a complex programmable logic device CPLD, a baseboard management controller BMC, a Flash memory Flash of a basic input/output system BIOS and a central processing unit CPU, the method comprises the steps of executing a first operation through the CPLD when the CPLD is connected to a power supply and first indicating information sent by the BMC is acquired, wherein the first indicating information is information sent by the BMC after the Flash verification is passed, changing the state of the server from a first state to a second state after the first operation is executed, wherein the first state is the state that the server is not connected with the power supply, the second state is the state that the server is connected with the power supply and waits for a start-up instruction, and sending a reset signal to the CPU through the CPLD when the CPLD acquires the second indicating information sent by the BMC, wherein the second indicating information is information sent by the CPU after the CPU passes through the verification, the CPU is designated data sent by the BMC, and the CPU is designated to be reset according to a preset starting signal, and the reset signal is used for the initial starting of the CPU.

In an exemplary embodiment, the method further comprises disabling execution of the first operation by the CPLD when the CPLD is connected to a power source and the first indication information sent by the BMC is not acquired, and sending a third indication information to the CPU by the CPLD before the CPLD sends a reset signal to the CPU, wherein the power-on instruction is sent by the CPLD to the CPU, the power-on instruction is used for indicating start-up of the server, the first signal is used for indicating execution of a power-on time sequence by the CPU, sending a second signal to the CPU by the CPLD and disabling sending of the reset signal to the CPU by the CPLD, wherein the second signal is used for indicating that the CPU power source is in place, and sending a third indication information to the BMC by the CPLD when the CPLD acquires a third signal sent by the CPU, wherein the third signal is used for indicating that the CPU has acquired a specified module of the second signal to the CPU to send data to the MCTP for the integrated circuit to request the data to be stored in the memory module based on a specified data protocol, and the MCTP is used for checking the specified data in the integrated circuit module to verify the data.

In an exemplary embodiment, the method further includes sending, by the BMC, a check instruction to the CPU using 13C of MCTP based on SPDM when the BMC obtains the third indication information, determining, by the BMC, whether a target hash value of the specified data sent by the CPU in response to the check instruction is equal to a preset hash value or not when the BMC obtains the target hash value of the specified data, wherein the preset hash value is a hash value stored in advance by the BMC, determining that verification of the specified data stored in the CPU is successful when the BMC determines that the target hash value is equal to the preset hash value, and determining that verification of the specified data stored in the CPU fails when the BMC determines that the target hash value is not equal to the preset hash value.

In an exemplary embodiment, the method further comprises the steps of acquiring first data and second data from the Flash through the BMC based on a serial peripheral interface SPI when the BMC is connected to a power supply for the first time within preset time, wherein the second data are obtained after the first data are operated by using a target algorithm, operating the first data through the BMC by using the target algorithm to obtain third data, determining that the Flash is verified to pass when the second data are determined to be equal to the third data, and determining that the Flash is verified to fail when the second data are determined to be unequal to the third data.

In an exemplary embodiment, the method further comprises sending, by the BMC, first alarm information when the BMC fails to verify the Flash, wherein the first alarm information is used for indicating that data in the Flash is tampered with, and/or sending, by the BMC, second alarm information when the BMC fails to verify specified data stored in the CPU, wherein the second alarm information is used for indicating that the specified data stored in the CPU is tampered with.

In an exemplary embodiment, the method further comprises refreshing the Flash by using the acquired BIOS image through the BMC or instructing the CPU to start the BIOS based on a target Flash when the BMC fails to verify the Flash or fails to verify the designated data stored in the CPU, wherein the server further comprises the target Flash, and a BIOS program is stored in the target Flash.

In an exemplary embodiment, the method further comprises the steps of after the BMC sends the second indication information to the CPLD, sending a query instruction to the CPU by the BMC based on SPDM after a preset time by using I3C of MCTP, and sending third warning information by the BMC when the BMC obtains response information sent by the CPU in response to the query instruction and the response information is used for indicating the BIOS start failure, wherein the third warning information is used for indicating the BIOS start failure.

According to another embodiment of the application, the BIOS starting device is applied to a server, the server comprises a complex programmable logic device CPLD, a baseboard management controller BMC, a Flash memory Flash of a basic input/output system BIOS and a central processing unit CPU, the BIOS starting device comprises an execution module and a first sending module, wherein the execution module is used for executing a first operation through the CPLD when the CPLD is connected to a power supply and obtains first instruction information sent by the BMC, the first instruction information is information sent by the BMC after the Flash verification is passed, after the first operation is executed, the state of the server is changed from a first state to a second state, the first state is that the server is in a state that the server is connected with the power supply and waits for a start-up instruction, the first sending module is used for sending a reset signal to the CPU through the CPLD when the CPLD obtains second instruction information sent by the BMC, the second instruction information is sent by the CPLD, the CPU is sent by the CPU after the CPU is appointed to be reset, and the CPU is scheduled to be started up according to the initial data after the instruction information is sent by the CPU, and the CPU is scheduled to be verified.

According to a further embodiment of the application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

According to a further embodiment of the application there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

According to a further embodiment of the present application, there is also provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

According to the application, after the BMC passes the verification of Flash, the CPLD sends the first indication information to the CPLD, the CPLD executes the first operation after receiving the first indication information, the server changes from the state of not being connected with the power supply to the state of being connected with the power supply and waiting for starting up, after the BMC passes the verification of the appointed data stored in the CPU, the CPLD sends the second indication information to the CPLD, the CPLD sends the reset signal to the CPU after receiving the second indication information, the CPU initializes according to the preset flow after receiving the reset signal, and the BIOS is started. Because the BMC is used for completing verification of the appointed data stored in the Flash and the CPU, and the CPLD sends a reset signal to the CPU after the verification is passed, the startup protection function is realized, and the problem that a server without the PFR does not have the startup protection function is solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 is a block diagram of the hardware architecture of a server device for a BIOS boot method according to an embodiment of the application;

FIG. 2 is a schematic diagram of interaction of a PFR chip with a BMC according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an alternative BIOS boot flow according to an embodiment of the application;

Fig. 4 is a schematic diagram illustrating interaction between a CPLD and a BMC according to an embodiment of the present application;

FIG. 5 is a flow chart of an alternative BMC verifying Flash according to an embodiment of the application;

FIG. 6 is a flow chart of an alternative BMC validating CPU internal data in accordance with an embodiment of the present application;

FIG. 7 is a flowchart of an alternative factory side informing a BMC of hash values in accordance with an embodiment of the present application;

FIG. 8 is a flowchart of an alternative BMC detecting that boot protection is functioning properly, according to an embodiment of the application;

FIG. 9 is a flowchart of an alternative BIOS Flash informing the BMC of the hash value in accordance with an embodiment of the present application;

FIG. 10 is a flowchart of an alternative BIOS system start-up detection according to an embodiment of the application;

FIG. 11 is a block diagram illustrating a BIOS boot device according to an embodiment of the application;

fig. 12 is a schematic structural view of an alternative electronic device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The embodiment of the method for starting the BIOS provided by the embodiment of the application can be executed in a server device or a similar computing device. Taking the operation on the server device as an example, fig. 1 is a block diagram of a hardware structure of the server device of a BIOS startup method according to an embodiment of the present application. As shown in fig. 1, the server apparatus may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU, a programmable logic device FPGA, or the like, and a memory 104 for storing data, wherein the server apparatus may further include a transmission apparatus 106 for communication functions and an input-output apparatus 1 08. It will be appreciated by those of ordinary skill in the art that the architecture shown in fig. 1 is merely illustrative and is not intended to limit the architecture of the server apparatus described above. For example, the server device may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to a BIOS start method in the embodiment of the present application, and the processor 102 executes the computer program stored in the memory 104 to perform various functional applications and data processing, that is, to implement the above-described method. The memory 104 may include high speed random access memory, but may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid state memory. In some examples, the memory 104 may further include memory remotely located with respect to the processor 102, which may be connected to the server device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as a NIC) that may be connected to other network devices via a base station so that communications may not be performed over the internet da. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating wirelessly over the internet da.

To better understand the BIOS start-up Mai flow, the related art BIOS start-up Mai flow is explained as follows:

According to one scheme, a Boot Guard function is realized by using a PFR chip, so that Mai BIOS is started, FIG. 2 shows an interaction process of a PFR chip and a baseboard management controller (Baseboard Management Controller, abbreviated as BMC) BMC, the PFR is an independent Field-Programmable gate array (GATE ARRAY, abbreviated as FPGA) chip, a serial external Memory (SERIAL PERIPHERAL INTERFACE READ-Only Memory, abbreviated as SPI ROM) is checked before the BMC/BIOS operates, boot Guard verification is performed on a central processor (Central Processing Unit, abbreviated as CPU) after the BMC/BIOS is started, but not all servers are provided with the PFR chip, the PFR firmware design is not hardware, the complexity of the PFR is relatively high, the PFR resources are relatively rich, and the cost is relatively high.

In order to solve the above-mentioned problems in the related art, a BIOS start Mai method is provided in the present embodiment, and is applied to a server, where the server includes a complex programmable device CPLD, a baseboard management controller BMC, a Flash memory Flash of a basic input/output system BIOS, and a central processing unit CPU, as shown in FIG. 3, the process includes the following steps S302-S304:

Step S302, executing a first operation through the CPLD when the CPLD is connected to a power supply and the first instruction information sent by the BMC is obtained, wherein the first instruction information is information sent by the BMC after the Flash is verified to pass, and after the first operation is executed, the state of the server is changed from a first state to a second state, wherein the first state is that the server is in a state of being not connected with the power supply, and the second state is that the server is in a state of being connected with the power supply and waiting for a starting instruction;

Optionally, when the server system is connected to an AC power supply (ALTERNATING CURRENT, abbreviated as AC), the BMC starts Mai to perform step 1 in fig. 4, that is, the BMC acquires data from Flash by using a serial peripheral interface (SERIAL PERIPHERAL INTERFACE, abbreviated as SPI) to verify Flash, fig. 5 illustrates a flow of verifying Flash by the BMC, the server system is first in a first state, that is, a lowest power consumption state (G3 state), when the AC is plugged in, the CPLD prohibits the execution of the first operation and waits for the first indication information of the BMC, when the BMC determines that the BMC is powered on for the first time, and the server is not in a second state (S5 state), the BMC starts to switch and verify Flash, and sends the first indication information to the CPLD after verification is passed, and then the CPLD performs the first operation after receiving the first indication information.

It should be noted that, because the current BMC has a ready interface for accessing the BIOS SPI (because the BMC can refresh the BIOS Flash and has an interface for reading and writing the BIOS Flash), the hardware design of the BMC can be not additionally modified, and the increase of the resources of the CPLD caused by the fact that the verification work of the Flash is handed over to the CPLD for execution is avoided.

In an exemplary embodiment, the method further comprises the steps of S11-S13:

Step S11, under the condition that the BMC is connected to a power supply for the first time within a preset time, acquiring first data and second data from the Flash based on a serial peripheral interface SPI through the BMC, wherein the second data is obtained after the first data is operated by using a target algorithm;

Optionally, the target algorithm includes, but is not limited to, a hash algorithm.

The hash algorithm is an algorithm for converting input data of an arbitrary length into an output value of a fixed length, and the core idea is to generate a unique hash value, called a hash value, by performing a series of calculations and transformations on the input data.

Step S12, calculating the first data by the BMC through the target algorithm to obtain third data;

And step S13, determining that the Flash is verified to pass under the condition that the second data is equal to the third data, and determining that the Flash is verified to fail under the condition that the second data is not equal to the third data.

Alternatively, as shown in fig. 5, if the BMC fails to verify Flash, the BMC will report an error.

By the steps, the BMC can rapidly and accurately verify the Flash. In addition, the work of verifying Flash by the PFR chip in the related technology is completed by the BMC, and additional reorganization of the BMC is not needed, so that the resource requirement on system configuration, particularly CPLD, is greatly reduced, the starting process of the BIOS is more universal, and meanwhile, the economic cost is greatly reduced.

In one exemplary embodiment, the method further comprises the step of prohibiting execution of the first operation by the CPLD if the CPLD is connected to a power source and the first indication information sent by the BMC is not acquired;

It should be noted that, in order to ensure safe startup of the BIOS, the CPLD needs to perform the first operation after verification of the BIOS program in Flash is successful, and when the CPLD does not receive the first indication information sent by the BMC, it is described that the CPLD does not know whether the BIOS program in Flash is tampered, so that the first operation is not performed.

In addition, when the BMC fails to verify the Flash, the first instruction information is not sent to the CPLD.

Step S304, under the condition that the CPLD acquires second instruction information sent by the BMC, a reset signal is sent to the CPU through the CPLD, wherein the second instruction information is information sent after the BMC verifies that the specified data stored in the CPU passes, the specified data is information acquired by the CPU from the Flash, and the reset signal is used for indicating the CPU to initialize according to a preset flow and starting the BIOS.

Step S302-S304 is that after the BMC passes the verification of Flash, the CPLD sends first indication information to the CPLD, the CPLD executes a first operation after receiving the first indication information, the server changes from a state of not being connected with a power supply to a state of being connected with the power supply and waiting for starting up, after the BMC passes the verification of specified data stored in the CPU, the CPLD sends second indication information to the CPLD, the CPLD sends a reset signal to the CPU after receiving the second indication information, the CPU initializes according to a preset flow after receiving the reset signal, and starts the BIOS. Because the BMC is used for completing verification of the appointed data stored in the Flash and the CPU, and the CPLD sends a reset signal to the CPU after the verification is passed, the startup protection function is realized, and the problem that a server without the PFR does not have the startup protection function is solved.

In an exemplary embodiment, before sending a reset signal to the CPU by the CPLD, the method further comprises the steps of S21-S23:

Step S2 1, under the condition that the CPLD acquires a starting instruction, a first signal is sent to the CPU through the CPLD, wherein the starting instruction is used for indicating to start the server, and the first signal is used for indicating the CPU to execute starting time sequence;

Step S22, a second signal is sent to the CPU through the CPLD, and the reset signal is forbidden to be sent to the CPU through the CPLD, wherein the second signal is used for indicating that the CPU power supply is in place;

optionally, fig. 6 illustrates a flow of the BMC verifying the internal data of the CPU, and the second signal is the sys_power_ok signal in fig. 6.

It should be noted that, the CPLD sends a sys_power_ok signal to the CPU to inform the server that its POWER source is already operating normally, and the system may start to operate. This signal can be used as an indication of system start-up to ensure that the system will not start operating until the power is normal, to prevent system failure or damage due to power problems, and to ensure system stability and reliability.

Alternatively, the Reset signal is the Reset signal in fig. 6.

Step S23, when the CPLD acquires a third signal sent by the CPU, third indication information is sent to the BMC through the CPLD, wherein the third signal is a signal which is sent by a specified module of the CPU after acquiring the second signal and is used for requesting to verify the specified data stored in the CPU, the third indication information is used for indicating the BMC to perform data interaction with the CPU based on a security protocol data model SPDM by using an improved integrated circuit interconnection bus I3C of a management component transmission protocol MCTP so as to verify the specified data stored in the CPU.

Optionally, as shown in step 3 in fig. 4, the BMC has an intelligent interconnect control interface (I3C for short), a security protocol data model protocol address (Security Protocol and Data Model IP for short, SPDM IP) and a management component transport protocol (MANAGEMENT COMPONENTTRANSPORT PROTOCOL for short, MCTP) to perform communication authentication with the CPU.

It should be noted that, at present, the BMC manages the CPU through the I3C, for example, obtains information such as temperature, state, and register of the CPU, so the BMC may use the I3C interface to complete the Boot Guard function, that is, the BMC also has an existing interface for accessing the CPU through the I3C, without additional modification to the hardware design.

Alternatively, the designated module is an S3M module and the third signal is the pltrst_sync signal in fig. 6.

Optionally, after receiving the sys_power_ok signal, the internal S3M module of the CPU may issue a pltrst_sync signal indicating that the internal data of the CPU is checked.

It should be noted that, through the above steps, the CPLD only completes the reception of the signal ready by the CPU and notifies the BMC to verify the internal data of the CPU, and then the BMC completes the verification of the Flash and the specified data stored in the CPU, thereby completing the implementation of the startup protection function, avoiding the use of the PFR chip, and also requiring no CPLD to verify the internal data of the CPU, saving resources, and greatly reducing the cost.

In an exemplary embodiment, the method further comprises the following steps S3 1-S33:

step S31, when the BMC acquires the third indication information, sending a check instruction to the CPU by using the I3C of MCTP based on SPDM through the BMC;

Step S32, under the condition that the BMC obtains a target hash value of the specified data sent by the CPU in response to the verification instruction, determining whether the target hash value is equal to a preset hash value or not through the BMC, wherein the preset hash value is a hash value prestored by the BMC;

optionally, as shown in fig. 7, when the BMC is started, the factory end checks Boot Guard and a preset hash value of the BMC, and the factory end sends a first command to the BMC to determine whether the BMC stores the preset hash value, and if the BMC does not have the preset hash value, the factory end presets the hash value and writes the preset hash value into the BMC;

optionally, as shown in fig. 8, when the BMC is started, the BMC detects whether the startup protection function is started and the preset hash value exists, if yes, the BMC executes a flow corresponding to the startup protection function, and if not, the BMC does not execute a flow corresponding to the startup protection function and works normally.

Optionally, as shown in fig. 9, after the BMC is started, an update flow of the BIOS Flash is started, and the hash value is transmitted to the BMC through the refresh tool, so as to ensure that a preset hash value stored in the BMC corresponds to the BIOS program in the Flash.

And step S33, when the BMC determines that the target hash value is equal to a preset hash value, determining that verification of the specified data stored in the CPU is successful, and when the BMC determines that the target hash value is not equal to the preset hash value, determining that verification of the specified data stored in the CPU is failed.

Through the steps, the BMC determines that the CPU has not been tampered after obtaining the data in the Flash through verification of the internal data of the CPU, and in addition, through the verification of the internal data of the CPU, the BMC can avoid the use of a PFR chip or a CPLD to verify the CPU, thereby saving system resources and saving cost.

In an exemplary embodiment, the method further comprises the following step S4 1 and/or step S42:

Step S41, under the condition that the BMC fails to verify the Flash, sending first alarm information through the BMC, wherein the first alarm information is used for indicating that the data in the Flash is tampered;

And step S42, when the BMC fails to verify the specified data stored in the CPU, sending second alarm information through the BMC, wherein the second alarm information is used for indicating that the specified data stored in the CPU is tampered.

Optionally, tampered data in Flash and/or tampered specified data stored in CPU may be directly output or recorded through a serial port or log, etc. to inform the user.

It should be noted that, the user receives the first warning information and/or the second warning information, so as to timely know that the data in Flash and/or the specified data stored in the CPU are tampered, so that a quick response can be made.

In an exemplary embodiment, the method further comprises the step of refreshing the Flash by using the acquired BIOS image through the BMC or instructing the CPU to start the BIOS based on a target Flash in the case that the BMC fails to verify the Flash or fails to verify the designated data stored in the CPU, wherein the server further comprises the target Flash, and a BIOS program is stored in the target Flash.

Optionally, the BMC may restore the BIOS image through a Flash (TRANS FLASH, abbreviated as TF) card and/or an Embedded multimedia card (Embedded Multi MEDIA CARD, abbreviated as EMMC), or grasp the BIOS image through a network, or switch to another BIOS Flash, so as to greatly improve flexibility of the BMC in implementing a restoration mechanism.

In an exemplary embodiment, the method further comprises the following steps S5 1-S52:

step S5 1, after the BMC sends the second instruction information to the CPLD, sending a query instruction to the CPU by using the I3C of MCTP based on SPDM through the BMC after preset time;

And step S52, when the BMC acquires response information sent by the CPU in response to the query instruction and the response information is used for indicating the BIOS start failure, third warning information is sent through the BMC, wherein the third warning information is used for indicating the BIOS start failure.

Optionally, fig. 10 illustrates a detection flow of the BIOS start-up flow, where the BMC detects the start-up of the BIOS through SPDM over MCTPover I C to verify whether the CPU successfully starts up the BIOS.

It will be apparent that the embodiments described above are merely some, but not all, embodiments of the invention. For better understanding of the above method, the following description will explain the above process with reference to the examples, but is not intended to limit the technical solution of the embodiments of the present invention, specifically:

1. as shown in fig. 4, the function PRoT is implemented by the BMC and is divided into three parts:

The first part is that step 1 in FIG. 4, verify Flash;

Step 3 and step 4 in FIG. 4, verifying whether the information read by CPU from Flash (i.e. the above CPU internal data) is correct;

third, in step 8 of FIG. 4, BIOS system start-up is detected.

2. The description about the above first section is as follows:

1. referring to the flow in fig. 5, when the server is in the G3 state (i.e., the first state), the AC is inserted, the CPLD stops the subsequent flow, waits for the BMC to power up and verifies that the SPI Flash passes, and then the CPLD executes the subsequent flow again;

2. if the BMC is powered on for the first time and the server system is in a non-S5 state (namely the second state), the BMC can switch and verify the BIOS SPI Flash da line;

3. after the verification of the BMC on the Flash is passed, informing the CPLD that the CPLD can continue to normally power on da lines, and if the verification of the BMC on the Flash fails, reporting an error by da lines;

3. the description about the above second section is as follows:

1. Referring to the flow in fig. 6, when the system receives a start-up instruction or signal, a start-up flow is initiated;

2. the CPLD starts to execute the starting time sequence, and after execution is completed, a SYS_POWER_OK signal is sent to indicate that the Power is ready;

3. After Power is ready, the CPLD needs to pull the CPU Reset signal (i.e. the Reset signal) to ensure that the CPU will not start (in order to wait for the BMC to complete the internal data verification of the CPU);

4. After receiving the Power OK signal, the S3M module in the CPU sends a PLTRST_SYNC signal to instruct the BMC to verify the data da lines in the CPU, the BMC acquires the HASH value of the information stored in the CPU through SPDM over MCTP over I C, the HASH value is not compared with the HASH value already known in the BMC, if the HASH value is consistent, the verification is passed, otherwise, the verification is failed;

5. if the BMC checks successfully, the result is informed to the main board CPLD to execute the subsequent starting-up flow, the main board CPLD releases the CPU Reset, and the whole BIOS starting-up process is started.

3. The third part is described below with reference to the flowchart in fig. 10, where the BMC detects the BIOS start Mai through SPDM over MCTP over I C.

It should be noted that the present application also has the advantages of (1) no expansion of flexibility in configuration, whether the system supports Boot Guard and which functions of the Boot Guard are supported, switch can be realized by configuration, and a system administrator is allowed to customize a safe start Mai flow according to needs, (2) compatibility, in the existing system, the Boot Guard can be used as an additional function of a BMC to enhance the safe start Mai function without large-scale hardware replacement, and (3) maintenance cost is reduced, and the BMC is helpful for reducing maintenance cost and complexity of the system through remote management and automatic security check.

In summary, the invention aims to design a device which can realize Boot Guard function (BIOS safe start) through BMC without PCR chip. By modifying the BMC code to replace the possible addition of one chip or to retrofit an existing chip to a more costly chip.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiment also provides a BIOS starting device which is applied to a server, wherein the server comprises a complex programmable logic device CPLD, a baseboard management controller BMC, a Flash memory Flash of a basic input/output system BIOS and a central processing unit CPU, and the BIOS starting device is used for realizing the embodiment and the preferred implementation mode, and is not described again. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the modules described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

FIG. 11 is a block diagram of a BIOS boot device according to an embodiment of the application, the device comprising:

An execution module 1102, configured to execute a first operation by using the CPLD when the CPLD is connected to a power supply and obtains first instruction information sent by the BMC, where the first instruction information is information sent by the BMC after the BMC verifies that the Flash passes, and after the first operation is executed, the state of the server is changed from a first state to a second state, where the first state is a state in which the server is not connected to the power supply, and the second state is a state in which the server is connected to the power supply and waits for a startup instruction;

A first sending module 1104, configured to send, by using the CPLD, a reset signal to the CPU when the CPLD obtains second instruction information sent by the BMC, where the second instruction information is information sent by the BMC after verification of specified data stored in the CPU is passed, the specified data is information obtained by the CPU from the Flash, and the reset signal is used to instruct the CPU to initialize according to a predetermined flow, and start the BIOS.

The device sends the first indication information to the CPLD after the BMC passes the verification of Flash, the CPLD executes the first operation after receiving the first indication information, the server changes from the state of not being connected with the power supply to the state of being connected with the power supply and waiting for starting, the BMC sends the second indication information to the CPLD after passing the verification of the appointed data stored in the CPU, the CPLD sends the reset signal to the CPU after receiving the second indication information, and the CPU initializes according to a preset flow after receiving the reset signal and starts the BIOS. Because the BMC is used for completing verification of the appointed data stored in the Flash and the CPU, and the CPLD sends a reset signal to the CPU after the verification is passed, the startup protection function is realized, and the problem that a server without the PFR does not have the startup protection function is solved.

In an exemplary embodiment, the execution module 1102 is further configured to prohibit execution of the first operation by the CPLD if the CPLD is connected to a power source and the first indication information sent by the BMC is not obtained, and the first sending module 1104 is further configured to send, by the CPLD, a first signal to the CPU if a start-up instruction is obtained by the CPLD before the CPLD sends the reset signal to the CPU, where the start-up instruction is used to instruct to turn on the server, the first signal is used to instruct the CPU to execute a start-up time sequence, send, by the CPLD, a second signal to the CPU and prohibit sending of the reset signal to the CPU by the CPLD, where the second signal is used to instruct that the CPU power source is in place, and send, by the CPLD, a third indication information to the CPU if the CPLD obtains a third signal sent by the CPU, where the third signal is used to instruct the CPU to send, by the third signal to instruct the mctr-send the CPU to the second module to instruct the CPU to send the data to the mctc to request the data exchange the data to the mctc to be checked by the mctc based on the data protocol, and the data packet is checked by the mctc.

In an exemplary embodiment, the device further comprises a second sending module, a determining module and a determining module, wherein the second sending module is used for sending a verification instruction to the CPU by using the I3C of MCTP based on SPDM through the BMC when the BMC obtains the third indication information, the determining module is used for determining whether the target hash value is equal to a preset hash value through the BMC when the BMC obtains the target hash value of the specified data sent by the CPU in response to the verification instruction, the preset hash value is the hash value stored in advance by the BMC, the verification success of the specified data stored in the CPU is determined when the BMC determines that the target hash value is equal to the preset hash value, and the verification failure of the specified data stored in the CPU is determined when the BMC determines that the target hash value is not equal to the preset hash value.

In an exemplary embodiment, the device further comprises a processing module, a determining module and a determining module, wherein the processing module is used for acquiring first data and second data from the Flash based on a serial peripheral interface SPI through the BMC when the BMC is connected to a power supply for the first time within a preset time, the second data are data obtained after the first data are operated by using a target algorithm, the BMC is used for operating the first data by using the target algorithm to obtain third data, and the determining module is used for determining that the Flash is verified to pass when the second data are equal to the third data, and determining that the Flash is verified to fail when the second data are not equal to the third data.

In an exemplary embodiment, the second sending module is further configured to send, through the BMC, first alarm information when the BMC fails to verify the Flash, where the first alarm information is used to indicate that data in the Flash is tampered with, and/or send, through the BMC, second alarm information when the BMC fails to verify specified data stored in the CPU, where the second alarm information is used to indicate that the specified data stored in the CPU is tampered with.

In an exemplary embodiment, the processing module is further configured to refresh the Flash by using the obtained BIOS image or instruct the CPU to start the BIOS based on a target Flash when the BMC fails to verify the Flash or fails to verify the specified data stored in the CPU, where the server further includes the target Flash, and the target Flash stores a BIOS program therein.

In an exemplary embodiment, the second sending module is further configured to send, after the BMC sends the second indication information to the CPLD, a query instruction to the CPU by using an I3C of MCTP based on SPDM after a preset time, and send, by the BMC, third warning information when the BMC obtains response information sent by the CPU in response to the query instruction and the response information is used to indicate that the BIOS fails to start, where the third warning information is used to indicate that the BIOS fails to start.

It should be noted that each of the above modules may be implemented by software or hardware, and the latter may be implemented by, but not limited to, the above modules all being located in the same processor, or each of the above modules being located in different processors in any combination.

Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

Alternatively, in the present embodiment, the above-described computer program may be configured to execute the following steps by the computer program:

S1, executing a first operation through the CPLD when the CPLD is connected to a power supply and acquires first indication information sent by the BMC, wherein the first indication information is information sent by the BMC after the Flash is verified to pass, and after the first operation is executed, changing the state of the server from a first state to a second state, wherein the first state is that the server is in a state of being not connected with the power supply, and the second state is that the server is in a state of being connected with the power supply and waiting for a starting instruction;

S2, under the condition that the CPLD acquires second instruction information sent by the BMC, a reset signal is sent to the CPU through the CPLD, wherein the second instruction information is information sent after the BMC verifies that specified data stored in the CPU passes, the specified data is information obtained by the CPU from the Flash, and the reset signal is used for indicating the CPU to initialize according to a preset flow and starting the BIOS.

In an exemplary embodiment, the computer readable storage medium may include, but is not limited to, a U disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, etc. various media in which a computer program may be stored.

An embodiment of the application also provides an electronic device comprising a memory 1202 and a processor 1204, as shown in fig. 12, the memory 1202 having stored therein a computer program, the processor 1204 being arranged to perform the steps of any of the method embodiments described above by means of the computer program.

Alternatively, in the present embodiment, the above-described processor 1 204 may be configured to execute the following steps by a computer program:

S1, executing a first operation through the CPLD when the CPLD is connected to a power supply and acquires first indication information sent by the BMC, wherein the first indication information is information sent by the BMC after the Flash is verified to pass, and after the first operation is executed, changing the state of the server from a first state to a second state, wherein the first state is that the server is in a state of being not connected with the power supply, and the second state is that the server is in a state of being connected with the power supply and waiting for a starting instruction;

S2, under the condition that the CPLD acquires second instruction information sent by the BMC, a reset signal is sent to the CPU through the CPLD, wherein the second instruction information is information sent after the BMC verifies that specified data stored in the CPU passes, the specified data is information obtained by the CPU from the Flash, and the reset signal is used for indicating the CPU to initialize according to a preset flow and starting the BIOS.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

Alternatively, it will be appreciated by those of ordinary skill in the art that the configuration shown in fig. 12 is merely illustrative, and that fig. 12 is not intended to limit the configuration of the electronic device described above. For example, the electronic device may also include more or fewer components (e.g., network interfaces, etc.) than shown in FIG. 12, or have a different configuration than shown in FIG. 12.

The memory 1202 may be used for storing software programs and modules, such as program instructions/modules corresponding to the BIOS startup method and the BIOS startup device in the embodiment of the present application, and the processor 1 204 executes the software programs and modules stored in the memory 1202, thereby executing various functional applications and data processing, i.e. implementing the BIOS startup method described above. Memory 1202 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, memory 1202 may further include memory located remotely from processor 1, which may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The memory 1202 may be, but is not limited to, used for storing information such as a system configuration file. As an example, as shown in fig. 12, the memory 1202 may include, but is not limited to, the execution module 1102 and the first sending module 1104 in the BIOS startup device. In addition, other module units in the above-mentioned BIOS startup device may be included, but are not limited to, and are not described in detail in this example.

Optionally, the transmission device 1206 is configured to receive or transmit data via a network. Specific examples of the network described above may include wired networks and wireless networks. In one example, the transmission means 1206 comprises a network adapter (Network Interface Controller, NIC) that can be connected to other network devices and routers via a network cable to communicate with the internet or a local area network. In one example, the transmission device 1 is a Radio Frequency (RF) module, which is used to communicate with the internet wirelessly.

The electronic device further comprises a display 1208 and a connection bus 1210 for connecting the individual module components of the electronic device.

Embodiments of the application also provide a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

Embodiments of the present application also provide another computer program product comprising a non-volatile computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

Embodiments of the present application also provide a computer program comprising computer instructions stored in a computer-readable storage medium, a processor of a computer device reading the computer instructions from the computer-readable storage medium, the processor executing the computer instructions to cause the computer device to perform the steps of any of the method embodiments described above.

It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. The BIOS starting method is characterized by being applied to a server, wherein the server comprises CPLD, BMC, BIOS Flash and CPU;

Comprising the following steps:

executing a first operation through the CPLD when the CPLD is connected to a power supply and acquires first indication information sent by the BMC, wherein the first indication information is information sent by the BMC after verification of the Flash, and after the first operation is executed, the state of the server is changed from a first state to a second state, wherein the first state is a state that the server is not connected with the power supply, and the second state is a state that the server is connected with the power supply and waits for a starting instruction;

Under the condition that the CPLD acquires second instruction information sent by the BMC, a reset signal is sent to the CPU through the CPLD, wherein the second instruction information is information sent by the BMC after verification of specified data stored in the CPU is passed, the specified data is information acquired by the CPU from the Flash, and the reset signal is used for indicating the CPU to initialize according to a preset flow and starting the BIOS;

Wherein, before the CPLD sends a reset signal to the CPU, the method further comprises:

Under the condition that the CPLD acquires a starting instruction, a first signal is sent to the CPU through the CPLD, wherein the starting instruction is used for indicating to start the server, and the first signal is used for indicating the CPU to execute a starting time sequence;

transmitting a second signal to the CPU by the CPLD and disabling the transmission of the reset signal to the CPU by the CPLD, wherein the second signal is used to indicate that the CPU power supply is in place;

And under the condition that the CPLD acquires a third signal transmitted by the CPU, transmitting third indication information to the BMC through the CPLD, wherein the third signal is a signal which is transmitted by a specified module of the CPU after acquiring the second signal and used for requesting to verify the specified data stored in the CPU, and the third indication information is used for indicating the BMC to perform data interaction with the CPU by using the I3C of MCTP based on SPDM so as to verify the specified data stored in the CPU.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The method further comprises the steps of:

And when the CPLD is connected to a power supply and the first indication information sent by the BMC is not acquired, prohibiting the execution of the first operation by the CPLD.

3. The method of claim 2, wherein the step of determining the position of the substrate comprises,

The method further comprises the steps of:

when the BMC acquires the third indication information, sending a check instruction to the CPU by using the I3C of MCTP based on SPDM by the BMC;

under the condition that the BMC acquires a target hash value of the specified data sent by the CPU in response to the verification instruction, determining whether the target hash value is equal to a preset hash value or not through the BMC, wherein the preset hash value is a hash value prestored by the BMC;

In the case that the BMC determines that the target hash value is equal to a preset hash value, determining that verification of the specified data stored in the CPU is successful, and under the condition that the BMC determines that the target hash value is not equal to a preset hash value, determining that verification of the designated data stored in the CPU fails.

4. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The method further comprises the steps of:

Under the condition that the BMC is connected to a power supply for the first time within a preset time, acquiring first data and second data from the Flash based on SPI by the BMC, wherein the second data is obtained by calculating the first data by using a target algorithm;

calculating the first data by the BMC through the target algorithm to obtain third data;

And under the condition that the second data is equal to the third data, determining that the Flash is verified, and under the condition that the second data is not equal to the third data, determining that the Flash is verified to be failed.

5. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The method further comprises the steps of:

Sending a first alarm message through the BMC under the condition that the BMC fails to verify the Flash, wherein the first alarm message is used for indicating that the data in the Flash is tampered with and/or

And under the condition that the BMC fails to verify the specified data stored in the CPU, sending second alarm information through the BMC, wherein the second alarm information is used for indicating that the specified data stored in the CPU is tampered.

6. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The method further comprises the steps of:

and under the condition that the BMC fails to verify the Flash or fails to verify the appointed data stored in the CPU, refreshing the Flash by using the acquired BIOS mirror image through the BMC or indicating the CPU to start the BIOS based on a target Flash, wherein the server further comprises the target Flash, and the BIOS program is stored in the target Flash.

7. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The method further comprises the steps of:

after the BMC sends the second instruction information to the CPLD, sending a query instruction to the CPU by using the I3C of MCTP based on SPDM after preset time;

And under the condition that the BMC acquires response information sent by the CPU in response to the query instruction and the response information is used for indicating the BIOS start failure, sending third warning information through the BMC, wherein the third warning information is used for indicating the BIOS start failure.

8. The BIOS starting device is characterized by being applied to a server, wherein the server comprises CPLD, BMC, BIOS Flash and CPU;

Comprising the following steps:

The execution module is used for executing a first operation through the CPLD when the CPLD is connected to a power supply and the first indication information sent by the BMC is obtained, wherein the first indication information is information sent by the BMC after the BMC verifies the Flash, and after the first operation is executed, the state of the server is changed from a first state to a second state, wherein the first state is that the server is in a state of not being connected with the power supply, and the second state is that the server is in a state of being connected with the power supply and waiting for a starting instruction;

A first sending module, configured to send a reset signal to the CPU through the CPLD when the CPLD obtains second instruction information sent by the BMC, where the second instruction information is information sent by the BMC after the second instruction information verifies that specified data stored in the CPU passes, the specified data is information obtained by the CPU from the Flash, and the reset signal is used to instruct the CPU to initialize according to a predetermined flow, and start the BIOS;

The first sending module is further configured to send, before sending, by the CPLD, a reset signal to the CPU, a first signal to the CPU by the CPLD when the CPLD obtains a startup instruction, where the startup instruction is used to instruct the server to start up, the first signal is used to instruct the CPU to perform startup timing, send, by the CPLD, a second signal to the CPU and prohibit sending, by the CPLD, the reset signal to the CPU, where the second signal is used to instruct the CPU to be in place, and send, by the CPLD, a third instruction message to the BMC when the CPLD obtains a third signal sent by the CPU, where the third instruction message is a signal sent by a specification module of the CPU after obtaining the second signal and used to request verification of the specified data stored in the CPU, and the third instruction message is used to instruct the BMC to interact with the CPU using an I3C of MCTP to verify the specified data in the CPU based on SPDM.

9. A computer-readable storage medium comprising,

The computer readable storage medium has stored therein a computer program, wherein the computer program when executed by a processor realizes the steps of the method as claimed in any of claims 1 to 7.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that,

The processor, when executing the computer program, implements the steps of the method as claimed in any one of claims 1 to 7.