CN118974872A - Electron beam corrector, preparation method thereof and scanning electron microscope - Google Patents

Abstract

The present application provides an electron beam corrector, a preparation method thereof and a scanning electron microscope. The electron beam corrector includes: a semiconductor substrate, a wiring layer located on the semiconductor substrate, and at least one correction electrode electrically connected to the wiring layer. The electron beam corrector is provided with at least one first through hole penetrating the semiconductor substrate and the wiring layer, and the inner wall of each first through hole is provided with at least one correction electrode, and at least part of each correction electrode is located in the wiring layer, and the correction electrode is an integrated structure. In the present application, by setting the correction electrode as an integrated structure, it is easier to form a correction electrode with better symmetry during the preparation process, so that the uniformity of the electric field formed by each correction electrode is better, and no overlay process is required to prepare the correction electrode, which reduces the process difficulty of preparing the correction electrode. In addition, the preparation process of the correction electrode is separated from the preparation process of each film layer in the wiring layer, and the preparation process of the wiring layer and the correction electrode will not affect each other.

Description

Electron beam corrector, preparation method thereof and scanning electron microscope Technical Field

The present application relates to the technical field of scanning electron microscopes, and in particular to an electron beam straightener, a preparation method thereof, and a scanning electron microscope.

Background Art

Scanning electron microscopes can scan the sample surface with a focused electron beam to obtain a sample surface image. Scanning electron microscopes can be used for sample imaging and surface analysis. For example, they can analyze the morphology of the material surface, the atomic number of the object, the surface composition, etc. Scanning electron microscopes are widely used in the semiconductor industry for wafer surface dimension measurement, surface defect analysis, electron beam lithography, etc.

The scanning electron microscope mainly consists of three parts, namely the vacuum system, the electron beam system and the imaging system. Among them, the electron beam system includes the electron beam source and the electron beam mirror group. Under normal circumstances, the electron beam emitted by the electron beam source cannot accurately enter the electron beam mirror group. In order to make the electron beam pass through the electron beam mirror group in parallel and reach the sample surface, an individual beam corrector (IBC) is required to correct the angle, position, astigmatism and other parameters of the electron beam, thereby improving the quality of electron beam imaging.

In the related art, the electron beam corrector includes a symmetrically arranged electrode structure, and an electric field is formed by applying a voltage to the electrode structure to control the deflection of the electron beam. In order to make the electric field formed by the electrode structure more uniform and facilitate the control of the electron beam deflection, the symmetry of the electrode structure is very high. In addition, since the electrode structure is composed of multiple metal layers, during the preparation process, good process consistency and stability are required to prepare an electrode structure with better symmetry. In addition, it is necessary to use an overlay process to prepare the electrode structure. In order to ensure the accuracy of the same electrode structure, the overlay accuracy of the preparation process is required to be high. Therefore, the preparation process of the electron beam corrector in the related art is more difficult.

Summary of the invention

The present application provides an electron beam corrector, a preparation method thereof and a scanning electron microscope, so as to reduce the difficulty of the preparation process of the electron beam corrector.

In the first aspect, the present application provides an electron beam corrector, which may include: a semiconductor substrate, a wiring layer located on the semiconductor substrate, and at least one correction electrode electrically connected to the wiring layer. The electron beam corrector is provided with at least one first through hole penetrating the semiconductor substrate and the wiring layer, and the inner wall of each first through hole is provided with at least one correction electrode, and at least part of each correction electrode is located in the wiring layer, and the correction electrode is an integrated structure. In an embodiment of the present application, the correction electrode is set as an integrated structure, and it is easier to form a correction electrode with better symmetry during the preparation process, so that the uniformity of the electric field formed by each correction electrode is better, and no overlay process is required to prepare the correction electrode, thereby reducing the process difficulty of preparing the correction electrode. In addition, during the preparation process of the electron beam corrector, the preparation process of the correction electrode can be separated from the preparation process of each film layer in the wiring layer, and the preparation process of the wiring layer and the preparation process of the correction electrode will not affect each other.

In one implementation of the present application, the correction electrode may be located only in the wiring layer. In this way, during the preparation process, the wiring layer may be etched to form a second through hole, and the second through hole may be filled with a conductive material to obtain the correction electrode. The preparation process of the correction electrode is relatively simple and the preparation cost is relatively low.

In another implementation of the present application, a portion of the correction electrode may be located in the wiring layer, and another portion may be located in the semiconductor substrate. Thus, the total height of the correction electrode is increased, so that the length of the path of the correction electron beam is longer, and the correction effect of the electron beam is better. During the preparation process, the wiring layer and the semiconductor substrate may be etched to obtain a second through hole, and a conductive material may be filled in the second through hole to form a correction electrode.

In a possible implementation, the correction electrode may penetrate the semiconductor substrate, that is, a portion of the correction electrode is located in the wiring layer, and another portion extends to the bottom surface of the semiconductor substrate, so that the total height of the correction electrode can be further increased, thereby increasing the length of the path of the correction electron beam.

Optionally, the semiconductor substrate may include semiconductor materials such as silicon. The semiconductor substrate has certain conductive properties. In order to insulate the correction electrode from the semiconductor substrate, an insulating layer may be provided between the correction electrode and the semiconductor substrate.

In a possible implementation, the correction electrode is electrically connected to the wiring layer at the end facing away from the semiconductor substrate. To prevent diffusion of metal ions in the correction electrode, a barrier layer is provided on the side of the correction electrode and the end facing away from the wiring layer.

In a specific implementation, in order to prevent the wiring layer and the semiconductor substrate from affecting the electric field formed by the correction electrode, a portion of at least one correction electrode may be embedded in the inner wall of the first through hole.

In another implementation of the present application, when the correction electrode is only located in the wiring layer, the side of the correction electrode facing the first through hole can be covered by the wiring layer. During the preparation process, it is necessary to etch the wiring layer and the semiconductor substrate after forming the correction electrode and each film layer in the wiring layer to obtain a first through hole that penetrates the semiconductor substrate and the wiring layer. The side of the correction electrode facing the first through hole is set to be covered by the wiring layer. In the process of forming the first through hole, the process accuracy of etching the wiring layer and the semiconductor substrate can be reduced, that is, the process difficulty is reduced. Similarly, when a part of the correction electrode is located in the wiring layer and the other part is located in the semiconductor substrate, the side of the correction electrode facing the first through hole is covered by the wiring layer and the semiconductor substrate. In this way, the process accuracy of etching the wiring layer and the semiconductor substrate can also be reduced, that is, the process difficulty is reduced.

In a possible implementation, the correction electrode is a strip-shaped structure that is consistent with the extension direction of the first through hole. In this way, the path of the correction electron beam formed by the correction electrode can be made longer, so that the correction effect of the electron beam is better.

Optionally, in order to improve the uniformity of the electric field formed by each correction electrode, at least two correction electrodes are evenly distributed on the inner wall of each first through hole.

In a possible implementation, a semiconductor device is provided on a side of the semiconductor substrate close to the wiring layer. For example, the semiconductor device may be a transistor. Of course, the semiconductor device may also be other devices, which are not limited here. The wiring layer may include: a first type of connecting wire located on the semiconductor substrate, and a second type of connecting wire located on the side of the first type of connecting wire away from the semiconductor substrate. The first type of connecting wire connects the semiconductor device tube and the second type of connecting wire, the second type of connecting wire is located on the side of the correction electrode away from the semiconductor substrate, and the second type of connecting wire is electrically connected to the end of the correction electrode away from the semiconductor substrate. In this way, the semiconductor device is electrically connected to the correction electrode through the first type of connecting wire and the second type of connecting wire, so that the voltage applied to the correction electrode can be controlled by the semiconductor device. Optionally, a dielectric layer is provided between the first type of connecting wire and the semiconductor substrate, and between the second type of connecting wire and the first type of connecting wire, respectively. The first type of connecting wire is electrically connected to the semiconductor substrate through a connecting hole in the dielectric layer, and the second type of connecting wire is electrically connected to the first type of connecting wire through a connecting hole in the dielectric layer.

In a possible implementation, the wiring layer may further include: a shielding layer located on the side of the second type of connecting wire away from the semiconductor substrate, and a dielectric layer is provided between the shielding layer and the second type of connecting wire. By providing the shielding layer, it is possible to prevent external factors from affecting components such as the correction electrode, the first type of connecting wire, and the second type of connecting wire, thereby ensuring that the uniformity of the electric field formed by the correction electrode is good.

In addition, the wiring layer may further include: a passivation layer located on the side of the shielding layer away from the semiconductor substrate, and a dielectric layer is provided between the passivation layer and the shielding layer. The components inside the wiring layer can be protected by providing the passivation layer.

In a possible implementation, the cross-section of the correction electrode in the first direction is elliptical, circular, rectangular, trapezoidal or sector-shaped, and the first direction is a direction parallel to the surface of the semiconductor substrate. Of course, the cross-section of the correction electrode may also be in other shapes, which are not limited here. In specific implementation, the cross-sectional area, cross-sectional shape, and total height of the correction electrode may be set according to actual needs, and the design flexibility of the correction electrode is relatively high.

In a second aspect, the present application also provides a method for preparing any of the above-mentioned electron beam straighteners, including:

forming a partial film layer of a wiring layer on a semiconductor substrate;

At least one correction electrode is formed to penetrate at least a portion of the wiring layer; each correction electrode is electrically connected to the wiring layer, and the correction electrodes are an integrated structure;

After forming each film layer of the wiring layer, a first through hole penetrating the semiconductor substrate and the wiring layer is formed; at least one correction electrode is arranged on the inner wall of each first through hole.

In the embodiment of the present application, the correction electrode is an integrated structure, and during the preparation process, it is easier to form a correction electrode with good symmetry, so that the uniformity of the electric field formed by each correction electrode is better, and no overlay process is required to prepare the correction electrode, thereby reducing the process difficulty of preparing the correction electrode. In addition, the preparation process of the correction electrode is separated from the preparation process of each film layer in the wiring layer, and the preparation process of the wiring layer and the preparation process of the correction electrode will not affect each other.

In a specific implementation, before forming a partial film layer of the wiring layer on the semiconductor substrate, the method may further include:

A semiconductor device is formed on the surface of a semiconductor substrate. Taking a transistor as an example, a doping process can be used to form a channel region, a source region, a drain region, etc. of the transistor on the surface of the semiconductor substrate.

The partial film layer forming the wiring layer on the semiconductor substrate may include:

A first type of connecting wire is formed on a side of the semiconductor substrate having a semiconductor device, and the first type of connecting wire is electrically connected to the semiconductor device. In order to enable the semiconductor device to be electrically connected to the second type of connecting wire formed subsequently, the wiring layer may include multiple layers of first type of connecting wires. During the preparation process, a dielectric layer may be formed on the surface of the semiconductor substrate, and the dielectric layer may be etched to obtain connecting holes. Then, a first type of connecting wire is formed on the surface of the dielectric layer, so that the first type of connecting wire is electrically connected to the semiconductor device through the connecting holes. Afterwards, a dielectric layer and a first type of connecting wire are prepared layer by layer in a similar manner to form a stacked multilayer first type of connecting wire. Optionally, the first type of connecting wire may be prepared using metallic copper. Of course, the first type of connecting wire may also be prepared using other conductive materials, which are not limited here.

In the embodiments of the present application, the correction electrode can be prepared in a variety of ways. Two preparation methods of the correction electrode are described in detail below.

Preparation method 1: The correction electrode is prepared by electroforming (lithographie galvanoformung abformung, LIGA) process.

The forming of at least one correction electrode penetrating at least a portion of the wiring layer may include:

Etching the wiring layer and the semiconductor substrate to form a second through hole that penetrates a portion of the film layer of the wiring layer and penetrates the semiconductor substrate;

forming a seed layer on a side of the semiconductor substrate facing away from the wiring layer;

forming a corrective electrode in the second through hole by using an electroplating process;

The seed layer is removed after forming the rectifying electrode.

Preparation method 2: Prepare the correction electrode using the through silicon via process.

The forming of at least one correction electrode penetrating at least a portion of the wiring layer may include:

Etching the wiring layer and the semiconductor substrate to form a second through hole that penetrates a portion of the film layer of the wiring layer and penetrates the semiconductor substrate;

Disposing a temporary substrate on a side of the semiconductor substrate away from the wiring layer;

Filling the second through hole with a conductive material to form a correction electrode;

The temporary substrate is removed after forming the corrective electrode.

In the second preparation method, the preparation method is described by taking the correction electrode penetrating the semiconductor substrate as an example. When a part of the correction electrode is located in the wiring layer and the other part penetrates a part of the semiconductor substrate, the second through hole formed in the above step may also only penetrate a part of the semiconductor substrate. When the correction electrode is only located in the wiring layer, the second through hole formed in the above step may also only penetrate the dielectric layer in the wiring layer. The above steps can be adjusted according to actual conditions and are not limited here.

Of course, in addition to the above-mentioned preparation method 1 and preparation method 2, other methods can also be used to prepare the correction electrode during specific implementation, which is not limited here.

In a specific implementation, after forming the second through hole and before forming the corrective electrode, the method may further include: forming an insulating layer and a barrier layer on the inner wall of the second through hole. During the preparation process, the insulating layer may be deposited first in the second through hole, and then the barrier layer may be deposited. The insulating layer may insulate the corrective electrode from the semiconductor substrate. When the second through hole penetrates the semiconductor substrate, there may be no insulating layer at the bottom of the second through hole. When the second through hole only penetrates a portion of the semiconductor substrate, an insulating layer may also be provided at the bottom of the second through hole to prevent the corrective electrode from contacting the semiconductor substrate at the bottom of the second through hole. In addition, in order to facilitate the formation of the insulating layer, the insulating layer may cover the entire side wall of the second through hole, that is, an insulating layer is also provided inside the second through hole at the location of the dielectric layer. The barrier layer may prevent the diffusion of metal ions in the corrective electrode. The end of the corrective electrode facing away from the semiconductor substrate is electrically connected to the wiring layer. Therefore, the barrier layer is deposited on the side wall and the bottom of the second through hole, so that the side of the corrective electrode formed subsequently and the end facing away from the wiring layer are provided with a barrier layer.

Optionally, in the embodiment of the present application, after forming at least one correction electrode penetrating at least a portion of the wiring layer and before forming a first through hole penetrating the semiconductor substrate and the wiring layer, the method may further include:

A carrier is arranged on a side of the semiconductor substrate facing away from the wiring layer;

Forming a second type of connection line on a side of the first type of connection line away from the semiconductor substrate, and connecting the second type of connection line to the first type of connection line and the correction electrode;

forming a shielding layer on a side of the second type connecting wire facing away from the semiconductor substrate;

forming a passivation layer on a side of the shielding layer facing away from the semiconductor substrate;

After forming the first through hole penetrating the semiconductor substrate and the wiring layer, the carrier sheet is removed.

In a third aspect, the present application further provides a scanning electron microscope, which may include: an electron beam source, and any of the above electron beam correctors. The electron beam corrector in the embodiment of the present application has a better correction effect on the electron beam, so the imaging quality of the scanning electron microscope is better.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of an electron beam straightener in the related art;

FIG2 is a schematic diagram of a planar structure of an electron beam straightener provided in an embodiment of the present application;

FIG3 is another schematic diagram of the planar structure of the electron beam straightener provided in an embodiment of the present application;

FIG4a is a schematic cross-sectional view of the dashed line L in FIG3 ;

FIG4b is another schematic cross-sectional view of the dashed line L in FIG3 ;

FIG5a is another schematic cross-sectional view of the dashed line L in FIG3 ;

FIG5 b is another schematic cross-sectional view of the dashed line L in FIG3 ;

FIG6 is another schematic cross-sectional view of the dashed line L in FIG3 ;

7a to 7d are schematic diagrams of the planar structure of an electron beam straightener provided in an embodiment of the present application;

FIG8 is a flow chart of a method for preparing an electron beam straightener provided in an embodiment of the present application;

9a to 9e are schematic structural diagrams corresponding to the steps of the preparation method in the embodiment of the present application.

Reference numerals:

200-microcorrector; 21-semiconductor substrate; 211-semiconductor device; 22-wiring layer; 221-first type of connecting wire; 222-second type of connecting wire; 223-dielectric layer; 224-shielding layer; 225-passivation layer; 23-correction electrode; 24-insulating layer; 25-barrier layer; 26-seed layer; 27-temporary substrate; 28-carrier; U-first through hole; H-second through hole; V-connection hole.

DETAILED DESCRIPTION

Scanning electron microscopes can be divided into single electron beam microscopes and multi-electron beam microscopes. Single electron beam microscopes shoot a single electron beam at the sample surface, while multi-electron beam microscopes can converge on the sample surface through the synergistic effect of multiple electron beams. Therefore, multi-electron beam microscopes have higher production capacity. However, under normal circumstances, the electron beam emitted by the electron beam source cannot be accurately incident on the electron beam mirror group, resulting in low electron beam imaging quality, especially for multi-electron beam microscopes, this problem will be more significant. Therefore, it is necessary to set an electron beam corrector to correct the angle, position, astigmatism and other parameters of the electron beam, so as to improve the quality of electron beam imaging.

FIG1 is a schematic diagram of the structure of an electron beam corrector in the related art. As shown in FIG1 , the electron beam corrector in the related art may include: a silicon substrate 11, a logic circuit 12, and an electrode structure 13. The electron beam corrector is provided with an opening T. During the operation of the scanning electron microscope, the electron beam emitted by the electron beam source passes through the opening T and is emitted to the electron beam mirror assembly. The logic circuit 12 may apply a voltage to the electrode structure 13 to form an electric field at the opening T, thereby controlling the deflection of the electron beam and realizing the correction of parameters such as the angle, position, and astigmatism of the electron beam.

The logic circuit 12 may include: a transistor 121, a first type metal layer 122 and a second type metal layer 123. The transistor 121 is located on the surface of the silicon substrate 11. The transistor 121 is electrically connected to the electrode structure 13 through the connection lines in the first type metal layer 122 and the connection lines in the second type metal layer 123. Since there are a large number of transistors 121 in the logic circuit 12, it is necessary to set multiple layers of the first type metal layer 122 to lead out the signal of the transistor 121 due to the limitation of the wiring space. The electrode structure 13 is formed by stacking multiple metal layers, and the metal layers in the electrode structure 13 are respectively arranged in the same layer as each first type metal layer 122. A dielectric layer 14 is provided between the silicon substrate 11 and the first type metal layer 122, between two adjacent first type metal layers 122, between the first type metal layer 122 and the second type metal layer 123, and between the second type metal layer 123 and other film layers, and the opening T runs through the dielectric layer 14 and the silicon substrate 11.

During the preparation process, the transistor 121 can be prepared by the front end of line (FEOL) process in semiconductor technology, and then the first type metal layer 122, the second type metal layer 123 and the electrode structure 13 and other structures can be prepared by the back end of line (BEOL) process, wherein the metal layer in the electrode structure 13 needs to be prepared by the same patterning process as the corresponding first type metal layer 122. Then, the dielectric layer 14 between the electrode structures 13 is etched by the micro electro mechanical system (MEMS) process, and a deep silicon etching process is used to form a silicon deep hole, thereby forming an opening T.

However, in order to make the electric field formed by the electrode structure 13 more uniform and facilitate the control of the electron beam deflection, the symmetry of the electrode structure 13 is very high. In addition, since the electrode structure 13 is composed of multiple metal layers, during the preparation process, better process consistency and stability are required to prepare an electrode structure 13 with better symmetry. In addition, it is necessary to use an overlay process to prepare the electrode structure 13. In order to ensure the accuracy of the same electrode structure 13, the overlay accuracy of the preparation process is required to be high. Therefore, the preparation process of the electron beam straightener in the related art is more difficult.

Based on this, the embodiments of the present application provide an electron beam corrector, a preparation method thereof, and a scanning electron microscope to reduce the difficulty of the preparation process of the electron beam corrector.

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. It should be noted that in this specification, similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

The scanning electron microscope provided in the embodiment of the present application can be used for imaging and surface analysis of samples. For example, the morphology of the material surface, the atomic number of the object, the surface composition, etc. can be analyzed. The scanning electron microscope can be applied to the field of semiconductor technology and can be used for wafer surface dimension measurement, surface defect analysis, electron beam lithography, etc. The electron beam corrector provided in the embodiment of the present application can be applied to a single electron beam microscope or a multi-electron beam microscope. The electron beam corrector can correct the electron beam emitted by the electron beam source to improve the quality of electron beam imaging.

FIG2 is a schematic diagram of the planar structure of the electron beam corrector provided in an embodiment of the present application, and FIG3 is another schematic diagram of the planar structure of the electron beam corrector provided in an embodiment of the present application. As shown in FIG2 and FIG3, the electron beam corrector may include: at least one micro-corrector 200, each micro-corrector 200 can correct a beam of electron beams, that is, the number of micro-correctors 200 in the electron beam corrector is equal to the number of electron beams. As shown in FIG2, when the electron beam corrector provided in an embodiment of the present application is applied to a multi-electron beam microscope, the electron beam corrector includes a plurality of micro-correctors 200, and FIG2 is used as an example to illustrate that the electron beam corrector includes nine micro-correctors 200, and FIG2 is used as an example to illustrate that each micro-corrector 200 is arranged in an array. In the specific implementation, the number and arrangement of the micro-correctors 200 can be set according to actual needs, which is not limited here. As shown in FIG3, when the electron beam corrector provided in an embodiment of the present application is applied to a single electron beam microscope, the electron beam corrector includes a micro-corrector 200.

FIG4a is a cross-sectional schematic diagram at the dotted line L in FIG3 . As shown in FIG4a , the electron beam corrector in the embodiment of the present application may include: a semiconductor substrate 21, a wiring layer 22 located on the semiconductor substrate 21, and at least one correction electrode 23 electrically connected to the wiring layer 22. The electron beam corrector is provided with at least one first through hole U penetrating the semiconductor substrate 21 and the wiring layer 22, and at least one correction electrode 23 is provided on the inner wall of each first through hole U. At least part of each correction electrode 23 is located in the wiring layer 22, and the correction electrode 22 is an integrated structure. Different from the electrode structure obtained by stacking multiple layers of metal in the related art, the correction electrode in the embodiment of the present application is an integrated structure, that is, the correction electrode is a component obtained by an integrated molding process.

In the embodiment of the present application, the correction electrode 23 is set as an integrated structure, and in the preparation process, it is easier to form a correction electrode 23 with good symmetry, so that the uniformity of the electric field formed by each correction electrode 23 in the micro-corrector 200 is good, and no overlay process is required to prepare the correction electrode 23, thereby reducing the process difficulty of preparing the correction electrode 23. In addition, in the preparation process of the electron beam corrector, the preparation process of the correction electrode 23 can be separated from the preparation process of each film layer in the wiring layer 22, and the preparation process of the wiring layer 22 and the preparation process of the correction electrode 23 will not affect each other.

In the embodiment of the present application, a first through hole U penetrating the semiconductor substrate 21 and the wiring layer 22 is provided in the electron beam corrector, and a correction electrode 23 is provided on the inner wall of the first through hole U. In this way, during the operation of the scanning electron microscope, the electron beam emitted by the electron beam source passes through the first through hole U and is directed to the electron beam mirror group, and then to the sample surface. By detecting the secondary electrons generated by the electron beam bombarding the sample surface, the surface image of the sample can be obtained. A voltage can be applied to the correction electrode 23 through the connecting wire in the wiring layer 22 to form an electric field at the first through hole U, so as to correct the parameters such as the inclination angle and position of the electron beam passing through the first through hole U. For example, the image of the electron beam can be corrected from the ellipse caused by dispersion to a circle. Since the uniformity of the electric field formed by each correction electrode 23 in the embodiment of the present application is good, it is easier to control the deflection of the electron beam. In addition, when the electron beam corrector is used in a multi-electron beam microscope, each electron beam can be corrected by each micro-corrector 200 to pass through the corresponding first through hole U in parallel, so that the synergy of each electron beam is better, achieving the purpose of simultaneous operation of multiple electron beams and improving the imaging quality of the electron microscope.

As shown in FIG. 4a , in one implementation of the present application, the correction electrode 23 may be located only in the wiring layer 22. In this way, during the preparation process, only the wiring layer 22 may be etched to form a second through hole, and a conductive material may be filled in the second through hole to obtain the correction electrode 23. The preparation process of the correction electrode 23 is relatively simple and the preparation cost is relatively low.

Referring to FIG1 , in the related art, the electrode structure 13 is composed of multiple metal layers. During the preparation process, the metal layer in the electrode structure 13 needs to be prepared by the same patterning process as the first type metal layer 122. Due to the limitation of the preparation process, the thickness of the metal layer in the electrode structure 13 is limited, thereby limiting the total height of the electrode structure 13 and limiting the length of the path of the corrected electron beam. In the embodiment of the present application, by setting the correction electrode as an integrated structure, during the preparation process of the electron beam corrector, the preparation process of the correction electrode can be separated from the preparation process of each film layer in the wiring layer, and the preparation process of the correction electrode is not limited by the preparation process of the wiring layer. Therefore, in another implementation of the present application, FIG5a is another cross-sectional schematic diagram at the dotted line L in FIG3 . As shown in FIG5a , a part of the correction electrode 23 can be located in the wiring layer 22, and another part can be located in the semiconductor substrate 21. Thereby, the total height of the correction electrode 23 is increased, the length of the path of the corrected electron beam is longer, and the correction effect of the electron beam is better. During the preparation process, the wiring layer 22 and the semiconductor substrate 21 may be etched to obtain a second through hole, and a conductive material may be filled in the second through hole to form the correction electrode 23 .

FIG6 is another cross-sectional schematic diagram at the dotted line L in FIG3 . As shown in FIG6 , the correction electrode 23 can penetrate the semiconductor substrate 21 , that is, a portion of the correction electrode 23 is located in the wiring layer 22 , and the other portion extends to the bottom surface of the semiconductor substrate 21 . In this way, the total height of the correction electrode 23 can be further increased, thereby increasing the length of the path of the correction electron beam.

In summary, the total height of the correction electrode can be set according to actual needs. When the total height required for the correction electrode is small, the correction electrode can be located only in the wiring layer. When the height required for the correction electrode is large, part of the correction electrode can be located in the wiring layer, and the other part can penetrate the semiconductor substrate. In addition, the depth of the correction electrode penetrating the semiconductor substrate can be set according to the height requirement. Therefore, different correction voltage requirements can be met by adjusting the total height of the correction electrode.

Optionally, as shown in FIG. 4 a , the semiconductor substrate 21 may include semiconductor materials such as silicon. The semiconductor substrate 21 has certain conductive properties. In order to insulate the correction electrode 23 from the semiconductor substrate 21 , an insulating layer 24 may be provided between the correction electrode 23 and the semiconductor substrate 21 .

Continuing with reference to FIG. 4a , the correction electrode 23 may include a metal material, such as metal copper, gold, nickel, tungsten, etc. The correction electrode 23 is electrically connected to the wiring layer 22 at the end facing away from the semiconductor substrate 21. In order to prevent the diffusion of metal ions in the correction electrode 23, a blocking layer 25 may be provided on the side of the correction electrode 23 and the end facing away from the wiring layer 22.

In a specific implementation, in order to prevent the wiring layer and the semiconductor substrate from affecting the electric field formed by the correction electrode, a portion of at least one correction electrode may be embedded in the inner wall of the first through hole. As shown in FIG4a, when the correction electrode 23 is only located in the wiring layer 22, the side of the correction electrode 23 facing the first through hole U is not wrapped by the wiring layer 22, thereby preventing the wiring layer 22 from affecting the electric field formed by the correction electrode 23 at the first through hole U. As shown in FIG5a, when a portion of the correction electrode 23 is located in the wiring layer 22 and the other portion is located in the semiconductor substrate 21, the side of the correction electrode 23 facing the first through hole U is not wrapped by the wiring layer 22 and the semiconductor substrate 21, thereby preventing the wiring layer 22 and the semiconductor substrate 21 from affecting the electric field formed by the correction electrode 23 at the first through hole U.

FIG4b is another cross-sectional schematic diagram at the dotted line L in FIG3 , and FIG5b is another cross-sectional schematic diagram at the dotted line L in FIG3 . As shown in FIG4b , in another implementation of the present application, when the correction electrode 23 is only located in the wiring layer 22, the side of the correction electrode 23 facing the first through hole U may be covered by the wiring layer 22. In the preparation process, after forming the correction electrode 23 and each film layer in the wiring layer 22, the wiring layer 22 and the semiconductor substrate 21 need to be etched to obtain the first through hole U penetrating the semiconductor substrate 21 and the wiring layer 22. The side of the correction electrode 23 facing the first through hole U is set to be covered by the wiring layer 23. In the process of forming the first through hole U, the process accuracy of etching the wiring layer 22 and the semiconductor substrate 21 can be reduced, that is, the process difficulty is reduced. Similarly, as shown in FIG5b, when a portion of the correction electrode 23 is located in the wiring layer 22 and the other portion is located in the semiconductor substrate 21, the side surface of the correction electrode 23 facing the first through hole U is covered by the wiring layer 22 and the semiconductor substrate 21. In this way, the process accuracy of etching the wiring layer 22 and the semiconductor substrate 21 can also be reduced, that is, the process difficulty can be reduced.

As shown in FIG. 4 a and FIG. 5 a , the correction electrode 23 is a strip-shaped structure that is consistent with the extension direction of the first through hole U. In this way, the path of the correction electron beam formed by the correction electrode 23 can be made longer, so that the correction effect of the electron beam is better.

As shown in FIG3 , in order to make the electric field formed by each correction electrode 23 in the micro-corrector 200 more uniform, at least two correction electrodes 23 evenly distributed can be set on the inner wall of each first through hole U. An even number of correction electrodes 23 can be set on the inner wall of each first through hole U. FIG3 takes eight correction electrodes 23 set on the inner wall of each first through hole U as an example for schematic diagram. In specific implementation, the number of correction electrodes 23 can be set according to actual conditions, and is not limited here.

As shown in FIG. 4a, in the embodiment of the present application, the semiconductor substrate 21 is provided with a semiconductor device 211 on a side close to the wiring layer 22. For example, the semiconductor device 211 may be a transistor. Of course, the semiconductor device 211 may also be other devices, which is not limited here. The above wiring layer 22 may include: a first type of connection line 221 located on the semiconductor substrate 21, and a second type of connection line 222 located on the side of the first type of connection line 221 away from the semiconductor substrate 21. The first type of connection line 221 connects the semiconductor device 211 and the second type of connection line 222, the second type of connection line 222 is located on the side of the correction electrode 23 away from the semiconductor substrate 21, and the second type of connection line 222 is electrically connected to the end of the correction electrode 23 away from the semiconductor substrate 21. In this way, the semiconductor device 211 is electrically connected to the correction electrode 23 through the first type of connection line 221 and the second type of connection line 222, so that the voltage applied to the correction electrode 23 can be controlled by the semiconductor device 211.

Optionally, a dielectric layer 223 is provided between the first type of connection line 221 and the semiconductor substrate 21, and between the second type of connection line 222 and the first type of connection line 221, respectively. The first type of connection line 221 is electrically connected to the semiconductor substrate 21 through a connection hole V in the dielectric layer 223, and the second type of connection line 222 is electrically connected to the first type of connection line 221 through a connection hole V in the dielectric layer 223. In practical applications, the first type of connection line 221 and the second type of connection line 222 are made of metal materials. Due to the limitation of the preparation process, the thickness of the first type of connection line 221 and the second type of connection line 222 is limited. Therefore, in order to electrically connect the semiconductor device 211 and the second type of connection line 222, multiple layers of the first type of connection line 221 can be provided, and a dielectric layer 223 is provided between two adjacent layers of the first type of connection line 221, and the two adjacent layers of the first type of connection line 221 are electrically connected through the connection hole V in the dielectric layer 223.

Continuing to refer to FIG. 4a, in the electron beam straightener provided in the embodiment of the present application, the wiring layer may further include: a shielding layer 224 located on the side of the second type connecting wire 222 away from the semiconductor substrate 21, and a dielectric layer 223 is provided between the shielding layer 224 and the second type connecting wire 222. By providing the shielding layer 224, it is possible to prevent external factors from affecting components such as the correction electrode 23, the first type connecting wire 221, and the second type connecting wire 222, thereby ensuring that the electric field formed by the correction electrode 23 has good uniformity.

In addition, the wiring layer 22 may further include a passivation layer 225 located on the side of the shielding layer 224 away from the semiconductor substrate 21, and a dielectric layer 223 is provided between the passivation layer 225 and the shielding layer 224. The components inside the wiring layer 22 can be protected by providing the passivation layer 225.

As shown in FIG3 , in an embodiment of the present application, the shape of the cross section of the correction electrode 23 in the first direction can be an ellipse, and the first direction is a direction parallel to the surface of the semiconductor substrate, that is, the first direction is a direction parallel to the plane shown in FIG3 . FIG7a to FIG7d are schematic diagrams of the planar structure of the electron beam corrector provided in an embodiment of the present application. In addition to the ellipse shown in FIG3 , the shape of the cross section of the correction electrode 23 can also be a circle (as shown in FIG7a ), a rectangle (as shown in FIG7b ), a trapezoid (as shown in FIG7c ) or a fan ring (as shown in FIG7d ). Of course, the shape of the cross section of the correction electrode 23 can also be other shapes, which are not limited here. In the specific implementation, the cross-sectional area, cross-sectional shape, and total height of the correction electrode can be set according to actual needs, and the design flexibility of the correction electrode is relatively high.

Based on the same technical concept, the embodiment of the present application also provides a method for preparing any of the above-mentioned electron beam straighteners. FIG. 8 is a flow chart of the method for preparing the electron beam straightener provided in the embodiment of the present application. As shown in FIG. 8 , the method for preparing the above-mentioned electron beam straightener provided in the embodiment of the present application may include:

S301, forming a partial film layer of a wiring layer on a semiconductor substrate;

S302, forming at least one correction electrode penetrating at least a portion of the wiring layer; each correction electrode is electrically connected to the wiring layer, and the correction electrodes are an integrated structure;

S303, after forming each film layer of the wiring layer, forming a first through hole penetrating the semiconductor substrate and the wiring layer; at least one correction electrode is provided on the inner wall of each first through hole.

In the embodiment of the present application, the correction electrode is an integrated structure, and during the preparation process, it is easier to form a correction electrode with good symmetry, so that the uniformity of the electric field formed by each correction electrode in the micro-corrector is better, and no overlay process is required to prepare the correction electrode, thereby reducing the process difficulty of preparing the correction electrode. In addition, the preparation process of the correction electrode is separated from the preparation process of each film layer in the wiring layer, and the preparation process of the wiring layer and the preparation process of the correction electrode will not affect each other.

9a to 9e are schematic structural diagrams corresponding to the steps of the preparation method in the embodiment of the present application. The above preparation method provided in the embodiment of the present application is described in detail below in conjunction with the accompanying drawings.

In specific implementation, before the above step S301, the following steps may also be included:

9 a , a semiconductor device 211 is formed on the surface of a semiconductor substrate 21 . Taking the semiconductor device 211 as a transistor as an example, a doping process may be used to form a channel region, a source region, a drain region, etc. of the transistor on the surface of the semiconductor substrate 21 .

The above step S301 may include:

Continuing to refer to FIG. 9a, a first-class connection line 221 is formed on a side of the semiconductor substrate 21 having the semiconductor device 211, and the first-class connection line 221 is electrically connected to the semiconductor device 211. In order to enable the semiconductor device 21 to be electrically connected to the second-class connection line 222 formed subsequently, the wiring layer 22 may include multiple layers of the first-class connection line 221. During the preparation process, a dielectric layer 223 may be formed on the surface of the semiconductor substrate 21, and the dielectric layer 223 may be etched to obtain a connection hole V. Then, the first-class connection line 221 is formed on the surface of the dielectric layer 223, so that the first-class connection line 221 is electrically connected to the semiconductor device 211 through the connection hole V. Afterwards, the dielectric layer 223 and the first-class connection line 221 are prepared layer by layer in a similar manner to form multiple layers of the first-class connection line 221 arranged in a stacked manner. Optionally, the first-class connection line 221 may be prepared using metal copper. Of course, the first-class connection line 221 may also be prepared using other conductive materials, which are not limited here.

After the above step S301 and before the above step S302, the method may further include: thinning the semiconductor substrate to a target thickness, so that the thickness of the final micro-corrector is thin and meets the thickness requirement. Optionally, a grinding device may be used to grind the surface of the semiconductor substrate away from the wiring layer. Of course, other methods may also be used to thin the semiconductor substrate, which is not limited here.

In the embodiment of the present application, in the above step S302, the correction electrode can be prepared in a variety of ways. The following describes in detail two preparation methods of the correction electrode in conjunction with the accompanying drawings.

Preparation method 1: using electroforming (lithographie galvanoformung abformung, LIGA) process to prepare the correction electrode. Preparation method 1 can be used to prepare the electron beam corrector shown in FIG6 , in which a portion of the correction electrode 23 is located in the wiring layer 22 , and another portion extends to the bottom surface of the semiconductor substrate 21 .

9b, the wiring layer 22 and the semiconductor substrate 21 are etched to form a second through hole H that penetrates a portion of the film layer of the wiring layer 22 and penetrates the semiconductor substrate 21. The dielectric layer 223 in the wiring layer 22 may be etched by an etching process, and a deep silicon etching process may be used to form a silicon deep hole in the semiconductor substrate 21, and finally the second through hole H is formed.

9 c , a seed layer 26 is formed on a side of the semiconductor substrate 21 away from the wiring layer 22 . The material of the seed layer 26 may be the same as that of the correction electrode. For example, the material of the seed layer 26 may be metallic copper.

9d, a correction electrode 23 is formed in the second through hole H by an electroplating process, and then the surface of the correction electrode 23 facing away from the semiconductor substrate 21 is polished;

After forming the rectifying electrode 23, the seed layer is removed to obtain the structure shown in FIG. 9d.

Preparation method 2: Prepare the correction electrode using the through silicon via process.

9b, the wiring layer 22 and the semiconductor substrate 21 are etched to form a second through hole H that penetrates a portion of the film layer of the wiring layer 22 and penetrates the semiconductor substrate 21. The dielectric layer 223 in the wiring layer 22 may be etched by an etching process, and a deep silicon etching process may be used to form a silicon deep hole in the semiconductor substrate 21, and finally the second through hole H is formed.

9c, a temporary substrate 27 is disposed on a side of the semiconductor substrate 21 away from the wiring layer 22. By providing the temporary substrate 27, the conductive material subsequently filled in the second through hole H can be prevented from leaking out.

A conductive material is filled in the second through hole H to form a correction electrode. For example, the conductive material may be metal copper. Of course, the conductive material may also be other materials, which are not limited here.

After forming the corrective electrode 23, the temporary substrate is removed to obtain the structure shown in FIG. 9d.

In the second preparation method, the preparation method is described by taking a structure in which a part of the correction electrode is located in the wiring layer and the other part extends to the bottom surface of the semiconductor substrate as an example. When a part of the correction electrode is located in the wiring layer and the other part penetrates a part of the semiconductor substrate, the second through hole H formed in the above step may also only penetrate a part of the semiconductor substrate. When the correction electrode is only located in the wiring layer, the second through hole H formed in the above step may also only penetrate the dielectric layer in the wiring layer. The above steps can be adjusted according to actual conditions and are not limited here.

Of course, in addition to the above-mentioned preparation method 1 and preparation method 2, other methods can also be used to prepare the correction electrode during specific implementation, which is not limited here.

In a specific implementation, in the above step S302, after forming the second through hole and before forming the corrective electrode, the following may be further included: referring to FIG. 9c, forming an insulating layer 24 and a barrier layer 25 on the inner wall of the second through hole H. In the preparation process, the insulating layer 24 may be first deposited in the second through hole H, and then the barrier layer 25 may be deposited. The insulating layer 24 may insulate the corrective electrode from the semiconductor substrate 21. When the second through hole H penetrates the semiconductor substrate 21, there may be no insulating layer 24 at the bottom of the second through hole H. When the second through hole H only penetrates a portion of the semiconductor substrate 21, an insulating layer 24 may also be provided at the bottom of the second through hole H to prevent the corrective electrode from contacting the semiconductor substrate 21 at the bottom of the second through hole H. In addition, in order to facilitate the formation of the insulating layer 24, the insulating layer 24 may cover the entire side wall of the second through hole H, that is, the insulating layer 24 is also provided inside the second through hole H where the dielectric layer 223 is located. The barrier layer 25 can prevent the diffusion of metal ions in the corrective electrode. The end of the corrective electrode away from the semiconductor substrate 21 is electrically connected to the wiring layer 22. Therefore, the barrier layer 25 is deposited on the sidewall and bottom of the second through hole H, so that the side surface and the end of the corrective electrode away from the wiring layer formed subsequently are provided with the barrier layer 25.

Referring to FIG. 9e , after the above step S302 and before the above step S303, the following may also be included:

A carrier sheet 28 is disposed on a side of the semiconductor substrate 21 facing away from the wiring layer 22 , and the carrier sheet 28 can play a supporting role.

A second type of connecting wire 222 is formed on the side of the first type of connecting wire 221 away from the semiconductor substrate 21, and the second type of connecting wire 222 connects the first type of connecting wire 221 and the correction electrode 23. Optionally, the second type of connecting wire 222 can be prepared by metal materials, for example, metal copper, gold, nickel, tungsten, etc. Of course, other conductive materials can also be used to prepare the second type of connecting wire 222, which is not limited here.

A shielding layer 224 is formed on the side of the second type connecting line 222 away from the semiconductor substrate 21. For example, the shielding layer 224 may be made of metal material. Of course, the shielding layer 224 may also be made of other materials with shielding function, which is not limited here.

A passivation layer 225 is formed on a side of the shielding layer 224 facing away from the semiconductor substrate 21;

In the above step S303, referring to FIG6 , the dielectric layer 223 in the wiring layer 22 may be etched by an etching process, and a deep silicon hole may be formed in the semiconductor substrate 21 by a deep silicon etching process, so as to form a first through hole U penetrating the semiconductor substrate 21 and the wiring layer 22. Since the insulating layer 24 is used to insulate the semiconductor substrate 21 from the correction electrode 23, in the process of forming the first through hole U, the insulating layer 24 on the side of the correction electrode 23 facing the first through hole U may be etched away.

After the above step S303, the carrier is removed to obtain the structure shown in FIG. 6 .

Based on the same technical concept, the embodiment of the present application also provides a scanning electron microscope, which may include: an electron beam source, and any of the above electron beam straighteners. The electron beam straightener in the embodiment of the present application has a good correction effect on the electron beam, so the imaging quality of the scanning electron microscope is good.

Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (22)

1. An electron beam corrector, comprising: a semiconductor substrate, a wiring layer over the semiconductor substrate, and at least one rectifying electrode electrically connected to the wiring layer;

   The electron beam corrector is provided with at least one first through hole penetrating through the semiconductor substrate and the wiring layer, and the inner wall of each first through hole is provided with at least one correction electrode;

   At least part of each correction electrode is positioned in the wiring layer, and the correction electrodes are of an integral structure.
2. The electron beam corrector of claim 1, wherein the correction electrodes are located only within the routing layer.
3. The electron beam corrector of claim 1, wherein a side of the correction electrode facing the first through hole side is covered by the wiring layer.
4. The electron beam corrector of claim 1, wherein a portion of the correction electrodes are located within the wiring layer and another portion is located within the semiconductor substrate.
5. The electron beam corrector of claim 4, wherein the correction electrode extends through the semiconductor substrate.
6. The electron beam corrector of claim 4, wherein a side of the correction electrode facing the first through hole side is covered by the wiring layer and the semiconductor substrate.
7. The electron beam corrector of claim 4, wherein an insulating layer is provided between the correction electrode and the semiconductor substrate.
8. The electron beam corrector of claim 1, wherein the correction electrode is electrically connected to the wiring layer at an end of the side facing away from the semiconductor substrate; and a blocking layer is arranged on the side surface of the correction electrode and the end part of one side, which is away from the wiring layer.
9. The electron beam corrector of claim 1, wherein a portion of at least one of the correction electrodes is embedded in an inner wall of the first through hole.
10. The electron beam corrector according to any one of claims 1 to 9, wherein the correction electrode has a stripe-like structure in conformity with an extending direction of the first through hole.
11. The electron beam corrector according to any one of claims 1-10, wherein the inner wall of each of the first through holes is provided with at least two of the correction electrodes uniformly distributed.
12. The electron beam corrector according to any one of claims 1 to 11, wherein the semiconductor substrate is provided with a semiconductor device at a side close to the wiring layer;

    The wiring layer includes: a first type of connection line located above the semiconductor substrate, and a second type of connection line located on a side of the first type of connection line facing away from the semiconductor substrate; dielectric layers are respectively arranged between the first type connecting lines and the semiconductor substrate and between the second type connecting lines and the first type connecting lines;

    the first type connecting wire is connected with the semiconductor device tube and the second type connecting wire; the second type connecting wire is positioned at one side of the correction electrode, which is away from the semiconductor substrate, and is electrically connected with the end part of one side of the correction electrode, which is away from the semiconductor substrate.
13. The electron beam corrector of claim 12, wherein the routing layer further comprises: and a shielding layer positioned on one side of the second type connecting wire away from the semiconductor substrate, wherein a dielectric layer is arranged between the shielding layer and the second type connecting wire.
14. The electron beam corrector of claim 13, wherein the routing layer further comprises: and a passivation layer positioned on one side of the shielding layer away from the semiconductor substrate, wherein a dielectric layer is arranged between the passivation layer and the shielding layer.
15. The electron beam corrector according to any one of claims 1-14, wherein the shape of the cross section of the correction electrode in the first direction is elliptical, circular, rectangular, trapezoidal or fan-shaped;

    The first direction is a direction parallel to the semiconductor substrate surface.
16. A method of making an electron beam corrector, comprising:

    Forming a partial film layer of a wiring layer over a semiconductor substrate;

    Forming at least one correction electrode penetrating at least a portion of the wiring layer; each correction electrode is electrically connected with the wiring layer, and the correction electrodes are of an integrated structure;

    forming a first through hole penetrating the semiconductor substrate and the wiring layer after forming each film layer of the wiring layer; at least one correcting electrode is arranged on the inner wall of each first through hole.
17. The method of manufacturing of claim 16, wherein forming at least one corrective electrode at least through a portion of the wiring layer comprises:

    Etching the wiring layer and the semiconductor substrate to form a second through hole penetrating through part of the film layer of the wiring layer and penetrating through the semiconductor substrate;

    forming a seed layer on one side of the semiconductor substrate away from the wiring layer;

    Forming the correction electrode in the second through hole by adopting an electroplating process;

    The seed layer is removed after the correction electrode is formed.
18. The method of manufacturing of claim 16, wherein forming at least one corrective electrode at least through a portion of the wiring layer comprises:

    Etching the wiring layer and the semiconductor substrate to form a second through hole penetrating through part of the film layer of the wiring layer and penetrating through the semiconductor substrate;

    a temporary substrate is arranged on one side of the semiconductor substrate, which is away from the wiring layer;

    filling conductive materials in the second through holes to form the correction electrodes;

    the temporary substrate is removed after the correction electrode is formed.
19. The method of manufacturing of claim 17 or 18, further comprising, after forming the second via, before forming the corrective electrode:

    And forming an insulating layer and a barrier layer on the inner wall of the second through hole.
20. The method according to any one of claims 16 to 19, further comprising, before forming a part of the film layer of the wiring layer over the semiconductor substrate:

    forming a semiconductor device on the surface of the semiconductor substrate;

    The partial film layer for forming the wiring layer on the semiconductor substrate comprises the following steps:

    a first type of connection line is formed on a side of the semiconductor substrate having the semiconductor device, and the first type of connection line is electrically connected with the semiconductor device.
21. The method of manufacturing of claim 20, further comprising, after forming at least one corrective electrode extending through at least a portion of the wiring layer, before forming a first via extending through the semiconductor substrate and the wiring layer:

    A carrier is arranged on one side of the semiconductor substrate, which is away from the wiring layer;

    Forming a second type of connecting wire on one side of the first type of connecting wire, which is far away from the semiconductor substrate, and enabling the second type of connecting wire to connect the first type of connecting wire and the correction electrode;

    forming a shielding layer on one side of the second type connecting wire away from the semiconductor substrate;

    Forming a passivation layer on one side of the shielding layer away from the semiconductor substrate;

    after forming a first via hole penetrating the semiconductor substrate and the wiring layer, the carrier is removed.
22. A scanning electron microscope, comprising: an electron beam source, and an electron beam corrector as claimed in any one of claims 1 to 15.