CN118971846A - A phase interpolator encoding method and phase interpolator - Google Patents
A phase interpolator encoding method and phase interpolator Download PDFInfo
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Abstract
本申请公开一种相位插值器的编码方法和相位插值器，旨在解决现有相位插值结构的输出相位的非线性大的问题。通过数字信号选择两路通道，按照不同权重进行相位求和得到输出相位信号，所述相位插值器包括依次相连的相位输入信号模块、权重选择模块和输出相位信号模块，所述权重选择模块包括P通道多个加权通道单元、N通道多个加权通道单元、以及解码电路；还包括：通道交换模块，设置在相位输入信号模块与权重选择模块之间；所述解码电路在码值Code到达其整个变化区间的中间值时，交换接通的P通道和N通道，改善输出相位的非线性。
The present application discloses an encoding method and a phase interpolator of a phase interpolator, aiming to solve the problem of large nonlinearity of the output phase of the existing phase interpolation structure. Two channels are selected by digital signals, and the phases are summed according to different weights to obtain an output phase signal. The phase interpolator includes a phase input signal module, a weight selection module and an output phase signal module connected in sequence, and the weight selection module includes a plurality of weighted channel units of the P channel, a plurality of weighted channel units of the N channel, and a decoding circuit; and also includes: a channel exchange module, which is arranged between the phase input signal module and the weight selection module; when the code value Code reaches the middle value of its entire variation range, the decoding circuit exchanges the connected P channel and N channel to improve the nonlinearity of the output phase.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a phase interpolator.
Background
The phase interpolator (english name Phase Interpolator) is a circuit widely used in phase locked loops, clock recovery circuits. The basic principle is that according to different digital signals, the input signals with different phases are divided into multiple pathsTwo paths of channels are selected through digital signals, and then phase summation is carried out according to different weights to obtain an output phase. The phase interpolation architecture is shown in fig. 1, as shown in equation (1),Is the weight corresponding to each signal channel.
（1）
Common phase interpolation structures are a current mode structure as shown in fig. 2 and a voltage mode structure as shown in fig. 3. In the current mode structure, if phase interpolation with higher accuracy is to be realized, as shown in fig. 2, a plurality of current source switches bank are required to be used, and the switching tube is controlled by a certain decoding circuit.
The linearity of the phase interpolator circuit affects jitter in a PLL and BER in CDR applications, and therefore it becomes particularly important to improve the nonlinearity of the output phase.
Disclosure of Invention
The application provides a coding method of a phase interpolator and the phase interpolator, and aims to solve the problem of large nonlinearity of an output phase of an existing phase interpolation structure.
In a first aspect, a method for encoding a phase interpolator, where the phase interpolator includes a phase input signal module, a weight selection module, and an output phase signal module that are sequentially connected, where the weight selection module includes a plurality of P-channel weighted channel units, a plurality of N-channel weighted channel units, and a decoding circuit; the phase interpolator also comprises a channel exchange module which is arranged between the phase input signal module and the weight selection module; the encoding method of the phase interpolator includes the following.
Receiving a first signal and a second signal from a phase input signal module by using a first input end and a second input end of the channel exchange module respectively; and the first signal and the second signal are respectively sent to the weight selection module by utilizing the first output end and the second output end of the channel exchange module.
The decoding circuit is utilized to switch on a plurality of weighting channel units corresponding to the P channel and a plurality of weighting channel units corresponding to the N channel according to different Code values, and the channel exchange module is controlled to switch between the P channel and the N channel; wherein, the total number of the weighting units which are correspondingly connected with the first signal and the second signal is kept unchanged, the number of the weighting units which are correspondingly connected with the first signal is monotonically decreased/increased along with the Code, and the number of the weighting units which are correspondingly connected with the second signal is monotonically increased/decreased along with the Code; when the Code value Code reaches the middle value of the whole change interval, the channel exchange module is used for exchanging the P channel and the N channel which are correspondingly connected with the first signal and the second signal.
According to a second aspect, a phase interpolator is configured to select two paths of channels according to different digital signals for multiple paths of input different phase signals, and perform phase summation according to different weights to obtain an output phase signal, where the phase interpolator includes a phase input signal module, a weight selection module, and an output phase signal module that are sequentially connected, where the weight selection module includes a plurality of weighted channel units of P channels, a plurality of weighted channel units of N channels, and a decoding circuit; it is characterized by also comprising: the channel exchange module is arranged between the phase input signal module and the weight selection module.
The first input end and the second input end of the channel switching module are respectively connected with the first output end and the second output end of the phase input signal module, and the first output end and the second output end of the channel switching module are respectively connected with the weight selection module.
The decoding circuit is used for determining a plurality of weighting channel units corresponding to the P channel and a plurality of weighting channel units corresponding to the N channel corresponding to the different Code value codes, and controlling the channel switching module to switch between the P channel and the N channel; wherein the total number of the weighting units connected with the first input end and the second input end is kept unchanged, the number of the weighting units connected with the first input end monotonically decreases/increases along with the Code, and the number of the weighting units connected with the second input end correspondingly monotonically increases/decreases along with the Code; when the Code value Code reaches the middle value of the whole change interval, the switched-on P channel and N channel are exchanged.
In the above solution, optionally, the method includes: setting the whole variation interval of the Code value Code asThenWhen the number of the weighted channel units of the P channel and the N channel is the largest; code=0The weighted channel units of the P channel and the N channel are exactly the same.
In the above solution, optionally, the method includes: setting the whole variation interval of the Code value Code as; The change interval of the Code isThe number of the weighting units of the P channel is monotonically decreased, and the number of the weighting units of the N channel is monotonically increased; the change interval of the Code isAnd the number of the weighting units of the P channel is monotonically increased, and the number of the weighting units of the N channel is monotonically decreased.
In the above solution, optionally, the method includes: the phase of the output phase signal is related to the number of weighting channel units connected with the first input end and the second input end, and the more the number of the weighting channel units connected with the first input end is, the fewer the number of the weighting channel units connected with the second input end is, and the phase of the output phase signal is closer to the phase of the signal passing through the first input end.
In the above solution, optionally, the method includes: when code=0, the first input terminal is connected with the P channelThe second input end of each weighting channel unit is connected with 1 weighting channel unit of N channels.
At the position ofThe number of the weighting units of the P channel connected with the first input end is sequentially reduced by 1, and the number of the weighting units of the N channel connected with the second input end is sequentially increased by 1.
When the first input end is connected with the P channelA weighted channel unit with N channel connected to the second inputAnd a weighted channel unit.
When the first input end is connected with N channelA weighted channel unit with a second input connected to the P channelAnd a weighted channel unit.
At the position ofThe number of the weighting units of the N channels connected with the first input end is sequentially reduced by 1, and the number of the weighting units of the P channels connected with the second input end is sequentially increased by 1.
When the first input end is connected with 0 weighting channel units of N channels, the second input end is connected with P channelsAnd a weighted channel unit.
When the first input end is connected with 1 weighting channel unit of N channels, the second input end is connected with P channelsAnd a weighted channel unit.
Compared with the prior art, the application has at least the following beneficial effects.
The present application is based on further analysis and study of the problems of the prior art, recognizing that the linearity of the phase interpolator circuit affects jitter in a PLL and BER in CDR applications, so that linearity is a very important indicator of the phase interpolator. In the phase interpolation architecture weighting unit control logic scheme, the weighting channel units have the greatest difference in consideration of mismatch, thereby resulting in the greatest nonlinearity of the output phase. The conventional weighting unit control logic scheme is that the first input terminal IN1 is connected to the P-channel and the second input terminal IN2 is connected to the N-channel, so IN the conventional scheme, code=0 andThe selected weighted channel units differ the most in consideration of mismatch, resulting in the greatest nonlinearity of the output phase. At the position ofWithin the range, the weighted channel unit difference is at mostAnd each. The difference source is related to whether the input signal goes through the P-channel or the N-channel, and the difference of the conventional weighting unit control logic scheme is the largest because the input signal goes through the P-channel and the N-channel.
Therefore, the application exchanges the input phase signal when the Code value Code reaches the intermediate value by adding the channel exchange module between the phase input signal and the weight selection module, and reduces the difference number of the P channel and the N channel of the weight selection module so as to realize the effect of reducing the nonlinearity of the phase interpolator circuit. Since the present application exchanges the input phase signal when the Code value Code reaches the intermediate value, code=0 andThe weighted channel units are chosen exactly the same, the resulting mismatch is minimal and the nonlinearity is improved. At the position ofWithin the range, the weighted channel unit difference is at mostAnd the number of non-linearities and differences are positively correlated. The proposed solution of the application improves the nonlinearity. Assume that the nonlinearity caused by the difference of the individual weighting units isThe nonlinearity of the proposed solution is thenThe traditional scheme is thatAbout half reduced.
Drawings
Fig. 1 is a drawing of the background art.
Fig. 2 is a second background art drawing.
Fig. 3 is a drawing of the third background art.
Fig. 4 is a block diagram illustrating a conventional weight selection module according to an embodiment of the present application.
Fig. 5 is a block diagram of channel switching and weight selection according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the description of the present application: unless otherwise indicated, the meaning of "a plurality" is two or more. The terms "first," "second," "third," and the like in this disclosure are intended to distinguish between the referenced objects without a special meaning in terms of technical connotation (e.g., should not be construed as emphasis on the degree of importance or order, etc.). The expressions "comprising", "including", "having", etc. also mean "not limited to" (certain units, components, materials, steps, etc.).
In one embodiment, a method for encoding a phase interpolator is provided, and in combination with fig. 4 and 5, the phase interpolator includes a phase input signal module, a weight selection module, and an output phase signal module that are sequentially connected, where the weight selection module includes a P-channel plurality of weighted channel units, an N-channel plurality of weighted channel units, and a decoding circuit; the phase interpolator also comprises a channel exchange module which is arranged between the phase input signal module and the weight selection module; the encoding method of the phase interpolator includes the following.
Receiving a first signal and a second signal from a phase input signal module by using a first input end and a second input end of a channel exchange module respectively; and the first signal and the second signal are respectively sent to the weight selection module by utilizing the first output end and the second output end of the channel exchange module.
The decoding circuit is utilized to connect a plurality of weighting channel units corresponding to the P channel and a plurality of weighting channel units corresponding to the N channel according to different Code values, and the channel switching module is controlled to switch between the P channel and the N channel; wherein, the total number of the weighting units which are correspondingly connected with the first signal and the second signal is kept unchanged, the number of the weighting units which are correspondingly connected with the first signal is monotonically decreased/increased along with the Code, and the number of the weighting units which are correspondingly connected with the second signal is monotonically increased/decreased along with the Code; when the Code value Code reaches the middle value of the whole change interval, the channel exchange module is used for exchanging the P channel and the N channel which are correspondingly connected with the first signal and the second signal.
In one embodiment, as shown in fig. 5, a phase interpolator is provided, which is configured to select two paths of channels according to different digital signals, and perform phase summation according to different weights to obtain an output phase signal, where the phase interpolator includes a phase input signal module, a weight selection module, and an output phase signal module that are sequentially connected, and the weight selection module includes a plurality of weighted channel units of P channels, a plurality of weighted channel units of N channels, and a decoding circuit; further comprises: the channel exchange module is arranged between the phase input signal module and the weight selection module.
The first input end and the second input end of the channel exchange module are respectively connected with the first output end and the second output end of the phase input signal module, and the first output end and the second output end of the channel exchange module are respectively connected with the weight selection module.
The decoding circuit is used for determining a plurality of weighting channel units corresponding to the P channel and a plurality of weighting channel units corresponding to the N channel which are connected with different Code values, and controlling the channel switching module to switch between the P channel and the N channel; wherein the total number of the weighting units connected with the first input end and the second input end is kept unchanged, the number of the weighting units connected with the first input end monotonically decreases/increases along with the Code, and the number of the weighting units connected with the second input end correspondingly monotonically increases/decreases along with the Code; when the Code value Code reaches the middle value of the whole change interval, the switched-on P channel and N channel are exchanged.
In this embodiment, the linearity of the phase interpolator circuit affects jitter in the PLL and BER in CDR applications, so linearity is a very important indicator of the phase interpolator. IN the circuit implementation, the nonlinear circuit and the number of phase weighting units are obviously positively correlated, taking an X bit phase interpolator as an example, four quadrature phase generating modules (not shown IN the figure) generate IN1, IN2, IN3, IN4 and INd (INd is the IN1 of the next period), thus four weight selection sections are provided, and each weight selection section sharesThe phase weighting units are commonly used for each weight selection interval in actual designAnd a phase weighting unit. The conventional weighting unit control logic scheme is different from the present embodiment in that whether there is a channel switch module or not, and the decoding circuit is also different accordingly. In the embodiment, a channel exchange module is added between the phase input signal and the weight selection module, the input phase signal is exchanged when the Code value Code is the intermediate value, and the difference number of the P channel and the N channel of the weight selection module is reduced, so that the nonlinear effect of the phase interpolator circuit is reduced.
As shown IN fig. 4, IN the conventional weighting unit control logic scheme, the first input terminal IN1 is connected to the P-channel, the second input terminal IN2 is connected to the N-channel, i.e. there is no channel switching module, IN this embodiment, a channel switching module is added between the IN1/IN2 and the P/N-channel, and the decoding circuit is used to control the channel switching module to switch the P/N-channel when the Code value Code is intermediate.
In one embodiment, the phase of the output phase signal is related to the number of weighted channel elements that are turned on by the first input and the second input, the greater the number of weighted channel elements that are turned on by the first input, the fewer the number of weighted channel elements that are turned on by the second input, and the phase of the output phase signal is closer to the phase of the signal that is passed through the first input.
In one embodiment, the total number of weighting units with the first and second inputs connected is kept unchanged, and the whole variation interval of the Code value Code is set asAt this time, the total number of weighting units with the first and second inputs turned on is kept to beIn a subsequent variation, the number of weighting units with the first input terminal being turned on is increased, while the number of weighting units with the second input terminal being turned on is decreased, and the two are complemented. The specific variations are shown below.
When code=0, the first input terminal is connected with the P channelThe second input end of each weighting channel unit is connected with 1 weighting channel unit of N channels.
At the position ofThe number of the weighting units of the P channel connected with the first input end is sequentially reduced by 1, and the number of the weighting units of the N channel connected with the second input end is sequentially increased by 1.
When the first input end is connected with the P channelA weighted channel unit with N channel connected to the second inputAnd a weighted channel unit.
When the first input end is connected with N channelA weighted channel unit with a second input connected to the P channelAnd a weighted channel unit. Here, the P-channel and the N-channel, which are connected to the first input terminal and the second input terminal, are exchanged.
At the position ofThe number of the weighting units of the N channels connected with the first input end is sequentially reduced by 1, and the number of the weighting units of the P channels connected with the second input end is sequentially increased by 1.
When the first input end is connected with 0 weighting channel units of N channels, the second input end is connected with P channelsAnd a weighted channel unit.
When the first input end is connected with 1 weighting channel unit of N channels, the second input end is connected with P channelsAnd a weighted channel unit.
In one embodiment, the whole variation interval of the Code value Code is set asThenAnd when the weighted channel units of the P channel and the N channel are different, the number of the weighted channel units is the largest. At this time, the number of differences between the weighted channel units of the P channel and the N channel is at mostAnd each.
Code=0The weighted channel units of the P channel and the N channel are exactly the same.
In one embodiment, the whole variation interval of the Code value Code is set as。
The change interval of the Code isAnd the number of the weighting units of the P channel is monotonically decreased, and the number of the weighting units of the N channel is monotonically increased.
The change interval of the Code isAnd the number of the weighting units of the P channel is monotonically increased, and the number of the weighting units of the N channel is monotonically decreased.
The whole change interval of the Code value Code is set asThe conventional weighting unit selection logic scheme is that when code=0, the first input terminal IN1 is turned on by the P-channelThe N-channel 1 weighting channel unit is connected to the second input IN 2.
At the position ofThe number of the weighting units of the P channel connected with the first input end IN1 is sequentially reduced by 1, and the number of the weighting units of the N channel connected with the second input end IN2 is sequentially increased by 1.
When the first input IN1 is connected to the P-channelThe weighted channel units are connected with the second input end IN2 through N channelsAnd a weighted channel unit.
When the first input IN1 is connected to the P-channelThe weighted channel units are connected with the second input end IN2 through N channelsAnd a weighted channel unit.
At the position ofThe number of the weighting units of the P-channel connected to the first input terminal IN1 is sequentially reduced by 1, and the number of the weighting units of the N-channel connected to the second input terminal IN2 is sequentially increased by 1.
IN the case of the first input IN1 being connected to the P-channel 0 weighting channel units and the second input IN2 being connected to the N-channelAnd a weighted channel unit.
When the first input IN1 is connected to the N-channelThe P-channel 1 weighting channel unit is connected to the second input IN 2.
In the conventional weighted cell selection logic scheme, code=0 andThe weighted channel units are chosen exactly the same, the resulting mismatch is minimal and the nonlinearity is improved. Within the range of the variation intervalThe weighted channel unit difference is at mostThe greatest difference occursWhen the first input IN1 goes through the P-channel 0 weighting units, the second input IN2 goes through the N-channelAnd a weighting unit.
In the present embodiment, however, code=0 andThe weighted channel units are chosen exactly the same, the resulting mismatch is minimal and the nonlinearity is improved. At the position ofWithin the range, the weighted channel unit difference is at mostIndividual (the greatest difference occursWhen the first input IN1 goes through the P-channelA weighting unit having a second input terminal IN2 for passing through the N channelA weighting unit) and the number of non-linearities and differences are positively correlated. The present embodiment improves the nonlinearity. Assume that the nonlinearity caused by the difference of the individual weighting units isThe nonlinearity of the present embodiment is thenThe traditional scheme is thatAbout half reduced.
IN this embodiment, taking a 10bit phase interpolator as an example, four quadrature phase generating modules (not shown IN the figure) generate IN1, IN2, IN3, IN4, INd (INd is IN1 of the next period), so there are four weight selection intervals, each of which has 256 phase weighting units, and IN practical design, each weight selection interval has 256 phase weighting units.
The whole variation interval of the Code value Code is Code:0-256. The total number of the weighting units connected with the first input end and the second input end is kept unchanged, and the whole change interval of the Code value Code is set as Code:0-256, wherein the total number of weighting units with the first input terminal and the second input terminal being turned on is kept to be 256, and in the subsequent variation, the number of weighting units with the first input terminal being turned on is increased, and the number of weighting units with the second input terminal being turned on is decreased, and the two are complemented.
When code=0, the first input terminal IN1 is turned on by 255 weighted channel units of P channel, and the second input terminal IN2 is turned on by 1 weighted channel unit of N channel.
At Code: IN the change interval of 0-127, the number of the weighting units of the P channel connected with the first input end IN1 is sequentially reduced by 1, and the number of the weighting units of the N channel connected with the second input end IN2 is sequentially increased by 1.
When code=127, the first input terminal IN1 is turned on by 128 weighted channel units of P channels, and the second input terminal IN2 is turned on by 128 weighted channel units of N channels.
When code=128, the first input terminal IN1 is turned on by 127 weighted channel units of N channels, and the second input terminal IN2 is turned on by 129 weighted channel units of P channels.
At Code:128-255, the number of weighting units of the N channels connected to the first input terminal IN1 is sequentially reduced by 1, and the number of weighting units of the P channels connected to the second input terminal IN2 is sequentially increased by 1.
When code=255, the first input terminal IN1 is turned on by N-channel 0 weighted channel units, and the second input terminal IN2 is turned on by P-channel 256 weighted channel units.
When code=256, the first input terminal IN1 is turned on by 1 weighted channel unit of N channels, and the second input terminal IN2 is turned on by 255 weighted channel units of P channels.
The Code is as follows: in the range of 0-256, when code=0 and code=127, the number of differences between the weighted channel units of the P channel and the N channel is maximum, and the maximum number is 127. When code=0 and code=256, the weighted channel units of the P channel and the N channel are exactly the same.
The Code is in the Code change section: and 0-127, the number of the weighting units of the P channel is monotonically decreased, and the number of the weighting units of the N channel is monotonically increased. P channels are reduced from 255 weighted channel units to 128, and N channels are increased from 1 to 128; at this time, the P-channel is connected to the first input terminal IN1, and the N-channel is connected to the second input terminal IN2.
The Code is in the Code change section: 128-255, the number of the weighting units of the P channel is monotonically increased, and the number of the weighting units of the N channel is monotonically decreased. The number of the P channel weighted channel units is increased from 129 to 256, and the number of N channels is reduced from 127 to 0; at this time, the P-channel is connected to the second input terminal IN2, and the N-channel is connected to the first input terminal IN1.
Also taking a 10bit phase interpolator as an example, the whole variation interval of the Code value Code is Code:0-256. The conventional weighting unit selection logic scheme is: when code=0, IN1 is turned on by 255 weighted channel units of P channel, and the second input terminal IN2 is turned on by 1 weighted channel unit of N channel.
At Code: IN the change interval of 0-127, the number of the weighting units of the P channel connected with the first input end IN1 is sequentially reduced by 1, and the number of the weighting units of the N channel connected with the second input end IN2 is sequentially increased by 1.
When code=127, the first input terminal IN1 is turned on by 128 weighted channel units of P channels and 128 weighted channel units of N channels.
When code=128, the first input terminal IN1 is turned on by 127 weighted channel units of P channel and 129 weighted channel units of N channel.
At Code:128-255, the number of the weighting units of the P-channel connected to the first input terminal IN1 is sequentially reduced by 1, and the number of the weighting units of the N-channel connected to the second input terminal IN2 is sequentially increased by 1.
When code=255, the first input terminal IN1 is turned on by P-channel 0 weighted channel units and N-channel 256 weighted channel units.
When code=256, the first input terminal IN1 is turned on by 255 weighted channel units of N channels and 1 weighted channel unit of P channels.
Therefore, the conventional weighted-cell selection logic scheme has a maximum difference in weighted channel cells selected by code=0 and code=256 in consideration of mismatch, and the maximum difference in weighted channel cells is 255. The resulting non-linearity of the output phase is maximized.
Compared with the embodiment, in code=0 and code=127, the number of the difference between the weighted channel units of the p channel and the N channel is maximum, and the number of the difference is 127 at maximum, which is 128 less than that of the conventional scheme. And the nonlinearity and the number of differences are positively correlated. The present embodiment improves the nonlinearity. Assume that the nonlinearity caused by the difference of the individual weighting units isThe nonlinearity of the present embodiment is thenThe traditional scheme is thatAbout half reduced.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
Claims (6)
1. The encoding method of the phase interpolator comprises a phase input signal module, a weight selection module and an output phase signal module which are sequentially connected, wherein the weight selection module comprises a plurality of P-channel weighting channel units, a plurality of N-channel weighting channel units and a decoding circuit; the phase interpolator is characterized by further comprising a channel exchange module, which is arranged between the phase input signal module and the weight selection module; the encoding method of the phase interpolator comprises the following steps:
receiving a first signal and a second signal from a phase input signal module by using a first input end and a second input end of the channel exchange module respectively; the first signal and the second signal are respectively sent into the weight selection module by utilizing a first output end and a second output end of the channel exchange module;
The decoding circuit is utilized to switch on a plurality of weighting channel units corresponding to the P channel and a plurality of weighting channel units corresponding to the N channel according to different Code values, and the channel exchange module is controlled to switch between the P channel and the N channel; wherein, the total number of the weighting units which are correspondingly connected with the first signal and the second signal is kept unchanged, the number of the weighting units which are correspondingly connected with the first signal is monotonically decreased/increased along with the Code, and the number of the weighting units which are correspondingly connected with the second signal is monotonically increased/decreased along with the Code; when the Code value Code reaches the middle value of the whole change interval, the channel exchange module is used for exchanging the P channel and the N channel which are correspondingly connected with the first signal and the second signal.
2. The phase interpolator is used for selecting two paths of channels through digital signals according to different digital signals and carrying out phase summation according to different weights to obtain an output phase signal, and comprises a phase input signal module, a weight selection module and an output phase signal module which are sequentially connected, wherein the weight selection module comprises a plurality of P-channel weighting channel units, a plurality of N-channel weighting channel units and a decoding circuit; characterized by further comprising: the channel exchange module is arranged between the phase input signal module and the weight selection module;
The first input end and the second input end of the channel switching module are respectively connected with the first output end and the second output end of the phase input signal module, and the first output end and the second output end of the channel switching module are respectively connected with the weight selection module;
The decoding circuit is used for determining a plurality of weighting channel units corresponding to the P channel and a plurality of weighting channel units corresponding to the N channel corresponding to the different Code value codes, and controlling the channel switching module to switch between the P channel and the N channel; wherein the total number of the weighting units connected with the first input end and the second input end is kept unchanged, the number of the weighting units connected with the first input end monotonically decreases/increases along with the Code, and the number of the weighting units connected with the second input end correspondingly monotonically increases/decreases along with the Code; when the Code value Code reaches the middle value of the whole change interval, the switched-on P channel and N channel are exchanged.
3. The phase interpolator of claim 2, comprising:
setting the whole variation interval of the Code value Code as ThenWhen the number of the weighted channel units of the P channel and the N channel is the largest;
code=0 The weighted channel units of the P channel and the N channel are exactly the same.
4. The phase interpolator of claim 2, comprising:
setting the whole variation interval of the Code value Code as ；
The change interval of the Code isThe number of the weighting units of the P channel is monotonically decreased, and the number of the weighting units of the N channel is monotonically increased;
the change interval of the Code is And the number of the weighting units of the P channel is monotonically increased, and the number of the weighting units of the N channel is monotonically decreased.
5. The phase interpolator of claim 2, comprising:
The phase of the output phase signal is related to the number of weighting channel units connected with the first input end and the second input end, and the more the number of the weighting channel units connected with the first input end is, the fewer the number of the weighting channel units connected with the second input end is, and the phase of the output phase signal is closer to the phase of the signal passing through the first input end.
6. The phase interpolator of claim 2, comprising:
when code=0, the first input terminal is connected with the P channel The second input end of the weighting channel unit is connected with 1 weighting channel unit of the N channels;
at the position of The number of the weighting units of the P channel connected with the first input end is sequentially reduced by 1, and the number of the weighting units of the N channel connected with the second input end is sequentially increased by 1;
when the first input end is connected with the P channel A weighted channel unit with N channel connected to the second inputA weighted channel unit;
When the first input end is connected with N channel A weighted channel unit with a second input connected to the P channelA weighted channel unit;
at the position of The number of the weighting units of the N channels connected with the first input end is sequentially reduced by 1, and the number of the weighting units of the P channels connected with the second input end is sequentially increased by 1;
when the first input end is connected with 0 weighting channel units of N channels, the second input end is connected with P channels A weighted channel unit;
When the first input end is connected with 1 weighting channel unit of N channels, the second input end is connected with P channels And a weighted channel unit.
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| JP2013201693A (en) * | 2012-03-26 | 2013-10-03 | Toshiba Corp | Phase interpolator and phase interpolation method |
| CN114421967A (en) * | 2022-01-24 | 2022-04-29 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic device |
| CN114651260A (en) * | 2019-11-14 | 2022-06-21 | 高通股份有限公司 | Phase selective convolution with dynamic weight selection |
| CN118018010A (en) * | 2024-04-08 | 2024-05-10 | 芯动微电子科技(武汉)有限公司 | Method and device for judging working stability of data clock recovery circuit |
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| JP2013201693A (en) * | 2012-03-26 | 2013-10-03 | Toshiba Corp | Phase interpolator and phase interpolation method |
| CN114651260A (en) * | 2019-11-14 | 2022-06-21 | 高通股份有限公司 | Phase selective convolution with dynamic weight selection |
| CN114421967A (en) * | 2022-01-24 | 2022-04-29 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic device |
| CN118018010A (en) * | 2024-04-08 | 2024-05-10 | 芯动微电子科技(武汉)有限公司 | Method and device for judging working stability of data clock recovery circuit |
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