CN119005116B

CN119005116B - Chip design method and system, and computer program product

Info

Publication number: CN119005116B
Application number: CN202410945324.6A
Authority: CN
Inventors: 李思隆
Original assignee: Shenzhen Aowei Lingxin Technology Co ltd
Current assignee: Shenzhen Aowei Lingxin Technology Co ltd
Priority date: 2024-07-15
Filing date: 2024-07-15
Publication date: 2025-06-10
Anticipated expiration: 2044-07-15
Also published as: CN119005116A

Abstract

The embodiment of the disclosure provides a chip design method and system and a computer program product, wherein the chip design method comprises the steps of obtaining design information aiming at a memory, wherein the design information comprises bit depth and bit width, area, power consumption and read-write frequency, selecting a plurality of alternative databases from a standard unit database, selecting at least one target database from the plurality of alternative databases according to the bit depth and the bit width of the memory, executing layout generation operation aiming at the memory according to the bit depth and the bit width of the memory and the bit depth and the bit width of the at least one target database, generating at least one simulation layout, obtaining simulation information of the at least one simulation layout, comparing the simulation information of the simulation layout with the design information of the memory, and taking the simulation layout as the target layout when the simulation information of the simulation layout is identical with the design information of the memory. By adopting the technical scheme, the balance among the performance, the power consumption and the area can be comprehensively considered, so that the performance of the chip is improved.

Description

Chip design method and system, and computer program product

Technical Field

The present disclosure relates to the field of integrated circuit technology, and in particular, to a chip design method and system, and a computer program product.

Background

In integrated circuit design, layout selection plays an important role in performance, power consumption and area of a memory chip. For example, for the same memory chip, when different layouts are used for designing, the performance, power consumption and area of the memory chip are different, and even the memory chip is difficult to reach the balance among the performance, the power consumption and the area, the performance of the memory chip is poor. Therefore, how to provide a technical solution to improve the performance of the chip becomes a technical problem to be solved.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide a chip design method, system, and computer program product, which can comprehensively consider the balance among the read-write frequency, power consumption, and area, so as to improve the performance of the chip.

The embodiment of the disclosure provides a chip design method, which comprises the following steps:

obtaining design information for a memory, wherein the design information comprises bit depth, bit width, area, power consumption and read-write frequency;

Selecting a plurality of alternative databases from the standard unit databases;

Selecting at least one target database from a plurality of candidate databases according to the bit depth and the bit width of the memory, wherein the bit depth and the bit width of the at least one target database are matched with the bit depth and the bit width of the memory;

according to the bit depth and the bit width of the memory and the bit depth and the bit width of at least one target database, performing layout generation operation aiming at the memory to generate at least one simulation layout;

And acquiring simulation information of at least one simulation layout, comparing the simulation information of the simulation layout with the design information of the memory, and taking the simulation layout as a target layout when the simulation information of the simulation layout is identical to the design information of the memory.

Optionally, the selecting a plurality of candidate databases from the standard cell databases includes:

selecting a plurality of databases containing at least the type of the memory based on the type of the memory to be designed;

Drawing performance curves of all databases, wherein parameters in the performance curves at least comprise area, power consumption and read-write frequency;

Under the condition of keeping the read-write frequency unchanged, the database meeting the design requirement is taken as an alternative database by comparing the area and the power consumption in the performance curve of each database.

Optionally, the generating at least one simulation layout according to the bit depth and bit width of the memory and the bit depth and bit width of at least one target database by performing a layout generating operation for the memory includes:

When the bit depth of the target database is identical to the bit depth of the memory and the bit width of the target database is identical to the bit width of the memory, performing layout generation operation on the target database through a pre-constructed script to generate a simulation layout corresponding to the memory;

When the bit depth of the target database is determined to be smaller than the bit depth of the memory and/or the bit width of the target database is determined to be smaller than the bit width of the memory, generating at least one simulation layout corresponding to the memory through the pre-constructed script after at least one splitting operation is performed on the bit depth and/or the bit width of the memory;

And when the bit depth of the target database is determined to be larger than the bit depth of the memory and/or the bit width of the target database is determined to be larger than the bit width of the memory, at least one combination operation is carried out on the bit depths and/or the bit widths of different memories, and at least one simulation layout corresponding to the memories is generated through the pre-built script.

Optionally, when determining that the bit depth of at least one target database is smaller than the bit depth of the memory and/or the bit width of at least one target database is smaller than the bit width of the memory, generating, through the pre-built script, at least one simulation layout corresponding to the memory after performing at least one splitting operation on the bit depth and/or the bit width of the memory, where the method includes:

Determining a splitting mode and splitting times of the memory according to a proportionality coefficient between the bit depth and the bit width of the memory when determining that the bit depth of at least one target database is smaller than the bit depth of the memory and/or the bit width of at least one target database is smaller than the bit width of the memory;

The method comprises the steps of carrying out at least one time of splitting on a memory to obtain a plurality of sub-memories according to the splitting times and the maximum splitting times of the memory, wherein the maximum splitting times are determined by the bit depth of the memory and the bit depth of a target database when the bit depth of the memory is split, and the maximum splitting times are determined by the bit width of the memory and the bit width of the target database when the bit width of the memory is split;

selecting at least one target database according to the bit depth and the bit width of the sub-memory, performing layout generation operation to generate a sub-simulation layout, and performing encapsulation operation after instantiating the sub-simulation layout to generate at least one simulation layout corresponding to the memory, wherein the number of times of instantiating the sub-simulation layout is the same as the number of times of splitting.

Optionally, after the generating the at least one simulation layout corresponding to the memory, the chip design method further includes at least one of the following:

The simulation information of the simulation layout is obtained, wherein the simulation information comprises simulation power consumption, simulation read-write frequency and simulation area;

When the simulation information of the simulation layout does not meet the design information of the memory, the splitting operation is executed again on the basis of at least one splitting operation on the bit depth or the bit width of the memory, and when the simulation information of the simulation layout does not meet the design information of the memory, the splitting operation is executed on the basis of at least one splitting operation on the bit depth or the bit width of the memory, and when the difference between the simulation read-write frequency of the simulation layout and the read-write frequency of the memory is determined to be in a second interval and the splitting frequency is even and larger than the preset splitting frequency, the splitting operation is executed on the basis of at least one splitting operation on the bit depth or the bit width of the memory.

Optionally, the chip design method further comprises at least one of the following operations:

Adding the simulation read-write frequency in the simulation parameters of the simulation layout to the design information of the memory;

adding the difference between the simulated read-write frequency in the simulated parameters of the simulated layout and the read-write frequency of the memory to the design information of the memory;

and recording simulation information of each simulation layout through the pre-constructed script, and storing the simulation information into a local file.

Optionally, the at least one target database includes a first target database and a second target database, and the port types of the first target database and the second target database are different; the at least one simulation layout comprises a first simulation layout and a second simulation layout, the first simulation layout corresponds to the first target database, and the first simulation layout corresponds to the second target database;

The obtaining the simulation information of at least one simulation layout, comparing the simulation information of the simulation layout with the design information of the memory, and taking the simulation layout as a target layout when the simulation information of the simulation layout is identical to the design information of the memory is determined, comprising:

Respectively acquiring simulation information of the first simulation layout and the second simulation layout, wherein the simulation information comprises simulation power consumption, simulation read-write frequency and simulation area;

Selecting the simulation layout of the simulation layout corresponding to the simulation read-write frequency identical to the read-write frequency of the memory, and comparing the simulation power consumption of the simulation layout with the power consumption of the memory when the simulation area of the simulation layout is identical to the area of the memory, until a simulation layout identical to the design information of the memory is generated as a target layout.

Optionally, after the simulation layout is used as the target layout when the simulation information of the simulation layout is determined to be the same as the design information of the memory, the chip design method further comprises the step of carrying out time sequence analysis on the target layout.

The embodiment of the disclosure also provides a chip design system, which comprises:

The system comprises an acquisition unit, a standard unit database, a storage unit and a storage unit, wherein the acquisition unit is suitable for acquiring design information for the storage, and the design information comprises bit depth, bit width, area, power consumption and read-write frequency;

The selecting unit is suitable for selecting at least one target database from a plurality of candidate databases according to the bit depth and the bit width of the memory, wherein the bit depth and the bit width of the at least one target database are matched with the bit depth and the bit width of the memory;

the simulation unit is suitable for executing layout generation operation aiming at the memory according to the bit depth and the bit width of the memory and the bit depth and the bit width of at least one target database to generate at least one simulation layout;

the processing unit is used for acquiring simulation information of at least one simulation layout, comparing the simulation information of the simulation layout with the design information of the memory, and taking the simulation layout as a target layout when the simulation information of the simulation layout is identical with the design information of the memory.

The disclosed embodiments also provide a computer program product comprising a computer program/instruction which, when executed by a processor, performs the steps of the method according to any of the preceding claims.

Compared with the prior art, the technical scheme of the embodiment of the disclosure has the following advantages:

According to the chip design method provided by the embodiment of the disclosure, at least one target database which is matched with the bit depth and the bit width of the memory can be selected from a plurality of candidate databases according to the bit depth and the bit width of the memory, and then the layout generation operation aiming at the memory can be executed according to the bit depth and the bit width of the memory and the bit depth and the bit width of the at least one target database, at least one simulation layout is generated, and when the simulation information of the simulation layout is determined to be identical with the design information of the memory, the memory corresponding to the target simulation layout is explained to meet the design requirement, so that the simulation layout can be used as the target layout. Thus, the read-write frequency, the power consumption, the area and the balance among the three can be comprehensively considered, so that the performance of the chip can be improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings used in the embodiments of the present disclosure or the description of the prior art will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

FIG. 1 illustrates a flow chart of a method of chip design in an embodiment of the disclosure;

FIG. 2 illustrates a flow chart of a method of selecting an alternative database in an embodiment of the present disclosure;

FIG. 3 illustrates a flow chart of a method of simulated layout generation in an embodiment of the present disclosure;

fig. 4 shows a schematic structural diagram of a chip design system in an embodiment of the disclosure.

Detailed Description

As described in the background, it is currently difficult to balance performance, power consumption, and area of the resulting memory chip, resulting in poor performance of the memory chip because:

the existing memory chip generation process only pays attention to a single performance index (such as read-write frequency), and comprehensive optimization of power consumption and area is ignored, so that the designed memory chip is difficult to achieve the optimal balance among performance, power consumption and area, and further the requirements of the performance, the power consumption and the area cannot be met at the same time.

In order to solve the technical problems, the embodiment of the disclosure provides a chip design method, which comprises the steps of obtaining design information for a memory, wherein the design information comprises bit depth and bit width, area, power consumption and read-write frequency, selecting a plurality of alternative databases from a standard unit database, selecting at least one target database from the plurality of alternative databases according to the bit depth and the bit width of the memory, wherein the bit depth and the bit width of the at least one target database are matched with the bit depth and the bit width of the memory, executing layout generation operation for the memory according to the bit depth and the bit width of the memory and the bit depth and the bit width of the at least one target database, generating simulation information of at least one simulation layout, comparing the simulation information of the simulation layout with the design information of the memory, and taking the simulation layout as a target layout when the simulation information of the simulation layout is identical with the design information of the memory.

It can be seen that in the chip design method provided by the embodiment of the disclosure, the read-write frequency, the power consumption and the area are comprehensively considered, and the balance among the three is considered, so that the performance of the chip can be improved.

In order that the above-recited objects, features and advantages of embodiments of the present disclosure will become more apparent, a more particular description of embodiments of the present disclosure will be rendered by reference to the appended drawings.

Referring to a flowchart of a chip design method in the embodiment of the disclosure shown in fig. 1, in some embodiments of the disclosure, the following steps may be performed as shown in fig. 1:

s11, acquiring design information for a memory.

In some implementations of the present disclosure, the design information may reflect parameter information of a memory to be formed by the present design, and an effect to be achieved by the memory.

In some embodiments, the design information may include bit depth and bit width, area, power consumption, and read-write frequency. The bit depth refers to the number of binary digits which can be stored in each storage unit (Cell) in the memory, the bit width refers to the number of binary digits which can be stored and transmitted in parallel in each storage unit in the memory, the area determines the storage capacity of the memory, the larger the area of the memory can be understood as the larger the corresponding storage capacity, the power consumption represents the energy consumed by the memory in the operation process, the read-write frequency reflects the exchange amount of data in the unit time of the memory in the operation process, the higher the read-write frequency is, the faster the read-write speed of the memory is, the data can be accessed more rapidly, but the power consumption is also increased.

In some embodiments of the present disclosure, the format of the design information may exist in the form of a table. For example, parameters of the design information may be filled in a form, and when reading is required, the contents in the form are converted into data satisfying the design requirement format by format conversion.

It should be noted that the types of design information listed in the above examples are merely examples. In some other examples, the design information may also include information of the type of memory, the write mask of the memory, the error correction code of the memory, the array of the memory, and so on.

S12, selecting a plurality of alternative databases from the standard unit databases.

In some implementations of the disclosure, the standard cell databases have a plurality of databases of different types, and include specifications and parameters of each database, and by selecting databases of different types and sizes, memories with different areas, power consumption, and read/write frequencies can be generated.

In some embodiments, multiple target databases may be obtained from a standard cell database based on information such as the type, specification, and parameters of each database.

In other embodiments, the target database may also be selected based on design requirements in determining the standard cell database.

It should be noted that, the standard cell database may be established in real time or may be obtained from an existing database, and the source of the standard cell database is not limited in the embodiments of the present disclosure.

S13, selecting at least one target database from a plurality of candidate databases according to the bit depth and the bit width of the memory.

In some implementations of the disclosure, when performing a simulation operation on a memory using a database, it is necessary to select at least one target database from a plurality of candidate databases based on a bit depth and a bit width of the memory, so that the bit depth and the bit width of the target database can be adapted to the bit depth and the bit width of the memory.

I.e. the bit depth and bit width of at least one target database, is adapted to the bit depth and bit width of the memory, whereby the memory is constituted by at least one of the target databases.

In some embodiments, "adapting" may refer to the bit depth of the target database being the same as the bit depth of the memory, the bit width of the target database being the same as the bit width of the memory, or the bit depth of the target database being the same as the bit depth of the memory, the bit width of the target database being proportional to the bit width of the memory (a scaling factor being greater than 1 and an integer), or the bit depth of the target database being proportional to the bit depth of the memory (a scaling factor being greater than 1 and an integer), the bit width of the target database being the same as the bit width of the memory, or the bit depth of the target database being proportional to the bit depth of the memory (a scaling factor being greater than 1 and an integer).

In short, there is at least one target database whose bit width and bit depth can meet the requirements of the memory, and at least one simulated layout corresponding to the bit depth and bit width of the memory can be generated by the at least one database.

S14, executing layout generation operation aiming at the memory according to the bit depth and the bit width of the memory and the bit depth and the bit width of at least one target database to generate at least one simulation layout.

In some implementations of the disclosure, through step S13, a target database adapted to the bit depth and the bit width of the memory may be obtained, and in consideration of the bit depth and the bit width of the memory, a scaling factor different from the bit depth and the bit width of the target database may be used to perform a corresponding layout generating operation to generate at least one simulation layout.

S15, acquiring simulation information of at least one simulation layout, comparing the simulation information of the simulation layout with the design information of the memory, and taking the simulation layout as a target layout when the simulation information of the simulation layout is identical to the design information of the memory.

In some implementations of the present disclosure, a memory may be simulated by multiple databases of different types, where the bit widths and bit depths of the simulated layouts are the same, and at this time, the simulated information of the simulated layout and the design information of the memory may be compared to determine a target simulated layout that is the same as the design information of the memory.

In some embodiments, when the comparison operation is performed, the simulation read-write frequency of the simulation layout and the read-write frequency of the memory can be compared first, and under the condition that the simulation read-write frequency of the simulation layout and the read-write frequency of the memory are the same, the simulation area of the simulation layout and the area of the memory, and the simulation power consumption of the simulation layout and the power consumption of the memory are compared sequentially, so that the simulation layout when the simulation information of the simulation layout and the design information of the memory are the same is used as the target layout.

That is, the read-write frequency, the area and the power consumption of the memory can be sequentially used as reference standards to select the target simulation layout from at least one simulation layout. Thus, the read-write frequency, the power consumption, the area and the balance among the three can be comprehensively considered, so that the performance of the chip can be improved.

In some embodiments of the present disclosure, for memories of the same type and the same specification, when using different databases for simulation, the read-write frequency, area and power consumption exhibited by the simulation layout are also different.

For example, for a certain database, when the simulation results in a memory with a bit width of 32 and a bit depth of 64, the performance is superior to that of memories formed by simulation of other databases, while when the simulation results in a memory with a bit width of 44 and a bit depth of 64, the performance is far inferior to that of memories formed by simulation of other databases, so that when the selected database is selected, the selected database needs to meet the selection requirement.

As an example, referring to the flowchart of an alternative database selection method in the embodiment of the disclosure shown in fig. 2, as shown in fig. 2, the following steps may be performed:

S21, selecting a plurality of databases containing at least the type of the memory based on the type of the memory to be designed.

In some embodiments of the present disclosure, the type of memory determines the type of database to be used.

For example, if the memory is single-ended, the selected database needs to include at least spsram, sprf, uhdsprf types.

And S22, drawing performance curves of all the databases, wherein parameters in the performance curves at least comprise area, power consumption and read-write frequency.

In some embodiments of the present disclosure, a large number of databases can be obtained via step S21, and there is a large difference between the databases, so that the performance curves of the databases can be drawn by reading the local files corresponding to the memories, so as to obtain different parameters and the performances of the databases under different parameter values.

S23, under the condition that the read-write frequency is kept unchanged, the areas and the power consumption in the performance curves of the databases are compared, and the database meeting the design requirement is taken as an alternative database.

In some embodiments of the present disclosure, the read-write frequency may be used as a reference, and the area parameter and the power consumption parameter of each database under different read-write frequencies may be obtained respectively, and after multiple comparisons, the database meeting the design requirement (i.e. when the read-write frequency is the same, the area is lower than the set area, and the power consumption is lower than the set power consumption) is used as the candidate database.

In other words, the comparison of the area and the power consumption is performed at the same read/write frequency, and the priority of using the database at different intervals is obtained. If the area and power consumption of the a-type database are not at all the same as those of the b-type database under the same interval, the b-type database is taken as an alternative database.

Through the selection mode, a plurality of alternative databases meeting design requirements can be obtained, so that the performance, the power consumption and the balance among areas of the memory to be formed can be further improved, and the performance of the chip is further improved.

In some embodiments of the present disclosure, as previously described, bit depth refers to the number of binary digits that each memory Cell (Cell) in a memory can store, and bit width refers to the number of binary digits that each memory Cell in a memory can store and transmit in parallel.

For example, a memory of one bit depth 256 and one bit width 64 is capable of storing 256 pieces of data of 64 bits wide.

In this case, referring to a flowchart of a simulation layout generating method in the embodiment of the present disclosure shown in fig. 3, as shown in fig. 3, the following steps may be performed:

s31, comparing the bit depth of the target database with the bit depth of the memory, and comparing the relation between the bit width of the target database and the bit width of the memory.

In some embodiments of the present disclosure, when performing a layout generation operation, an operation step corresponding to the bit depth of the target database and the bit depth of the memory, and the relation between the bit width of the target database and the bit width of the memory may be determined.

S32, when the bit depth of the target database is identical to the bit depth of the memory and the bit width of the target database is identical to the bit width of the memory, performing layout generation operation on the target database through a pre-constructed script to generate a simulation layout corresponding to the memory.

In some embodiments of the present disclosure, when it is determined that the bit depth of the target database is the same as the bit depth of the memory, and the bit width of the target database is the same as the bit width of the memory, it is described that the simulation operation can be performed by using the target database, so that the layout generation operation can be performed on at least one target database by reading the design information of the memory through the script constructed in advance, and a corresponding simulation layout is obtained.

Wherein "script" refers to a regression script that refers to a set of automated scripts for performing layout generation operations that are capable of automatically performing layout generation operations based on design information for a memory and at least one target database.

In some embodiments, assuming a target database with a bit depth of 256 and a bit width of 64 and a memory with a bit depth of 256 and a bit width of 64, then the generation of the simulated layout may be performed using this target database.

S33, when the bit depth of the target database is smaller than the bit depth of the memory and/or the bit width of the target database is smaller than the bit width of the memory, splitting the bit depth and/or the bit width of the memory at least once, and generating at least one simulation layout corresponding to the memory through the pre-constructed script.

In some embodiments of the present disclosure, if it is determined that the bit depth of the target database is smaller than the bit depth of the memory and/or the bit width of the target database is smaller than the bit width of the memory, it is indicated that a corresponding simulation layout cannot be generated using the currently selected target database. At this time, at least one splitting operation may be performed on the bit depth and/or bit width of the memory to reduce the bit depth and/or bit width of the memory to be split, so that the bit depth and bit width of the memory after splitting processing are consistent with the bit depth and bit width of the target database, and thus, design information of the memory may be read through a script constructed in advance, and layout generation operation may be performed on at least one target database to obtain a corresponding simulation layout.

As an example, assume a memory is a 256 bit depth, 64bit wide device capable of storing 256 64bit wide data. When the currently selected target database cannot directly generate the memory, the memory can be split into two 128x64 memories (namely bit depth splitting), four 64x64 memories, two 256x32 memories (namely bit width splitting), or four 256x16 memories, so that one splitting mode can be consistent with the bit depth and the bit width of the target database.

It should be noted that, firstly, after at least one splitting operation is performed on the bit depth and/or bit width of the memory, the bit depth and bit width of the split memory are consistent with the bit depth and bit width of at least one target database, and secondly, when the bit depth and/or bit width of the memory are split, a plurality of sub-memories with different bit depths and bit widths can be obtained by splitting, when the target database is selected by the sub-memories, the sub-memories with smaller splitting times can be preferentially selected to select the corresponding target database, because the more the split resources are, the more the area or the power consumption is, the more the wasted resources are.

For example, for a device with a memory having a bit depth of 256 and a bit width of 64, it can be split into two 128x64 memories (i.e., bit depth split), or four 64x64 memories, which are preferably selected with reference to the split into two 128x64 memories, to select the target database.

S34, when the bit depth of the target database is determined to be larger than the bit depth of the memory and/or the bit width of the target database is determined to be larger than the bit width of the memory, at least one combination operation is carried out on the bit depths and/or the bit widths of different memories, and then at least one simulation layout corresponding to the memories is generated through the pre-built script.

In some embodiments of the present disclosure, when it is determined that there is a target database having a bit depth greater than the bit depth of the memory and/or a bit width greater than the bit width of the memory, it is indicated that a corresponding one of the simulation layouts can be generated using the currently selected one of the target databases, but the bit width and/or bit depth of the simulation layout to be generated is greater than the bit depth and/or bit width of the memory to be formed. At this time, at least one combination operation may be performed on the bit depths and/or bit widths of different memories to increase the bit depths and/or bit widths of the desired memories, so that the bit depths and bit widths of the memories after the combination process are consistent with the bit depths and bit widths of the target databases, and thus, the design information of the memories may be read through the script constructed in advance, and the layout generation operation may be performed on at least one target database to obtain a corresponding simulation layout.

Therefore, according to the relation between the bit depth of the target database and the bit depth of the memory and the relation between the bit width of the target database and the bit width of the memory, the selected target database can be ensured to generate the simulation layout meeting the bit depth and bit width requirements of the memory, so that the generation efficiency can be improved, and the reworking phenomenon caused by the fact that the memory cannot be generated is avoided.

In some embodiments of the present disclosure, when it is determined that there is a target database having a bit depth smaller than that of the memory and/or a target database having a bit width smaller than that of the memory, a splitting manner may be determined according to a relationship between the bit depth and the bit width of the memory, and after splitting, a corresponding one of the simulation layouts is generated through a pre-constructed script.

In some embodiments of the present disclosure, step S33 may specifically include:

S331, when determining that the bit depth of at least one target database is smaller than the bit depth of the memory and/or the bit width of at least one target database is smaller than the bit width of the memory, determining a splitting mode and splitting times of the memory according to a proportionality coefficient between the bit depth and the bit width of the memory.

In some embodiments of the present disclosure, if it is determined that the bit depth of the target database is smaller than the bit depth of the memory and/or the bit width of the target database is smaller than the bit width of the memory, it is indicated that a corresponding simulation layout cannot be generated by using the currently selected target database, and at this time, the bit depth and/or the bit width of the memory may be split, and the number of splitting times may be determined simultaneously with the splitting.

Furthermore, the memory has different bit depth and bit width ratios, and the splitting modes adopted are different.

In some embodiments, the bit depth of the memory is split when it is determined that the proportionality coefficient between the bit depth and the bit width of the memory is greater than a first set value (the first set value is greater than 1, e.g., the first set value may be 2), otherwise the bit width of the memory is split.

Specifically, if the proportionality coefficient between the bit depth and the bit width of the memory is greater than the first set value, it indicates that the bit depth of the memory is greater than the bit width, and at this time, the bit depth of the memory can be split, so as to keep the bit width unchanged.

As an example, if the memory is a device having a bit depth of 256 bits wide 64, 256 64bit wide data can be stored. When the bit width of the selected target database is smaller than 256, the memory cannot be directly generated, and the ratio of 256 to 64 is 4 and is larger than the first set value 2, so that the memory can be split into two 128x64 memories in sequence.

In some embodiments of the present disclosure, the maximum number of splits may be determined by the bit depth of the memory and the bit depth of the target database, or by the bit width of the memory and the bit width of the target database. For example, the maximum split number is determined by the bit depth of the memory and the bit depth of the target database when splitting the bit depth of the memory, and the maximum split number is determined by the bit width of the memory and the bit width of the target database when splitting the bit width of the memory.

In one example, the maximum number of splits may be a ratio of a bit depth of the memory to a bit depth of the target database, or the maximum number of splits may be a ratio of a bit width of the memory to a bit width of the target database.

In this case, S332, according to the number of splitting times and the maximum number of splitting times of the memory, splitting the bit depth or bit width of the memory at least once, to obtain a plurality of sub-memories.

In some embodiments of the present disclosure, when determining the splitting manner and the splitting number performed on the memory, it may be necessary to determine whether to split the memory according to the actual splitting number of the memory.

For example, when it is determined that the number of splitting times of the memory is less than or equal to the maximum number of splitting times, it is described that at least one splitting may be performed on the bit depth or the bit width of the memory to obtain a plurality of sub-memories.

Specifically, when the number of splitting times of the memory is determined to be less than or equal to the maximum number of splitting times, splitting the bit depth or the bit width of the memory at least once to obtain a plurality of sub-memories, otherwise, stopping the current process.

S333, selecting at least one target database according to the bit depth and the bit width of the sub-memory, performing layout generation operation to generate a sub-simulation layout, instantiating the sub-simulation layout, and then performing packaging operation to generate at least one simulation layout corresponding to the memory.

In some embodiments of the present disclosure, when the splitting operation is performed, a plurality of sub-memories may be obtained, and then a target database having the same bit depth and bit width as the sub-memories may be selected, and after generating one sub-simulation layout by performing a layout generating operation on the selected target database, a plurality of sub-simulation layouts may be obtained by instantiating the sub-simulation layout, and then performing a packaging operation to generate at least one simulation layout corresponding to the memory.

In some embodiments, the number of times the sub-simulation layout is instantiated is the same as the number of splits. That is, the total number of the sub-simulation layouts and the initial sub-simulation layouts formed by instantiation is the same as the number of sub-memories formed by splitting.

In some embodiments of the present disclosure, the inventors further found that, by adopting the above scheme, a simulation layout meeting the bit depth and bit width requirements of the memory can be generated, and in consideration of the influence of power consumption and read-write frequency, when the simulation layout is generated, the simulation layout can be verified, and whether the power consumption and the read-write frequency of the simulation layout meet the requirements can be determined, so as to further balance the balance among the power consumption, the area and the read-write frequency of the memory.

As an example, the chip design method further comprises the step of obtaining simulation information of the simulation layout, wherein the simulation information comprises simulation power consumption, simulation read-write frequency and simulation area.

In some embodiments of the present disclosure, simulation parameters of a simulation layout may be obtained by reading a local file corresponding to the simulation layout. Because the simulation layout is opposite to the memory, the information such as power consumption, read-write frequency and area of the simulation layout formed by the current generation method can be obtained.

And then, when the simulation information of the simulation layout does not meet the design information of the memory, executing splitting operation on the memory again on the basis of at least one splitting operation on the bit depth or the bit width of the memory.

Specifically, by comparing the simulation parameters of the simulation layout with the design information of the memory, it can be determined whether the simulation parameters can meet the design information requirement of the memory, so that it can be determined whether the splitting operation needs to be performed again on the memory.

As an optional example, when it is determined that the simulation information of the simulation layout does not meet the design information of the memory, when it is determined that a difference value between the simulation read-write frequency of the simulation layout and the read-write frequency of the memory is in a first interval, a bit depth or bit width splitting operation is added to the memory on the basis of performing at least one splitting operation on the bit depth or bit width of the memory.

Specifically, when it is determined that the difference between the simulated read-write frequency of the simulated layout and the read-write frequency of the memory is in the first interval, it is indicated that the simulated read-write frequency of the simulated layout is far lower than the read-write frequency of the memory (for example, the simulated read-write frequency is 800mHz and the read-write frequency is 1200 mHz), and at this time, after splitting processing can be performed again, the simulated layout is generated so as to improve the simulated read-write frequency.

As a further alternative example, when it is determined that the difference between the simulated read-write frequency in the simulation parameters of the simulation layout and the read-write frequency of the memory is in the second interval and the number of splitting times is even and greater than the preset number of splitting times, the splitting operation is performed on the bit depth or the bit width of the memory at the same time on the basis of performing at least one splitting operation on the bit depth or the bit width of the memory.

Wherein the first interval is much larger than the second interval.

In some embodiments of the present disclosure, when it is determined that a difference between a simulated read-write frequency in a simulation parameter of a simulation layout and a read-write frequency of a memory is in a second interval, it is indicated that a frequency difference between the two is small, and the two frequencies can be consistent by splitting operation on a bit depth and a bit width of the memory at the same time.

For example, when it is determined that the difference between the simulated read-write frequency in the simulation parameters of the simulation layout and the read-write frequency of the memory is in the second interval, it may be determined whether the current splitting number is even, and on the basis that the splitting number is even and is equal to or greater than 4, splitting operation is performed on the bit depth and the bit width of the memory at the same time.

As an alternative example, taking the number of splitting times as 6 as an example, the bit depth is split into 6-2-i (i base number is 0) at first, the width is split into 2+i, then i is increased, then the bit depth is split into 4, the bit degree is split into 2, the bit depth is split into 3, the bit width is split into 3, the bit depth is split into 2, the bit width is split into 4 and the like until the simulation layout meeting the requirements is generated.

In some embodiments of the present disclosure, after generating at least one simulation layout corresponding to the memory, the chip design method further includes adding a simulation read-write frequency in a simulation parameter of the simulation layout to design information of the memory, or adding a difference between the simulation read-write frequency in the simulation parameter of the simulation layout and the read-write frequency of the memory to the design information of the memory.

In this way, in the subsequent generation process of the simulation layout, if the simulation layout is split into memories with the same size, the read-write frequency can be directly compared through the data recorded in advance, so that the simulation layout generation operation can be executed only when the read-write frequency is the same.

For example, a memory with a frequency of 1000mHz has been previously generated, but now the requirements are modified, for example a memory of 1200mHz is required. By comparing the stored information values, it is found that if the previous forming mode is adopted, the read-write frequency difference value is 200mHz, at this time, the splitting operation can be directly performed, the splitting operation is not required to be performed after the simulation layout is generated, and the generating efficiency is improved.

In some embodiments of the present disclosure, the simulation information of each simulation layout may also be recorded through the pre-constructed script and stored in a local file. Therefore, all memory information can be intuitively acquired, and if updating and optimizing are needed to be carried out later or the local file can be directly called during regeneration, so that the required time is reduced and the efficiency is improved.

In some alternative examples, after the simulation layout is generated, all information required by the user can be added to the design information in a script mode. All information needed by the user comprises splitting parameters, read-write frequency, area, power consumption and the like.

In some embodiments of the present disclosure, when selecting the target databases, at least one target database includes a first target database and a second target database, and the port types of the first target database and the second target database are different.

Correspondingly, the at least one simulation layout comprises a first simulation layout and a second simulation layout, the first simulation layout corresponds to the first target database, and the first simulation layout corresponds to the second target database.

In this case, the obtaining simulation information of at least one of the simulation layouts, comparing the simulation information of the simulation layout with the design information of the memory, and when determining that the simulation information of the simulation layout is identical to the design information of the memory, taking the simulation layout as a target layout includes:

Specifically, in the process of generating the simulation layout, the first simulation layout and the second simulation layout may be generated simultaneously, at this time, the read-write frequency of the first simulation layout and the second simulation layout may be compared in advance, and a simulation layout with a larger read-write frequency may be selected from the first simulation layout and the second simulation layout, for example, at least one simulation layout in the first simulation layout and/or the second simulation layout may be selected.

And then comparing the area and the power consumption parameters of the simulation layout and the memory in turn until a simulation layout which is the same as the design information of the memory is obtained as a target layout, and if not, re-executing the layout generation operation.

As an alternative example, the first simulation layout is sprf x 1024x64, the second simulation layout is spsram x 1024x64, the first simulation layout is taken as the simulation layout compared with the memory if the read-write frequency of the first simulation layout is larger than that of the second simulation layout, if the read-write frequency, the simulation area and the simulation power consumption of the first simulation layout are the same as those of the memory, the first simulation layout is taken as the target layout, and if the read-write frequency, the simulation area and the simulation power consumption of the first simulation layout are not the same as those of the memory, the memory is split, and a new simulation layout is regenerated.

In some optional examples, after determining the target simulation layout, performing time sequence analysis on the target layout, and when determining that the time sequence of the target simulation layout meets the set time sequence, taking a memory corresponding to the target simulation layout as a target memory.

Specifically, by adopting the steps, the simulation layout meeting the design information requirement can be designed. In actual operation of the memory, the timing of the memory needs to satisfy the timing constraints and time relationships of signals in the circuit or system to ensure that the memory will operate properly in accordance with the expected performance and timing specifications when applied to the circuit or system.

In some embodiments, it may be ensured that the memory is able to meet timing requirements at the desired process point of view through timing analysis techniques (e.g., static timing analysis).

The timing requirements may include timing constraints (e.g., clock frequency, maximum delay, and timing relationships), timing analysis, i.e., a process of verifying whether the circuit timing requirements meet design specifications, timing logic modeling, i.e., relationships involving registers, clock signals, and timing logic design, and latency control, i.e., allowing specific time delays to be introduced during statement execution, including regular latency and embedded latency.

Furthermore, after the time sequence of the target simulation layout is determined to meet the set time sequence, the actual chip design and test verification process can be performed, so that the read-write frequency, the power consumption and the area performance of the target simulation layout in actual application are ensured to meet the expectations.

The chip design method is described in detail above with respect to some embodiments, and for better understanding and implementation by those skilled in the art, the corresponding product is also described in detail below with respect to some embodiments.

Referring to the schematic structure of the chip design system shown in fig. 4, in the embodiment of the present disclosure, the chip design system 100 includes:

an acquisition unit 110 adapted to acquire design information for the memory, the design information including bit depth and bit width, area, power consumption, and read-write frequency;

a selecting unit 120, adapted to select at least one target database from the plurality of candidate databases according to the bit depth and bit width of the memory, where the bit depth and bit width of the at least one target database are adapted to the bit depth and bit width of the memory;

A simulation unit 130 adapted to perform a layout generation operation for the memory according to the bit depth and bit width of the memory and the bit depth and bit width of at least one of the target databases, generating at least one simulated layout;

And the processing unit 140 acquires simulation information of at least one simulation layout, compares the simulation information of the simulation layout with the design information of the memory, and takes the simulation layout as a target layout when the simulation information of the simulation layout is determined to be identical with the design information of the memory.

It should be understood that the above division of each unit is only a division of a logic function, and may be fully or partially integrated into a physical entity or may be physically separated when actually implemented. Furthermore, the above units may be implemented in the form of processor-invoked software.

For example, a system is employed that includes a processor, such as a general purpose processor, such as a central processing unit (central processing unit, CPU), coupled to a memory, where the memory has instructions stored therein, and the processor invokes the instructions stored in the memory to implement any one of the methods or to implement the functions of the units in the above embodiments, where the memory may be internal to the device or external to the device. Or each of the above units may be implemented in the form of a hardware circuit, and the functions of some or all of the units may be implemented by a design of a hardware circuit, which may be understood as one or more processors. For example, in one implementation, the hardware circuitry is an Application Specific Integrated Circuit (ASIC) that implements the functionality of some or all of the above units through the design of internal component logic relationships within the circuit, and in another implementation, the hardware circuitry may be implemented by a programmable logic device (programmable logic device, PLD) that may include a number of logic gates that are configured with configuration files to implement the functionality of some or all of the above units. All units of the above system may be realized in the form of a processor calling program in whole, or in the form of a hardware circuit in whole, or in part, in the form of a processor calling program in part, and in the rest in the form of a hardware circuit in part.

Embodiments of the present disclosure also provide a computer system suitable for use in implementing the chip-based design methodology.

It should be noted that, the computer system of the electronic device shown below is only an example, and should not impose any limitation on the functions and the application scope of the embodiments of the present application.

The computer system includes a central processing unit (Central Processing Unit, CPU) that can perform various appropriate actions and processes, such as performing the methods described in the above embodiments, according to a program stored in a Read-Only Memory (ROM) or a program loaded from a storage section into a random access Memory (Random Access Memory, RAM). In the RAM, various programs and data required for the system operation are also stored. The CPU, ROM, and RAM are connected to each other by a bus 304. An Input/Output (I/O) interface is also connected to the bus.

Connected to the I/O interface are an input section including a keyboard, a mouse, and the like, an output section including an output section such as a Cathode Ray Tube (CRT), a Liquid crystal display (Liquid CRYSTAL DISPLAY, LCD), and the like, a storage section including a hard disk, and the like, and a communication section including a network interface card such as a LAN (Local Area Network) card, a modem, and the like. The communication section performs communication processing via a network such as the internet. The drives are also connected to the I/O interfaces as needed. Removable media such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, and the like are mounted on the drive as needed so that a computer program read therefrom is mounted into the storage section as needed.

In particular, according to embodiments of the present application, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present application include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising a computer program for performing the method shown in the flowchart. In such embodiments, the computer program may be downloaded and installed from a network via a communication portion, and/or installed from a removable medium. When being executed by a Central Processing Unit (CPU), performs the various functions defined in the system of the present application.

It should be noted that, the computer readable medium shown in the embodiments of the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of a computer-readable storage medium may include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-Only Memory (ROM), an erasable programmable read-Only Memory (Erasable Programmable Read Only Memory, EPROM), a flash Memory, an optical fiber, a portable compact disc read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with a computer-readable computer program embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. A computer program embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, etc., or any suitable combination of the foregoing.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. Where each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units involved in the embodiments of the present application may be implemented by software, or may be implemented by hardware, and the described units may also be provided in a processor. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.

According to one aspect of the present application, there is provided a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The computer instructions are read from the computer-readable storage medium by a processor of a computer device, and executed by the processor, cause the computer device to perform the methods provided in the various alternative implementations described above.

As another aspect, the present application also provides a computer-readable medium that may be included in the electronic device described in the above embodiment, or may exist alone without being incorporated into the electronic device. The computer-readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to implement the methods described in the above embodiments.

It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the application. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, and includes several instructions to cause a computing device (may be a personal computer, a server, a touch terminal, or a network device, etc.) to perform the method according to the embodiments of the present application.

Although the embodiments of the present disclosure are disclosed above, the present disclosure is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure is therefore intended to be limited only by the appended claims.

Claims

1. A chip design method, comprising:

acquiring simulation information of at least one simulation layout, comparing the simulation information of the simulation layout with the design information of the memory, and taking the simulation layout as a target layout when the simulation information of the simulation layout is identical to the design information of the memory;

Wherein the generating at least one simulation layout according to the bit depth and bit width of the memory and the bit depth and bit width of at least one target database by performing layout generating operation for the memory comprises:

When the bit depth of the target database is determined to be larger than the bit depth of the memory and/or the bit width of the target database is determined to be larger than the bit width of the memory, at least one combination operation is carried out on the bit depths and/or the bit widths of different memories, and at least one simulation layout corresponding to the memories is generated through the pre-built script;

When determining that the bit depth of the target database is smaller than the bit depth of the memory and/or the bit width of the target database is smaller than the bit width of the memory, generating at least one simulation layout corresponding to the memory through the pre-constructed script after performing at least one splitting operation on the bit depth and/or the bit width of the memory, wherein the method comprises the following steps:

2. The chip design method according to claim 1, wherein the selecting a plurality of candidate databases from the standard cell databases comprises:

3. The chip design method according to claim 1, wherein after the generating the at least one simulation layout corresponding to the memory, the chip design method further comprises at least one of:

When the simulation information of the simulation layout does not meet the design information of the memory, the splitting operation is executed again on the basis of at least one splitting operation on the bit depth or the bit width of the memory, and when the difference between the simulation read-write frequency of the simulation layout and the read-write frequency of the memory is determined to be in a second interval and the splitting frequency is even and larger than the preset splitting frequency, the splitting operation is executed on the basis of at least one splitting operation on the bit depth or the bit width of the memory.

4. The chip design method according to claim 3, further comprising at least one of:

5. The chip design method according to claim 1, wherein at least one target database includes a first target database and a second target database, and port types of the first target database and the second target database are different; the at least one simulation layout comprises a first simulation layout and a second simulation layout, the first simulation layout corresponds to the first target database, and the second simulation layout corresponds to the second target database;

6. The chip design method according to claim 1, wherein the chip design method further comprises performing timing analysis on the target layout after determining that the simulation information of the simulation layout is the same as the design information of the memory.

7. A chip design system, comprising:

The processing unit is used for acquiring simulation information of at least one simulation layout, comparing the simulation information of the simulation layout with the design information of the memory, and taking the simulation layout as a target layout when the simulation information of the simulation layout is identical with the design information of the memory;

Wherein the simulation unit is further configured to:

8. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the method of any of claims 1 to 6.