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CN119008522A - Three-dimensional integration method and three-dimensional integration structure based on submicron through silicon vias - Google Patents

Three-dimensional integration method and three-dimensional integration structure based on submicron through silicon vias Download PDF

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CN119008522A
CN119008522A CN202411092291.1A CN202411092291A CN119008522A CN 119008522 A CN119008522 A CN 119008522A CN 202411092291 A CN202411092291 A CN 202411092291A CN 119008522 A CN119008522 A CN 119008522A
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wafer
bonding
processed
silicon
layer
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陈浪
王玮
张驰
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Peking University
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Peking University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本申请提供一种基于亚微米硅通孔的三维集成方法和三维集成结构，涉及半导体技术领域，包括：对第一晶圆的第一表面进行处理，得到处理后第一晶圆，处理后第一晶圆的第一表面上为键合层级结构，键合层级结构包括：第一支撑层，和，嵌入第一支撑层的多个金属衬垫；在第二晶圆的第二表面上制备多个第一硅通孔；向第一硅通孔中填充第一金属材料，得到多个填充后硅通孔；在二氧化硅绝缘层背离第二表面的表面，制备键合层级结构，得到处理后第二晶圆；键合处理后第一晶圆和处理后第二晶圆，对处理后第二晶圆进行减薄，减薄至填充后硅通孔的孔径的10倍；在处理后第二晶圆背离第二表面的表面，依次键合一个或多个第三晶圆，得到三维集成结构。

The present application provides a three-dimensional integration method and a three-dimensional integrated structure based on submicron silicon vias, which relate to the field of semiconductor technology, and include: processing a first surface of a first wafer to obtain a processed first wafer, wherein the first surface of the processed first wafer is a bonding hierarchical structure, and the bonding hierarchical structure includes: a first supporting layer, and a plurality of metal pads embedded in the first supporting layer; preparing a plurality of first silicon vias on the second surface of a second wafer; filling the first silicon vias with a first metal material to obtain a plurality of filled silicon vias; preparing a bonding hierarchical structure on a surface of a silicon dioxide insulating layer away from the second surface to obtain a processed second wafer; bonding the processed first wafer and the processed second wafer, and thinning the processed second wafer to 10 times the aperture of the filled silicon vias; bonding one or more third wafers in sequence on a surface of the processed second wafer away from the second surface to obtain a three-dimensional integrated structure.

Description

Three-dimensional integration method and three-dimensional integration structure based on submicron through silicon vias
Technical Field
The application relates to the technical field of semiconductors, in particular to a three-dimensional integration method and a three-dimensional integration structure based on submicron through silicon vias.
Background
With the rapid development of technologies such as artificial intelligence, automatic driving and 5G networks, the demands of various fields on chip computing power are rapidly increasing. However, the nano-fabrication process of integrated circuits has approached physical limits, and it has become increasingly difficult to increase the power of the chip by shrinking the transistor size. In this case, the importance of using heterogeneous integration of core particles (Chiplet) to extend and extend moore's law is increasingly highlighted, and integrated circuits are evolving from two-dimensional integration to three-dimensional integration.
Through Silicon Vias (TSVs) are becoming increasingly important as a key technology for three-dimensional integration to enable shortest signal connections between multiple layers of stacks. Along with the continuous downsizing and continuous enhancement of functions of the three-dimensional integrated circuit, the TSV technology will continuously evolve to micro-nano scale TSVs to realize higher integration level, faster data transmission speed and lower power consumption. However, current TSV technology lacks systematic three-dimensional integrated structures and corresponding process designs for sub-micron through silicon vias. Therefore, it is needed to propose a three-dimensional integration method and a three-dimensional integration structure based on submicron through silicon vias to realize a three-dimensional integration process for submicron through silicon vias.
Disclosure of Invention
In view of the foregoing, embodiments of the present application provide a three-dimensional integration method and three-dimensional integration structure based on submicron through-silicon vias, so as to overcome or at least partially solve the foregoing problems.
In a first aspect of an embodiment of the present application, there is provided a three-dimensional integration method based on submicron through silicon vias, the method including:
Processing a first surface of a first wafer to obtain a processed first wafer, wherein the first surface is a surface to be bonded of the first wafer, the first surface of the processed first wafer is a bonding hierarchical structure, and the bonding hierarchical structure comprises: a first support layer, and a plurality of metal pads embedded in the first support layer; the surface of the first wafer, which is away from the first surface, is interconnected with a first substrate;
The second surface of the second wafer is a surface to be bonded, and a plurality of first through silicon vias are prepared on the second surface by etching; the aperture of the first through silicon via is smaller than 1 micron;
Depositing a silicon dioxide insulating layer on the second surface;
Filling a first metal material into the first through silicon vias by Physical Vapor Deposition (PVD), atomic Layer Deposition (ALD) or electroplating to obtain a plurality of filled through silicon vias;
Preparing the bonding hierarchical structure on the surface of the silicon dioxide insulating layer, which is away from the second surface, so as to obtain a second wafer after treatment;
Mixing and bonding the processed first wafer and the processed second wafer, and thinning the processed second wafer to 10 times of the aperture of the filled through silicon via;
and sequentially bonding one or more third wafers on the surface of the processed second wafer, which is away from the second surface, to obtain a three-dimensional integrated structure, wherein the structure of the third wafer is the same as that of the processed first wafer or the processed second wafer.
In one possible implementation manner, the processing the first surface of the first wafer to obtain a processed first wafer includes:
Preparing a first supporting layer which takes silicon dioxide as a material on the first surface by means of thermal oxidation or Chemical Vapor Deposition (CVD);
Preparing a plurality of through holes in the first supporting layer by etching;
depositing a seed layer on the surface of the first supporting layer in a magnetron sputtering mode;
filling metal copper into the through hole in an electroplating manner until the metal copper completely fills the through hole to obtain a plurality of metal gaskets embedded into the first supporting layer;
and removing redundant metal materials on the surface of the first supporting layer, which is away from the first surface, in a Chemical Mechanical Polishing (CMP) mode, so that the surface of the first supporting layer is flat, and the bonding hierarchical structure is obtained.
In one possible embodiment, the preparing a plurality of through holes in the first supporting layer by etching includes:
defining a rewiring RDL image and a chip circuit contact point position PAD on the surface of the first supporting layer in a photoetching mode;
and carrying out plasma etching on the first supporting layer according to the RDL image and the PAD until the first surface is exposed, so as to obtain a plurality of through holes.
In one possible implementation, the hybrid bonding the processed first wafer and the processed second wafer, thinning the processed second wafer to 10 times the aperture of the filled through silicon via, includes:
aligning the metal pad embedded in the bonding hierarchical structure of the processed first wafer with the metal pad embedded in the bonding hierarchical structure of the processed second wafer, and bonding the processed first wafer and the processed second wafer;
And thinning the surface of the treated second wafer, which is away from the second surface, by adopting a multi-step thinning method to 10 times of the aperture of the filled through silicon via, wherein the first metal material is tungsten, copper or cobalt.
In one possible implementation manner, the surface of the second wafer facing away from the second surface after the processing sequentially bonds with one or more third wafers, including:
taking the surface of the processed second wafer, which is away from the second surface, as a third surface, and preparing the bonding hierarchical structure on the third surface;
sequentially bonding one or more third wafers on a surface of the bonding hierarchy on the third surface;
And preparing a plurality of second through silicon vias filled with a second metal material on the surface of the wafer which is bonded for the last time and is away from the bonding surface, and interconnecting the surface and the second substrate to obtain the three-dimensional integrated structure.
In a possible embodiment, in the case that the third wafer currently bonded is not the last wafer bonded, the structure of the third wafer currently bonded is the same as the structure of the second wafer after processing;
In the case that the third wafer currently bonded is the last wafer to be bonded, the structure of the third wafer currently bonded is the same as that of the first wafer after processing or the second wafer after processing.
In one possible embodiment, the sequentially bonding one or more third wafers includes:
aligning a metal pad embedded in a bonding hierarchical structure of the surface of the back of the uppermost wafer away from the bonding surface with the metal pad embedded in the bonding hierarchical structure of the third wafer, and bonding the uppermost wafer and the third wafer; thinning the third wafer by adopting a multi-step thinning method to 10 times of the aperture of the filled through silicon via of the third wafer;
Preparing the bonding hierarchical structure on the surface of the third wafer, which is away from the bonding surface;
The above steps are repeated until the last third wafer is bonded.
In one possible embodiment, the thickness of the silicon dioxide insulating layer is less than or equal to 50nm; the thickness of the first supporting layer is 1 um-5 um.
In one possible embodiment, the second through silicon via has an aperture diameter greater than 10um.
The second aspect of the embodiment of the application also provides a three-dimensional integrated structure based on the submicron through silicon vias, which is prepared by the three-dimensional integrated method based on the submicron through silicon vias in the first aspect.
A third aspect of the embodiments of the present application provides a three-dimensional integration apparatus based on submicron through-silicon vias, for performing the steps in the three-dimensional integration method provided in the first aspect, the apparatus comprising:
The first wafer processing module is used for processing a first surface of a first wafer to obtain a processed first wafer, the first surface is a surface to be bonded of the first wafer, the first surface of the processed first wafer is a bonding hierarchical structure, and the bonding hierarchical structure comprises: a first support layer, and a plurality of metal pads embedded in the first support layer; the surface of the first wafer, which is away from the first surface, is interconnected with a first substrate;
a second wafer first processing module for preparing a plurality of first through silicon vias by etching on the second surface; the second surface of the second wafer is a surface to be bonded, and the aperture of the first through silicon via is smaller than 1 micron;
A second wafer second processing module for depositing a silicon dioxide insulating layer on the second surface;
The second wafer third processing module is used for filling a first metal material into the first through-silicon-via through Physical Vapor Deposition (PVD), atomic Layer Deposition (ALD) or electroplating to obtain a plurality of filled through-silicon-vias;
A fourth processing module of the second wafer, configured to prepare the bonding hierarchical structure on a surface of the silicon dioxide insulating layer facing away from the second surface, so as to obtain a processed second wafer;
The first bonding module is used for hybrid bonding the processed first wafer and the processed second wafer, and thinning the processed second wafer to 10 times of the aperture of the filled through silicon via;
and the second bonding module is used for sequentially bonding one or more third wafers on the surface of the processed second wafer, which is away from the second surface, so as to obtain a three-dimensional integrated structure, wherein the structure of the third wafer is the same as that of the processed first wafer or the processed second wafer.
The embodiment of the application provides a three-dimensional integration method based on a submicron through silicon via, which comprises the following steps: processing a first surface of a first wafer to obtain a processed first wafer, wherein the first surface is a surface to be bonded of the first wafer, the first surface of the processed first wafer is a bonding hierarchical structure, and the bonding hierarchical structure comprises: a first support layer, and a plurality of metal pads embedded in the first support layer; the surface of the first wafer, which is away from the first surface, is interconnected with a first substrate; the second surface of the second wafer is a surface to be bonded, and a plurality of first through silicon vias are prepared on the second surface by etching; the aperture of the first through silicon via is smaller than 1 micron; depositing a silicon dioxide insulating layer on the second surface; filling a first metal material into the first through silicon vias by Physical Vapor Deposition (PVD), atomic Layer Deposition (ALD) or electroplating to obtain a plurality of filled through silicon vias; preparing the bonding hierarchical structure on the surface of the silicon dioxide insulating layer, which is away from the second surface, so as to obtain a second wafer after treatment; mixing and bonding the processed first wafer and the processed second wafer, and thinning the processed second wafer to 10 times of the aperture of the filled through silicon via; and sequentially bonding one or more third wafers on the surface of the processed second wafer, which is away from the second surface, to obtain a three-dimensional integrated structure, wherein the structure of the third wafer is the same as that of the processed first wafer or the processed second wafer.
According to the three-dimensional integration method provided by the application, the submicron-level TSV is prepared by etching the first through silicon via with the aperture smaller than 1 micron on the second wafer and filling the first metal material in the first through silicon via. And then, wafer hybrid bonding is realized through bonding hierarchical structures on the first wafer and the second wafer, and one or more third wafers (generating a multi-level TSV structure) are sequentially bonded to obtain a three-dimensional integrated structure, so that a three-dimensional integrated process based on submicron through silicon vias is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of steps of a three-dimensional integration method based on sub-micron through silicon vias provided by an embodiment of the application;
Fig. 2 is a schematic structural diagram of a processed first wafer formed in a three-dimensional integration method according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a first supporting layer and a through hole formed in a three-dimensional integration method according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a second wafer processing procedure in a three-dimensional integration method according to an embodiment of the disclosure;
Fig. 5 is a schematic structural diagram of a processed second wafer formed in a three-dimensional integration method according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a bonding structure between a processed first wafer and a processed second wafer according to an embodiment of the present application;
Fig. 7 is a schematic diagram of a thinned structure formed in a three-dimensional integration method according to an embodiment of the present application;
FIG. 8 is a bonding hierarchy of a third surface formed in a three-dimensional integration method according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a process of bonding a third wafer formed in a three-dimensional integration method according to an embodiment of the application;
FIG. 10 is a schematic diagram of the structure of a wafer bonded last time in a three-dimensional integration method according to an embodiment of the application;
FIG. 11 is a schematic diagram of a three-dimensional integrated structure based on sub-micron through silicon vias according to an embodiment of the present application;
FIG. 12 is a schematic diagram of another three-dimensional integrated structure based on sub-micron through-silicon vias provided by an embodiment of the present application;
Description of the drawings: a first wafer 100, a first support layer 101, a via 102, a metal pad 103; a second wafer 200, a first through silicon via 201, a silicon dioxide insulating layer 202, a filled through silicon via 203, a second support layer 204, a metal pad 205 embedded in the second support layer, a third support layer 206, a metal pad 207 embedded in the third support layer; a last bonded wafer 300, a silicon dioxide layer 301, and a filled second through silicon via 302.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings in the embodiments of the present application. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.
With the rapid development of technologies such as artificial intelligence AI, autopilot, and 5G networks, the demand for computing power in various fields has increased dramatically. AI is rapidly inducing revolution in various industries, and a strong chip computing power is a foundation for promoting AI development. However, the nano-fabrication process of integrated circuits has approached physical limits, and it has become increasingly difficult to increase the power of the chip by shrinking the transistor size. At this time, the importance of using heterogeneous integration of core particles (Chiplet) to extend and expand moore's law is increasingly highlighted, and integrated circuits are being developed from two-dimensional integration to three-dimensional integration. Through Silicon Vias (TSVs) are becoming increasingly important as a key technology for three-dimensional integration to enable shortest signal connections between multiple layers of stacks.
For example, by integrating a Graphics Processor (GPU) and a high-end graphics card AI chip of a high-bandwidth memory (HBM) by adopting a 2.5D/3D TSV technology, the near-memory calculation of the ultra-high bandwidth is realized, the bottleneck of a memory wall is broken through, and strong calculation power support is provided for AI model training. With the shrinking size of transistors and the increasing number of stacked layers, signal lines and power lines are mixed in multi-layer wiring, and circuit designs are increasingly complex, and how to deal with resource conflicts between signal networks and power supply networks becomes a key challenge for further miniaturization of chips. The conventional power supply lines are arranged on the front side of the chip, the wiring mode of the front side power supply network (FSPDN) can influence the allocation of metal layer resources, and the technology of the back side power supply network (BSPDN) can solve the design difficulty.
The related art proposes a scheme of transferring the power supply network from the transistor side to the back side rearrangement. Compared with the traditional power supply technology, the back power supply technology can remarkably improve the performance and energy efficiency of the chip, and meanwhile reduces the power consumption and the area. Implementation of this backside power technology relies on nanoscale TSVs to guide native FSPDN through an ultra-thin silicon substrate to the chip backside.
With the continuous shrinking of three-dimensional integrated circuit dimensions and the continuous enhancement of functions, the TSV technology will continue to play an important role in the future, and the TSV technology is expected to be widely applied in the next-generation chip design to achieve higher integration level, faster data transmission speed and lower power consumption. Meanwhile, along with the progress of material science and nano technology, the TSV technology is expected to further evolve, new materials and manufacturing processes are introduced, and the application of the TSV technology in the field of integrated circuits is expanded. In a word, the continuous development of micro-nano TSV technology will continuously push the integrated circuit technology to advance, so as to provide firm computational support for the development of an intelligent society and lay a foundation for future technological innovation. However, current TSV technology lacks systematic three-dimensional integrated structures and corresponding process designs for sub-micron through silicon vias.
In view of the above problems, embodiments of the present application provide a three-dimensional integration method and a three-dimensional integration structure based on submicron through silicon vias, so as to implement a process design for submicron through silicon vias. The three-dimensional integration method based on the submicron through silicon vias provided by the embodiment of the application is described in detail below through some embodiments and application scenes thereof with reference to the accompanying drawings.
The first aspect of the embodiment of the present application provides a three-dimensional integration method based on a submicron through silicon via, referring to fig. 1, fig. 1 is a step flowchart of the three-dimensional integration method based on a submicron through silicon via, as shown in fig. 1, where the method includes:
Step S101, processing a first surface of a first wafer to obtain a processed first wafer, where the first surface is a surface to be bonded of the first wafer, and the first surface of the processed first wafer is a bonding hierarchical structure, and the bonding hierarchical structure includes: a first support layer, and a plurality of metal pads embedded in the first support layer; the surface of the first wafer, which is away from the first surface, is interconnected with the first substrate.
In this embodiment, the first wafer may be a bare silicon wafer, or may be first interconnected with the substrate through a certain process (i.e., a surface of the first wafer facing away from the first surface may be interconnected with the first substrate), and step S101 may be performed on an actual chip having a specific function or device layer, such as a computing chip/logic chip, etc. Referring to fig. 2, fig. 2 shows a schematic structural diagram of a processed first wafer formed in a three-dimensional integration method, and as shown in fig. 2, a bonding hierarchy structure is prepared on a first surface of the first wafer 100, where the bonding hierarchy structure includes: a first support layer 101, and a plurality of metal pads 103 embedded in the first support layer 101. The metal pad 103 has the same height as the thickness of the first support layer 101.
The following is a detailed description of the processing process of the first wafer with respect to steps S201-S205.
In one possible implementation manner, the step S101 is performed on the first surface of the first wafer to obtain a processed first wafer, and includes:
in step S201, a first support layer made of silicon dioxide is prepared on the first surface by thermal oxidation or chemical vapor deposition CVD.
Referring to fig. 3, fig. 3 shows a schematic structural diagram of a first support layer and a through hole formed in a three-dimensional integration method, and as shown in fig. 3 (a), a first support layer 101 is prepared on a first surface of a first wafer 100 by thermal oxidation or chemical vapor deposition CVD, so that a thickness of the first support layer 101 is formed to be a height of a metal pad, which is a height set in advance for the metal pad. In one possible embodiment, the first support layer has a thickness of 1um to 5um (e.g., 1um, 3um, 5um, etc.). In this embodiment, the material of the first support layer may be silicon dioxide.
Step S202, preparing a plurality of through holes in the first supporting layer by etching.
In a possible implementation manner, the step S202 of preparing a plurality of through holes in the first supporting layer by etching includes:
In step S2021, a rewiring RDL image and a chip wiring contact position PAD are defined on the surface of the first supporting layer by photolithography.
Specifically, a pattern (including a rewiring RDL image and a chip wire bond PAD location PAD) is defined on the surface of the first support layer (the side facing away from the first surface) by a photoresist. The position of the pattern corresponds to the position of the subsequent through hole to be filled, i.e. the position of the metal pad.
And step S2022, performing plasma etching on the first supporting layer according to the RDL image and the PAD until the first surface is exposed, so as to obtain a plurality of through holes.
Specifically, as shown in fig. 3 (b), the first support layer 101 is subjected to plasma etching according to a defined pattern (the RDL image and the PAD) until the bottom (the first surface) of the first support layer is exposed, so as to obtain a plurality of through holes 102, so that the height of the through holes 102 is the same as the thickness of the first support layer 101.
In step S203, a seed layer is deposited on the surface of the first support layer by means of magnetron sputtering.
And S204, filling metal copper into the through hole in an electroplating manner until the metal copper completely fills the through hole, so as to obtain a plurality of metal gaskets embedded in the first supporting layer.
The seed layer is made of metallic copper, and the metallic copper matched with the seed layer is filled on the seed layer in an electroplating manner, so that the metallic material of the seed layer and the electroplated filled metallic material are combined until the metallic copper completely fills the through hole, and the metallic liner 103 is obtained.
In step S205, by means of chemical mechanical polishing CMP, the redundant metal material on the surface of the first support layer facing away from the first surface is removed, so that the surface of the first support layer is leveled, and the bonding hierarchical structure is obtained.
Further, in order to ensure that the metal copper completely fills the through hole, the electroplated metal copper slightly exceeds the surface of the first supporting layer, so that the surface of the first supporting layer on the side facing away from the first surface needs to be ground and polished in step S205, so that the surface is smooth and the superfluous metal material (including superfluous seed layer and electroplated metal copper) on the surface is removed, and a bonding hierarchical structure is obtained.
The following steps S102 to S105 are used to specifically describe the processing process of the second wafer, so as to obtain the processed second wafer. Wherein the second wafer is a bare silicon wafer of the same size as the first wafer. It should be noted that, there is no sequence between step S101 and steps S102-S105, that is, the first wafer may be processed (step S101 is executed), the second wafer may be processed (step S102-S105 is executed), the first wafer may be processed (step S101 is executed), or the first wafer and the second wafer may be processed simultaneously (step S101 is executed, and steps S102-S105 are executed simultaneously).
Step S102, a second surface of a second wafer is a surface to be bonded, and a plurality of first through silicon vias are prepared on the second surface by etching; the aperture of the first through silicon via is smaller than 1 micron.
Specifically, referring to fig. 4, fig. 4 is a schematic diagram illustrating a second wafer processing procedure in a three-dimensional integration method, and as shown in fig. 4 (a), a pattern (i.e., a position of a through silicon via TSV, and a cross-sectional shape) is defined on a second surface of the second wafer 200 by photolithography. Then, the second surface of the second wafer 200 is etched according to the defined pattern until reaching the preset TSV height, to obtain a plurality of first through silicon vias 201.
And step S103, depositing a silicon dioxide insulating layer on the second surface.
As shown in fig. 4 (b), a silicon dioxide insulating layer 202 is deposited over the first through-silicon-via TSV structure (including the bottom and sidewalls of the through-silicon via) and the second surface of the second wafer. In one possible embodiment, the thickness of the silicon dioxide insulating layer is less than or equal to 50nm (e.g., 40nm, 30nm, etc.).
Step S104, filling a first metal material into the first through holes by physical vapor deposition PVD, atomic layer deposition ALD or electroplating to obtain a plurality of filled through holes.
Specifically, the first metal material is filled into the first through-silicon via by any one of the methods, and in this step, since the silicon dioxide insulating layer is deposited in advance in step S103, the first metal material is filled on the silicon dioxide insulating layer until the first metal material completely fills the first through-silicon via. In order to ensure that the first metal material completely fills the first through silicon vias, the filled first metal material slightly exceeds the surface of the silicon dioxide insulating layer 102, and the redundant first metal material on the silicon dioxide insulating layer 102 can be removed by grinding and polishing to make the surface flat, as shown in fig. 4 (c), so as to obtain a plurality of filled through silicon vias 203, namely, a sub-micron scale through silicon via structure which is prepared preliminarily.
In addition, in the case of filling the first through-silicon via with the first metal material by selective electroplating, it is necessary to deposit a seed layer on the surface of the silicon oxide insulating layer by magnetron sputtering. Then, the first metal material matched with the seed layer is filled on the seed layer in an electroplating manner, so that the metal material of the seed layer is combined with the first metal material filled by electroplating, and the filled through silicon vias 203 are obtained.
And step S105, preparing the bonding hierarchical structure on the surface of the silicon dioxide insulating layer, which is away from the second surface, so as to obtain the processed second wafer.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a processed second wafer formed in a three-dimensional integration method, and as shown in fig. 5, a bonding hierarchy of the second wafer is prepared on a silicon dioxide insulating layer, the bonding hierarchy 204 of the second wafer is the same as the bonding hierarchy of the first wafer, and the bonding hierarchy includes: a second support layer 204, and a plurality of metal pads 205 embedded in the second support layer 204. The height of the metal pad 205 embedded in the second support layer is the same as the thickness of the second support layer 204. It should be noted that the post-processing second wafer obtained in the actual preparation is an integrated structure, and the lines between the bonding hierarchical structure of the second wafer and the silicon oxide insulating layer in fig. 5 are used to represent the hierarchical structure of the post-processing second wafer, and do not represent any detachable meaning. In this step, in the bonding hierarchical structure of the second wafer, the material of the second support layer 204 is silicon dioxide, and the metal material of the metal pad 205 embedded in the second support layer is the same as the first metal material filled in the filled through-silicon via, so that the metal pad can be combined with the first through-silicon via.
As can be seen from fig. 5, in preparing the bonding hierarchy on the silicon dioxide insulating layer, the positions of the plurality of metal pads 205 embedded in the second support layer in the bonding hierarchy should correspond to the positions of the filled through silicon vias 203, so that the metal pads 205 may cover one or more of the filled through silicon vias 203, and thus the filled through silicon vias 203 may be combined with the metal pads 205. Specifically, the position of the through silicon via after filling and the position of the metal pad need to be determined according to the actual application situation, and are not specifically limited in this embodiment.
In practice, referring to steps S201-S205 (the process of processing the first wafer), a bonding hierarchy of the same structure is prepared on the second wafer. The specific implementation method is as follows:
In step S301, a second supporting layer made of silicon dioxide is prepared on the surface of the silicon dioxide insulating layer facing away from the second surface by thermal oxidation or chemical vapor deposition CVD. The thickness of the second support layer is made to be the height of the metal pad, namely, the height preset for the metal pad. In one possible embodiment, the thickness of the second support layer is 1um to 5um.
Step S302, preparing a plurality of through holes in the second supporting layer by etching. Specifically, the rewiring RDL image and the chip line contact PAD position PAD can be defined on the surface of the second support layer by means of photolithography. And carrying out plasma etching on the second supporting layer according to the RDL image and the PAD until the bottom (silicon dioxide insulating layer) of the second supporting layer is exposed, so as to obtain a plurality of through holes.
In step S303, a seed layer is deposited on the surface of the second support layer by means of magnetron sputtering.
And step S304, filling metal copper into the through holes in an electroplating manner until the metal copper completely fills the through holes, so as to obtain a plurality of metal gaskets embedded into the second supporting layer. Specifically, the seed layer is made of metallic copper, and the metallic copper matched with the seed layer is filled on the seed layer in an electroplating manner, so that the metallic material of the seed layer and the electroplated filled metallic material are combined until the metallic copper completely fills the through hole, and the metallic liner is obtained.
In step S305, the redundant metal material on the surface of the second support layer facing away from the second surface is removed by chemical mechanical polishing CMP, so that the surface of the second support layer is leveled, and a bonding hierarchical structure is obtained. Specifically, in order to ensure that the metal copper completely fills the through hole, the electroplated metal copper slightly exceeds the surface of the second supporting layer, so that the surface of the second supporting layer on the side away from the second surface needs to be ground and polished, so that the surface is smooth and superfluous metal materials (including superfluous seed layers and electroplated metal copper) on the surface are removed, and a bonding hierarchical structure is obtained.
And step S106, the processed first wafer and the processed second wafer are bonded in a mixed mode, and the processed second wafer is thinned to 10 times of the aperture of the filled through silicon via.
In a possible implementation manner, the step S106 of hybrid bonding the processed first wafer and the processed second wafer, thinning the processed second wafer to 10 times the aperture of the filled through silicon via, includes:
step S1061, aligning the metal pad embedded in the bonding hierarchy of the processed first wafer with the metal pad embedded in the bonding hierarchy of the processed second wafer, and bonding the processed first wafer and the processed second wafer.
Referring to fig. 6, fig. 6 shows a schematic diagram of a bonding structure of a processed first wafer and a processed second wafer, and as shown in fig. 6, the processed first wafer and the processed second wafer are bonded in a mixed manner, wherein a metal pad 103 embedded in a bonding hierarchical structure of the processed first wafer and a metal pad 205 embedded in a bonding hierarchical structure of the processed second wafer belong to a one-to-one correspondence, so that bonding of the two wafers can be achieved by aligning the two.
And step S1062, thinning the surface of the processed second wafer away from the second surface by using a multi-step thinning method to 10 times of the aperture of the filled through silicon via, where the first metal material is tungsten, copper or cobalt.
Specifically, as shown in fig. 7, fig. 7 shows a schematic diagram of a thinned structure formed in a three-dimensional integration method, and as shown in fig. 7, the thinned second wafer is thinned to obtain a thinned hierarchical structure. As shown in fig. 7, the thinned hierarchical structure includes: a wafer support layer (e.g., the second wafer 200 shown in fig. 7), and a plurality of post-fill through-silicon vias embedded in the wafer support layer. The thickness of the wafer supporting layer, i.e. the thinned silicon wafer 200, is 10 times the aperture of the TSV to be fabricated (if 300nm aperture TSV is required, the thickness of the remaining silicon layer after thinning is 3 um). The thinning process typically employs a multi-step thinning process (mechanical thinning-CMP-dry etching) to achieve the desired silicon layer thickness. As shown in fig. 7, the filled through silicon via structure is a metal pillar with a pore size of less than 1 micron, the sidewall of the metal pillar is wrapped by a silicon dioxide layer, and one end of the filled through silicon via is combined with a metal pad embedded in the bonding hierarchy.
Step S107, sequentially bonding one or more third wafers on the surface of the processed second wafer facing away from the second surface, where the structure of the third wafer is the same as the structure of the processed first wafer or the processed second wafer.
In a possible implementation manner, the step S107, after the processing, sequentially bonds one or more third wafers on a surface of the second wafer facing away from the second surface, including:
And step S1071, taking the surface of the processed second wafer away from the second surface as a third surface, and preparing the bonding hierarchical structure on the third surface.
Specifically, in order to continue bonding other wafers on the second wafer, it is further required to prepare a bonding hierarchy on a side surface of the second wafer facing away from the second surface after processing, referring to fig. 8, fig. 8 shows a bonding hierarchy of a third surface formed in a three-dimensional integration method, and as shown in fig. 8, the bonding hierarchy includes: a third support layer 206, and a plurality of metal pads 207 embedded in the third support layer 206. The metal pad 207 has the same height as the thickness of the third support layer 206.
In particular implementations, referring to steps S201-S205 (processing of the first wafer), a bonding hierarchy of the same structure is prepared on a side surface of the second wafer facing away from the second surface. The specific implementation method is as follows:
In step S401, a third supporting layer made of silicon dioxide is prepared on the surface of the second wafer facing away from the second surface (i.e., the third surface) after the processing by thermal oxidation or chemical vapor deposition CVD. The thickness of the third support layer is made to be the height of the metal pad, which is the height set in advance for the metal pad. In one possible embodiment, the thickness of the third support layer is 1um to 5um.
Step S402, preparing a plurality of through holes in the third supporting layer by etching. Specifically, the rewiring RDL image and the chip line contact PAD position PAD may be defined on the surface of the third support layer by photolithography. And carrying out plasma etching on the third supporting layer according to the RDL image and the PAD until the bottom (silicon dioxide insulating layer) of the third supporting layer is exposed, so as to obtain a plurality of through holes.
In step S403, a seed layer is deposited on the surface of the third support layer by means of magnetron sputtering.
And step S404, filling metal copper into the through holes in an electroplating manner until the metal copper completely fills the through holes, so as to obtain a plurality of metal gaskets embedded into the third supporting layer. Specifically, the seed layer is made of metallic copper, and the metallic copper matched with the seed layer is filled on the seed layer in an electroplating manner, so that the metallic material of the seed layer and the electroplated filled metallic material are combined until the metallic copper completely fills the through hole, and the metallic liner is obtained.
In step S405, the redundant metal material on the surface of the third support layer facing away from the third surface is removed by chemical mechanical polishing CMP, so that the surface of the third support layer is leveled, and a bonding hierarchical structure is obtained. Specifically, in order to ensure that the metal copper completely fills the through hole, the electroplated metal copper slightly exceeds the surface of the third supporting layer, so that the surface of one side, facing away from the third surface, of the third supporting layer needs to be ground and polished, so that the surface is smooth, and redundant metal materials (including redundant seed layers and electroplated metal copper) on the surface are removed, thereby obtaining a bonding hierarchical structure.
Step S1072, sequentially bonding one or more third wafers on the surface of the bonding hierarchy on the third surface.
In a possible embodiment, in the case that the third wafer currently bonded is not the last wafer bonded, the structure of the third wafer currently bonded is the same as the structure of the second wafer after processing;
In the case that the third wafer currently bonded is the last wafer to be bonded, the structure of the third wafer currently bonded is the same as that of the first wafer after processing or the second wafer after processing.
In this embodiment, one or more wafers are continuously bonded on the third surface along the normal direction of the third surface, so as to form a multi-level structure. Specifically, if a plurality of third wafers are to be bonded, in this process, the structure of the third wafer used in the middle is the same as the structure of the second wafer after processing, so that the bonded three-dimensional integrated structure has a multi-level TSV structure, and the structure of the third wafer used in the last bonding may be the same as the structure of the second wafer after processing or the structure of the first wafer after processing.
In the case where the third wafer currently being bonded is not the last wafer being bonded, bonding is continued using the third wafer having the same structure as the processed second wafer. The processing process of the third wafer in this case is the same as the processing process of the second wafer after processing (steps S102-S105), and will not be described in detail in this embodiment. Accordingly, the specific method of bonding the third wafer is the same as the method of bonding the second wafer after processing to the first wafer after processing, as described below:
In one possible implementation, the step S1072 sequentially bonds one or more third wafers, including:
In step S501, a metal pad embedded in a bonding hierarchy structure of a surface of the uppermost wafer opposite to the bonding surface is aligned with a metal pad embedded in a bonding hierarchy structure of the third wafer, and the uppermost wafer and the third wafer are bonded.
Specifically, hybrid bonding is performed between every two wafers by using the bonding hierarchical structure of the outermost layer of each wafer. Since the third wafer has the same structure as the processed second wafer, the uppermost layer is a bonding hierarchical structure, and bonding is performed by using the bonding hierarchical structure of the third wafer. Referring to fig. 9, fig. 9 is a schematic diagram illustrating a process of bonding a third wafer formed in a three-dimensional integration method, and as shown in fig. 9 (a), a metal pad 207 embedded in a bonding hierarchy on a third surface is aligned with a metal pad embedded in the bonding hierarchy of the third wafer, and the two are in a one-to-one correspondence relationship, so that bonding of two wafers can be achieved by aligning the two.
And step S502, thinning the third wafer by adopting a multi-step thinning method to 10 times of the aperture of the filled through silicon via of the third wafer.
Specifically, as shown in fig. 9 (b), the side of the third wafer away from the bonding surface (i.e., the bonding hierarchical structure surface) is thinned, so as to obtain a thinned hierarchical structure. The thinned hierarchical structure comprises: a wafer support layer (third wafer), and a plurality of filled through silicon vias embedded in the wafer support layer. The thickness of the thinned silicon wafer is 10 times of the aperture of the TSV to be prepared (if the TSV with the aperture of 300nm is needed, the thickness of the residual silicon layer after thinning is 3 um). The thinning process typically employs a multi-step thinning process (mechanical thinning-CMP-dry etching) to achieve the desired silicon layer thickness. As shown in fig. 9 (b), the filled through silicon vias are metal pillars with a pore size of less than 1 micron, the sidewalls of the metal pillars are surrounded by a silicon dioxide layer, and one end of the filled through silicon vias is bonded to a metal pad embedded in the bond hierarchy.
In step S503, the bonding hierarchical structure is prepared on the surface of the third wafer facing away from the bonding surface.
Specifically, as shown in fig. 9 (c), in order to continue bonding a wafer on the uppermost wafer that has been bonded at present, it is also necessary to prepare a bonding hierarchy on the surface of the third wafer facing away from the bonding surface. In practice, referring to steps S201-S205 (the process of processing the first wafer), a bonding hierarchy of the same structure is prepared on the surface of the third wafer facing away from the bonding face. The specific implementation method is as follows:
In step S5031, a fourth support layer made of silicon dioxide is prepared on the surface of the third wafer facing away from the bonding surface by thermal oxidation or CVD. The thickness of the fourth support layer is made to be the height of the metal pad, which is the height set in advance for the metal pad. In one possible embodiment, the thickness of the fourth support layer is 1um to 5um.
Step S5032, preparing a plurality of through holes in the fourth supporting layer by etching. Specifically, the rewiring RDL image and the chip line contact PAD position PAD may be defined on the surface of the fourth supporting layer by photolithography. And carrying out plasma etching on the fourth supporting layer according to the RDL image and the PAD until the bottom (silicon dioxide insulating layer) of the fourth supporting layer is exposed, so as to obtain a plurality of through holes.
In step S5033, a seed layer is deposited on the surface of the fourth support layer by means of magnetron sputtering.
In step S5034, metal copper is filled into the through hole by electroplating until the metal copper completely fills the through hole, so as to obtain a plurality of metal pads embedded in the fourth supporting layer. Specifically, the seed layer is made of metallic copper, and the metallic copper matched with the seed layer is filled on the seed layer in an electroplating manner, so that the metallic material of the seed layer and the electroplated filled metallic material are combined until the metallic copper completely fills the through hole, and the metallic liner is obtained.
In step S5035, the redundant metal material on the surface of the fourth supporting layer is removed by chemical mechanical polishing CMP, so that the surface of the fourth supporting layer is leveled, and a bonding hierarchical structure is obtained. Specifically, in order to ensure that the metal copper completely fills the through hole, the metal copper after electroplating slightly exceeds the surface of the fourth supporting layer, so that the surface of the fourth supporting layer needs to be ground and polished to smooth the surface and remove the superfluous metal material (including superfluous seed layer and electroplated metal copper) on the surface, thereby obtaining a bonding hierarchical structure.
Step S504, repeating the above steps until the last third wafer is bonded.
In the case where the third wafer currently being bonded is the last wafer being bonded, bonding is continued using the third wafer having the same structure as the processed second wafer or the processed first wafer. Specifically, when the structure of the wafer is the same as that of the processed first wafer, the processing process of the wafer is the same as that of the processed first wafer (steps S201 to S205); when the structure of the wafer is the same as that of the processed second wafer, the processing process of the wafer is the same as that of the processed second wafer (steps S102-S105), and the description thereof is omitted in this embodiment.
Correspondingly, the bonding method comprises the following steps: and aligning the metal pad embedded in the bonding hierarchical structure of the surface of the uppermost wafer, which is away from the bonding surface, with the metal pad embedded in the bonding hierarchical structure of the last third wafer, and bonding the uppermost wafer and the last third wafer.
By repeatedly executing the steps S501 to S504, a multi-level hybrid bonding structure is prepared, where the hybrid bonding structure includes: a layer of bonded hierarchy and a layer of thinned hierarchy. Specifically, as shown in fig. 9 (c), multiple layers of hybrid bonding structures are sequentially bonded on the first wafer after processing (i.e., above the bonding hierarchy of the first wafer). The bonding hierarchy includes: a support layer made of silicon dioxide and a plurality of metal pads embedded in the support layer. The thinned hierarchical structure comprises: the wafer support layer and the plurality of filled through silicon vias embedded in the wafer support layer. As shown in fig. 9 (c), along the normal direction of the first surface of the first wafer, the bonding hierarchy, the hybrid bonding structure, … …, the hybrid bonding structure, the bonding hierarchy, and the last wafer are sequentially arranged. That is, the first wafer, the bonding hierarchy, the post-thinning hierarchy … … bonding hierarchy, and the last wafer are sequentially arranged along the normal direction of the first surface of the first wafer. And the two ends of the filled through silicon vias embedded in the thinned hierarchical structure are respectively combined with the metal pads embedded in the bonding hierarchical structure.
Step S1073, preparing a plurality of second through silicon vias filled with a second metal material on the surface of the wafer, which is bonded for the last time and is away from the bonding surface, so that the surface and the second substrate are interconnected to obtain the three-dimensional integrated structure.
In a specific implementation, a plurality of second through silicon vias are prepared by etching on the surface of the last bonded wafer facing away from the bonding face. In one possible embodiment, the second through silicon via has an aperture diameter greater than 10um (e.g., 11um, 15um, etc.). Specifically, referring to fig. 10, fig. 10 is a schematic diagram illustrating a structure of a wafer bonded last time in a three-dimensional integration method, taking the same structure as a processed second wafer as an example, as shown in fig. 10, a pattern (i.e. a position of a through silicon via TSV) is defined on a surface of the wafer bonded last time by photolithography. And then etching the surface of the third wafer according to the defined pattern until reaching the preset TSV height to obtain a plurality of second through silicon vias.
Then, a silicon dioxide layer is deposited on the surface of the last bonded wafer. As shown in fig. 10, a silicon dioxide layer 301 is deposited over the second through-silicon via TSV structure (including the bottom and sidewalls of the through-silicon via) and the surface of the wafer 300. In one possible embodiment, the thickness of the silicon dioxide layer is less than or equal to 50nm.
And finally, filling a second metal material into the second through holes by physical vapor deposition PVD, atomic layer deposition ALD or electroplating to obtain a plurality of filled second through holes. The second metal material is tungsten, copper or cobalt, and the second metal material needs to be the same as the first metal material.
Specifically, the second metal material is filled into the second through silicon via in any mode, and in this step, since the silicon dioxide layer is deposited in advance, the second metal material is filled on the silicon dioxide layer until the second metal material completely fills the second through silicon via. In order to ensure that the second metal material completely fills the second through silicon vias, the second metal material after filling slightly exceeds the surface of the silicon dioxide layer 301, and the superfluous second metal material on the silicon dioxide layer 301 can be removed by grinding and polishing to make the surface flat, as shown in fig. 10, so as to obtain a plurality of filled second through silicon vias 302.
In addition, in the case of filling the second through-silicon via with the second metal material by selective electroplating, it is necessary to deposit a seed layer on the surface of the silicon dioxide layer by magnetron sputtering. And filling a second metal material matched with the seed layer on the seed layer in an electroplating manner, so that the metal material of the seed layer is combined with the second metal material filled by electroplating, and the filled second through silicon vias 302 are obtained.
According to the three-dimensional integration method provided by the application, the submicron-level TSV is prepared by etching the first through silicon via with the aperture smaller than 1 micron on the second wafer and filling the first metal material in the first through silicon via. And then, wafer hybrid bonding is realized through bonding hierarchical structures on the first wafer and the second wafer, and one or more third wafers (a multi-level TSV structure is generated) are sequentially bonded to obtain a three-dimensional integrated structure (as shown in fig. 9 (c), a multi-layer thinned hierarchical structure and a bonding hierarchical structure are sequentially bonded on the processed first wafer, wherein two ends of a filled through silicon via embedded in the thinned hierarchical structure are respectively combined with metal pads embedded in bonding hierarchical structures of an upper layer and a lower layer), so that a three-dimensional integrated process based on submicron through silicon vias is realized.
The second aspect of the embodiment of the application also provides a three-dimensional integrated structure based on the submicron through silicon vias, which is prepared by the three-dimensional integrated method based on the submicron through silicon vias in the first aspect.
Referring to fig. 11, fig. 11 shows a schematic three-dimensional integrated structure based on submicron through-silicon vias, as shown in fig. 11, after the first wafer is bonded to the second wafer after processing, three third wafers are sequentially bonded on the third surface, and the structure of the third wafer (i.e., the 3 rd third wafer) used in the last bonding is the same as that of the second wafer after processing.
Referring to fig. 12, fig. 12 shows another schematic three-dimensional integrated structure based on submicron through-silicon vias, as shown in fig. 12, after the first wafer is bonded to the second wafer after processing, two third wafers are sequentially bonded on the third surface, and the structure of the third wafer (i.e., the 2 nd third wafer) used in the last bonding is the same as that of the first wafer after processing.
Through the three-dimensional integration method provided in the first aspect, a multi-level hybrid bonding structure is prepared, wherein the hybrid bonding structure comprises: a layer of bonded hierarchy and a layer of thinned hierarchy. And preparing a layer of mixed bonding structure after each bonding of a third wafer. Specifically, as shown in fig. 11, multiple layers of hybrid bonding structures are sequentially bonded to the first wafer after processing (i.e., above the bonding hierarchy of the first wafer). The bonding hierarchy includes: a support layer made of silicon dioxide and a plurality of metal pads embedded in the support layer. The thinned hierarchical structure comprises: the wafer support layer and the plurality of filled through silicon vias embedded in the wafer support layer. As shown in fig. 11, along the normal direction of the first surface of the first wafer, the bonding hierarchy, the hybrid bonding structure, … …, the hybrid bonding structure, the bonding hierarchy, and the last wafer are sequentially arranged. That is, the first wafer, the bonding hierarchy, the post-thinning hierarchy … … bonding hierarchy, and the last wafer are sequentially arranged along the normal direction of the first surface of the first wafer. And the two ends of the filled through silicon vias embedded in the thinned hierarchical structure are respectively combined with the metal pads embedded in the bonding hierarchical structure.
A third aspect of the embodiments of the present application provides a three-dimensional integration apparatus based on submicron through-silicon vias, for performing the steps in the three-dimensional integration method provided in the first aspect, the apparatus comprising:
The first wafer processing module is used for processing a first surface of a first wafer to obtain a processed first wafer, the first surface is a surface to be bonded of the first wafer, the first surface of the processed first wafer is a bonding hierarchical structure, and the bonding hierarchical structure comprises: a first support layer, and a plurality of metal pads embedded in the first support layer; the surface of the first wafer, which is away from the first surface, is interconnected with a first substrate;
a second wafer first processing module for preparing a plurality of first through silicon vias by etching on the second surface; the second surface of the second wafer is a surface to be bonded, and the aperture of the first through silicon via is smaller than 1 micron;
A second wafer second processing module for depositing a silicon dioxide insulating layer on the second surface;
The second wafer third processing module is used for filling a first metal material into the first through-silicon-via through Physical Vapor Deposition (PVD), atomic Layer Deposition (ALD) or electroplating to obtain a plurality of filled through-silicon-vias;
A fourth processing module of the second wafer, configured to prepare the bonding hierarchical structure on a surface of the silicon dioxide insulating layer facing away from the second surface, so as to obtain a processed second wafer;
The first bonding module is used for hybrid bonding the processed first wafer and the processed second wafer, and thinning the processed second wafer to 10 times of the aperture of the filled through silicon via;
and the second bonding module is used for sequentially bonding one or more third wafers on the surface of the processed second wafer, which is away from the second surface, so as to obtain a three-dimensional integrated structure, wherein the structure of the third wafer is the same as that of the processed first wafer or the processed second wafer.
In one possible implementation manner, the first wafer processing module is configured to perform the following steps:
Preparing a first supporting layer which takes silicon dioxide as a material on the first surface by means of thermal oxidation or Chemical Vapor Deposition (CVD);
Preparing a plurality of through holes in the first supporting layer by etching;
depositing a seed layer on the surface of the first supporting layer in a magnetron sputtering mode;
filling metal copper into the through hole in an electroplating manner until the metal copper completely fills the through hole to obtain a plurality of metal gaskets embedded into the first supporting layer;
and removing redundant metal materials on the surface of the first supporting layer, which is away from the first surface, in a Chemical Mechanical Polishing (CMP) mode, so that the surface of the first supporting layer is flat, and the bonding hierarchical structure is obtained.
In one possible embodiment, the preparing a plurality of through holes in the first supporting layer by etching includes:
defining a rewiring RDL image and a chip circuit contact point position PAD on the surface of the first supporting layer in a photoetching mode;
and carrying out plasma etching on the first supporting layer according to the RDL image and the PAD until the first surface is exposed, so as to obtain a plurality of through holes.
In one possible embodiment, the first bonding block includes:
A hybrid bonding sub-module, configured to align a metal pad embedded in a bonding hierarchy of the processed first wafer with a metal pad embedded in a bonding hierarchy of the processed second wafer, and bond the processed first wafer and the processed second wafer;
and the thinning submodule is used for thinning the surface of the treated second wafer, which is away from the second surface, by adopting a multi-step thinning method to 10 times of the aperture of the filled silicon through hole, and the first metal material is tungsten, copper or cobalt.
In one possible embodiment, the second bonding module includes:
a first bonding sub-module, configured to take a surface of the processed second wafer facing away from the second surface as a third surface, and prepare the bonding hierarchical structure on the third surface;
a second bonding sub-module for sequentially bonding one or more third wafers on the surface of the bonding hierarchy on the third surface;
and the third bonding submodule is used for preparing a plurality of second silicon through holes filled with a second metal material on the surface of the wafer which is bonded for the last time and is away from the bonding surface, so that the surface and the second substrate are interconnected to obtain the three-dimensional integrated structure.
In a possible embodiment, in the case that the third wafer currently bonded is not the last wafer bonded, the structure of the third wafer currently bonded is the same as the structure of the second wafer after processing;
In the case that the third wafer currently bonded is the last wafer to be bonded, the structure of the third wafer currently bonded is the same as that of the first wafer after processing or the second wafer after processing.
In a possible embodiment, the second bonding submodule is configured to perform the following steps:
aligning a metal pad embedded in a bonding hierarchical structure of the surface of the back of the uppermost wafer away from the bonding surface with the metal pad embedded in the bonding hierarchical structure of the third wafer, and bonding the uppermost wafer and the third wafer; thinning the third wafer by adopting a multi-step thinning method to 10 times of the aperture of the filled through silicon via of the third wafer;
Preparing the bonding hierarchical structure on the surface of the third wafer, which is away from the bonding surface;
The above steps are repeated until the last third wafer is bonded.
In one possible embodiment, the thickness of the silicon dioxide insulating layer is less than or equal to 50nm; the thickness of the first supporting layer is 1 um-5 um.
In one possible embodiment, the second through silicon via has an aperture diameter greater than 10um.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus, electronic devices, and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device that comprises the element.
The three-dimensional integration method and three-dimensional integration structure based on submicron through silicon vias provided by the application are described in detail, and specific examples are applied to illustrate the principles and the implementation modes of the application, and the description of the above examples is only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims (10)

1. A three-dimensional integration method based on submicron through silicon vias, the method comprising:
Processing a first surface of a first wafer to obtain a processed first wafer, wherein the first surface is a surface to be bonded of the first wafer, the first surface of the processed first wafer is a bonding hierarchical structure, and the bonding hierarchical structure comprises: a first support layer, and a plurality of metal pads embedded in the first support layer; the surface of the first wafer, which is away from the first surface, is interconnected with a first substrate;
The second surface of the second wafer is a surface to be bonded, and a plurality of first through silicon vias are prepared on the second surface by etching; the aperture of the first through silicon via is smaller than 1 micron;
Depositing a silicon dioxide insulating layer on the second surface;
Filling a first metal material into the first through silicon vias by Physical Vapor Deposition (PVD), atomic Layer Deposition (ALD) or electroplating to obtain a plurality of filled through silicon vias;
Preparing the bonding hierarchical structure on the surface of the silicon dioxide insulating layer, which is away from the second surface, so as to obtain a second wafer after treatment;
Mixing and bonding the processed first wafer and the processed second wafer, and thinning the processed second wafer to 10 times of the aperture of the filled through silicon via;
and sequentially bonding one or more third wafers on the surface of the processed second wafer, which is away from the second surface, to obtain a three-dimensional integrated structure, wherein the structure of the third wafer is the same as that of the processed first wafer or the processed second wafer.
2. The three-dimensional integration method based on submicron through silicon vias according to claim 1, wherein the processing the first surface of the first wafer to obtain a processed first wafer comprises:
Preparing a first supporting layer which takes silicon dioxide as a material on the first surface by means of thermal oxidation or Chemical Vapor Deposition (CVD);
Preparing a plurality of through holes in the first supporting layer by etching;
depositing a seed layer on the surface of the first supporting layer in a magnetron sputtering mode;
filling metal copper into the through hole in an electroplating manner until the metal copper completely fills the through hole to obtain a plurality of metal gaskets embedded into the first supporting layer;
and removing redundant metal materials on the surface of the first supporting layer, which is away from the first surface, in a Chemical Mechanical Polishing (CMP) mode, so that the surface of the first supporting layer is flat, and the bonding hierarchical structure is obtained.
3. The three-dimensional integration method based on submicron through-silicon vias according to claim 2, characterized in that said preparing a plurality of through-holes by etching in said first support layer comprises:
defining a rewiring RDL image and a chip circuit contact point position PAD on the surface of the first supporting layer in a photoetching mode;
and carrying out plasma etching on the first supporting layer according to the RDL image and the PAD until the first surface is exposed, so as to obtain a plurality of through holes.
4. The submicron through-silicon via-based three-dimensional integration method according to claim 1, wherein the hybrid bonding of the processed first wafer and the processed second wafer, thinning the processed second wafer to 10 times the aperture of the filled through-silicon via, comprises:
aligning the metal pad embedded in the bonding hierarchical structure of the processed first wafer with the metal pad embedded in the bonding hierarchical structure of the processed second wafer, and bonding the processed first wafer and the processed second wafer;
And thinning the surface of the treated second wafer, which is away from the second surface, by adopting a multi-step thinning method to 10 times of the aperture of the filled through silicon via, wherein the first metal material is tungsten, copper or cobalt.
5. The three-dimensional integration method based on submicron through-silicon vias according to claim 1, wherein said bonding one or more third wafers in sequence after said processing of the surface of the second wafer facing away from the second surface comprises:
taking the surface of the processed second wafer, which is away from the second surface, as a third surface, and preparing the bonding hierarchical structure on the third surface;
sequentially bonding one or more third wafers on a surface of the bonding hierarchy on the third surface;
And preparing a plurality of second through silicon vias filled with a second metal material on the surface of the wafer which is bonded for the last time and is away from the bonding surface, and interconnecting the surface and the second substrate to obtain the three-dimensional integrated structure.
6. The three-dimensional integration method according to claim 5, wherein in case that the third wafer currently bonded is not the last wafer bonded, the structure of the third wafer currently bonded is the same as the structure of the processed second wafer;
In the case that the third wafer currently bonded is the last wafer to be bonded, the structure of the third wafer currently bonded is the same as that of the first wafer after processing or the second wafer after processing.
7. The sub-micron through silicon via based three-dimensional integration method according to claim 6, wherein the sequentially bonding one or more third wafers comprises:
aligning a metal pad embedded in a bonding hierarchical structure of the surface of the back of the uppermost wafer away from the bonding surface with the metal pad embedded in the bonding hierarchical structure of the third wafer, and bonding the uppermost wafer and the third wafer; thinning the third wafer by adopting a multi-step thinning method to 10 times of the aperture of the filled through silicon via of the third wafer;
Preparing the bonding hierarchical structure on the surface of the third wafer, which is away from the bonding surface;
The above steps are repeated until the last third wafer is bonded.
8. The three-dimensional integration method based on sub-micron through silicon vias according to claim 1, wherein the thickness of the silicon dioxide insulating layer is less than or equal to 50nm; the thickness of the first supporting layer is 1 um-5 um.
9. The submicron through-silicon via-based three-dimensional integration method according to claim 5, wherein the diameter of the aperture of the second through-silicon via is larger than 10um.
10. A three-dimensional integrated structure based on submicron through-silicon vias, characterized in that it is prepared by the three-dimensional integrated method based on submicron through-silicon vias according to any one of claims 1 to 9.
CN202411092291.1A 2024-08-09 2024-08-09 Three-dimensional integration method and three-dimensional integration structure based on submicron through silicon vias Pending CN119008522A (en)

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