CN119002789A - IO sampling method and device and electronic equipment - Google Patents
IO sampling method and device and electronic equipment Download PDFInfo
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- CN119002789A CN119002789A CN202411175575.7A CN202411175575A CN119002789A CN 119002789 A CN119002789 A CN 119002789A CN 202411175575 A CN202411175575 A CN 202411175575A CN 119002789 A CN119002789 A CN 119002789A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
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Abstract
本公开提供IO采样方法和装置、电子设备。所述IO采样方法包括：接收IO输入信号；根据时钟周期信号对所述IO输入信号进行上升沿采样和下降沿采样以得到上升沿采样信号和下降沿采样信号；将所述上升沿采样信号和所述下降沿采样信号进行比较以得到比较结果；根据所述比较结果在已输出的上一次采样信号和当前采样信号中选择一个待输出信号，所述当前采样信号为所述上升沿采样信号或所述下降沿采样信号；以及将所述待输出信号输出作为与所述IO输入信号相对应的采样信号。本公开技术方案可以提升信号多毛刺和多抖动场景下的IO采样正确率。
The present disclosure provides an IO sampling method and device, and an electronic device. The IO sampling method includes: receiving an IO input signal; performing rising edge sampling and falling edge sampling on the IO input signal according to a clock cycle signal to obtain a rising edge sampling signal and a falling edge sampling signal; comparing the rising edge sampling signal and the falling edge sampling signal to obtain a comparison result; selecting a signal to be output from the last sampling signal output and the current sampling signal according to the comparison result, the current sampling signal being the rising edge sampling signal or the falling edge sampling signal; and outputting the signal to be output as a sampling signal corresponding to the IO input signal. The technical solution disclosed in the present disclosure can improve the accuracy of IO sampling in signal multi-burr and multi-jitter scenarios.
Description
Technical Field
The disclosure belongs to the technical field of integrated circuits, and relates to an IO sampling method and device and electronic equipment.
Background
In signal transmission, GPIO (General Purpose Input Output ) debounce and filtering are required for signal transmission accuracy. For example, in the scenes of industrial control application, there is often signal jitter caused by electromagnetic radiation and other factors, so that higher requirements are put on the functions of eliminating jitter and deburring of IO (Input/Output) of a chip. The debounce shown in fig. 1 is directed to the jitter of a mechanical key, for example, the low level goes high after the jitter, and the jitter can be restored to a stable value in a desired time. The filtering shown in fig. 2 aims at signal mutation and burr caused by electromagnetic radiation interference in industrial control application, and the mutation is unexpected, can occur at any time and can exist all the time.
For the jitter, the common circuit design can realize the jitter elimination of signal variation within one beat. However, this logic ignores the problem that the register has a metastable state, and when the glitch signal of the IO input happens to occur in the metastable state of the register, this glitch may be input to the input terminal of the GPIO. This may result in an IO erroneous pulse input. This problem is particularly pronounced in industrial control scenarios where the signal noise is large.
Disclosure of Invention
The disclosure provides an IO sampling method and device and electronic equipment, which are used for eliminating jitter and deburring of IO input signals so as to avoid error sampling of the IO input signals and filter the IO input signals.
In a first aspect, an embodiment of the present disclosure provides an IO sampling method. The IO sampling method comprises the following steps: receiving an IO input signal; performing rising edge sampling and falling edge sampling on the IO input signal according to the clock period signal to obtain a rising edge sampling signal and a falling edge sampling signal; comparing the rising edge sampling signal with the falling edge sampling signal to obtain a comparison result; selecting a signal to be output from the last sampling signal and the current sampling signal which are output according to the comparison result, wherein the current sampling signal is the rising edge sampling signal or the falling edge sampling signal; and outputting the signal to be output as a sampling signal corresponding to the IO input signal.
In one implementation manner of the first aspect, performing rising edge sampling and falling edge sampling on the IO input signal according to the clock period signal to obtain a rising edge sampling signal and a falling edge sampling signal includes: the IO input signal is sampled according to a rising edge and a falling edge of one clock cycle of the clock cycle signals or according to a falling edge of one clock cycle of the clock cycle signals and a rising edge of a next clock cycle to obtain the rising edge sampling signal and the falling edge sampling signal.
In one implementation manner of the first aspect, performing rising edge sampling and falling edge sampling on the IO input signal according to the clock period signal to obtain a rising edge sampling signal and a falling edge sampling signal includes: and carrying out rising edge sampling and falling edge sampling on the IO input signal according to the clock period signal, so that the rising edge sampling signal is different from the falling edge sampling signal when jitter or burr is contained in the IO input signal.
In one implementation manner of the first aspect, comparing the rising edge sampling signal and the falling edge sampling signal to obtain a comparison result includes: outputting a first comparison signal having a first level if the rising edge sampling signal is identical to the falling edge sampling signal; and outputting a second comparison signal having a second level opposite to the first level if the rising edge sampling signal is not identical to the falling edge sampling signal.
In an implementation manner of the first aspect, selecting one signal to be output from the output last sampled signal and the current sampled signal according to the comparison result includes: selecting the current sampling signal according to the first comparison signal in the current clock period in the clock period signals; and selecting the last sampled signal output according to the second comparison signal in the current clock cycle, wherein the last sampled signal output is output in the current clock cycle.
In an implementation manner of the first aspect, outputting the signal to be output as the sampling signal corresponding to the IO input signal includes: temporarily storing the selected signal to be output in the current clock period in the clock period signals; and outputting the signal to be output as the sampling signal at a next clock cycle of the clock cycle signals.
In one implementation manner of the first aspect, performing rising edge sampling and falling edge sampling on the IO input signal according to the clock period signal to obtain a rising edge sampling signal and a falling edge sampling signal includes: sampling the IO input signal according to the clock period signal by using a rising edge sampling D trigger to obtain a rising edge sampling signal; and sampling the IO input signal by using a D trigger of falling edge sampling according to the clock period signal to obtain the falling edge sampling signal.
In one implementation manner of the first aspect, comparing the rising edge sampling signal and the falling edge sampling signal to obtain a comparison result includes: and performing an exclusive nor operation on the rising edge sampling signal and the falling edge sampling signal.
In an implementation manner of the first aspect, the IO sampling method further includes: receiving a selection signal; and selecting one sampling signal from the rising edge sampling signal and the falling edge sampling signal according to the selection signal to serve as the current sampling signal.
In an implementation manner of the first aspect, the IO sampling method further includes: the clock period signal is down-converted or divided such that half of the clock period length is greater than the width of jitter or glitches contained in the IO input signal.
In a second aspect, embodiments of the present disclosure provide an IO sampling device. The IO sampling device includes: an input terminal configured to receive an IO input signal; a sampling circuit configured to perform rising edge sampling and falling edge sampling on the IO input signal according to a clock cycle signal to output a rising edge sampling signal and a falling edge sampling signal; an arithmetic circuit configured to compare the rising edge sampling signal and the falling edge sampling signal to output a comparison result; a signal selection circuit configured to select and output one signal to be output from the last sampled signal and the current sampled signal which are output according to the comparison result, wherein the current sampled signal is the rising edge sampled signal or the falling edge sampled signal; and an output circuit configured to output the signal to be output as a sampling signal corresponding to the IO input signal.
In one implementation manner of the second aspect, the sampling circuit includes: a first D flip-flop configured to receive the IO input signal and the clock cycle signal and sample the IO input signal according to a rising edge of the clock cycle signal to output the rising edge sampling signal; and a second D flip-flop configured to receive the IO input signal and the clock cycle signal and sample the IO input signal according to a falling edge of the clock cycle signal to output the falling edge sampling signal.
In one implementation manner of the second aspect, the operation circuit includes: an exclusive-or gate configured to receive the rising-edge sampling signal and the falling-edge sampling signal and exclusive-or the rising-edge sampling signal and the falling-edge sampling signal to output a first comparison signal having a first level or a second comparison signal having a second level opposite to the first level as the comparison result.
In one implementation manner of the second aspect, the signal selection circuit includes: a first selector configured to receive the comparison result, the current sampling signal, and the outputted last sampling signal, select and output the current sampling signal as the signal to be outputted when the comparison result is the first comparison signal, and select and output the outputted last sampling signal as the signal to be outputted when the comparison result is the second comparison signal.
In one implementation manner of the second aspect, the output circuit includes: and a register configured to receive the clock cycle signals and the signal to be output, temporarily store the signal to be output in a current clock cycle of the clock cycle signals, and output the signal to be output as the sampling signal in a next clock cycle of the clock cycle signals.
In an implementation manner of the second aspect, the IO sampling device further includes: and a second selector configured to receive a selection signal, the rising-edge sampling signal, and the falling-edge sampling signal, and select one sampling signal among the rising-edge sampling signal and the falling-edge sampling signal as the current sampling signal according to the selection signal.
In a third aspect, embodiments of the present disclosure provide an electronic device. The electronic device includes: the IO sampling device as described above; and at least one of a sensor interface, a communication interface, and a touch screen interface configured to receive the sampling signal from the IO sampling device.
According to the method and the device, IO sampling accuracy in a signal multi-burr and multi-jitter scene can be improved. After the first-stage sampling of the rising edge and the falling edge is carried out, signal burrs are filtered, and erroneous pulse judgment caused by the fact that the burrs are sampled is avoided. The signal of the select output is register sampled so that the signal of the second stage output does not generate metastables.
Drawings
Fig. 1 shows a first application scenario diagram of an IO sampling method according to an embodiment of the present disclosure.
Fig. 2 shows a second application scenario diagram of an IO sampling method according to an embodiment of the present disclosure.
Fig. 3 shows a flowchart of an IO sampling method according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of an IO sampling device according to an embodiment of the disclosure.
Fig. 5 shows a first schematic circuit diagram of an IO sampling device according to an embodiment of the disclosure.
Fig. 6 shows a second schematic circuit diagram of an IO sampling device according to an embodiment of the present disclosure.
Fig. 7 shows a signal timing diagram of an IO sampling device according to an embodiment of the disclosure.
Fig. 8 shows a third schematic circuit diagram of an IO sampling device according to an embodiment of the disclosure.
Fig. 9 shows a fourth schematic circuit diagram of an IO sampling device according to an embodiment of the present disclosure.
Fig. 10 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that, the illustrations provided in the following embodiments merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the prior art, a D flip-flop or a register for sampling an IO input signal has a metastable state, and when a jitter or a glitch of the IO input signal happens to occur in the metastable state, the jitter or the glitch may be input to the GPIO. This may result in an IO erroneous pulse input. This problem is particularly pronounced in industrial control scenarios where the signal noise is large.
To solve at least the above-mentioned problems, the embodiments of the present disclosure provide an IO adoption scheme that achieves debounce and deburring of an IO input signal by sampling the rising and falling edges of the IO input signal simultaneously according to a clock cycle signal. The clock period signal is set such that half the clock period length of the clock period signal is greater than the width of jitter or glitches contained in the IO input signal. The rising edge sampling and the falling edge sampling are carried out on the IO input signal according to the clock period signal, so that the rising edge sampling signal is different from the falling edge sampling signal when jitter or burr is contained in the IO input signal, and the last sampling signal which is output is adopted instead of the current sampling signal at the moment. When the rising edge sampling signal is identical to the falling edge sampling signal, the IO input signal does not contain jitter or burr, and at the moment, the rising edge sampling signal or the falling edge sampling signal is output as the sampling signal for the IO input signal. In this way, debounce and deburring for the IO input signal is achieved.
Referring to fig. 1 and 2, fig. 1 illustrates a first application scenario diagram of an IO sampling method according to an embodiment of the present disclosure, and fig. 2 illustrates a second application scenario diagram of an IO sampling method according to an embodiment of the present disclosure. The following embodiments of the present disclosure provide IO sampling methods and apparatuses, and electronic devices, including but not limited to various signal jitters applied in signal transmission processes. In one aspect, the present disclosure may be applied to the dithering of the mechanical key shown in fig. 1, such as a low level reaching a high level after being dithered, which may be restored to a stable value at a desired time. On the other hand, the present disclosure may be applied to signal mutations and burrs caused by electromagnetic radiation interference in the industrial control application shown in fig. 2, where the mutations are unexpected, may occur at any time, and may exist all the time.
The technical solutions in the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings in the embodiments of the present disclosure.
Fig. 3 is a flow chart illustrating an IO sampling method according to an embodiment of the present disclosure. As shown in fig. 3, the present embodiment provides an IO sampling method including the following steps S31 to S35.
In step S31, an IO input signal is received.
Specifically, according to different application scenarios, the IO input signal may be an input signal of a temperature sensor, a pressure sensor or a motion sensor, or may be an input signal of a communication line, or may be an input signal of a touch screen or a touch screen controller.
In step S32, the IO input signal is subjected to rising edge sampling and falling edge sampling according to the clock cycle signal to obtain a rising edge sampling signal and a falling edge sampling signal.
In an embodiment, the IO input signal is sampled according to a rising edge and a falling edge of one of the clock cycle signals or according to a falling edge of one of the clock cycle signals and a rising edge of a next clock cycle to obtain the rising edge sampling signal and the falling edge sampling signal.
Further, in an embodiment, the rising edge sampling signal is obtained by sampling the IO input signal according to the clock cycle signal by using a rising edge sampling D flip-flop, and the falling edge sampling signal is obtained by sampling the IO input signal according to the clock cycle signal by using a falling edge sampling D flip-flop.
In an embodiment, the IO input signal is sampled at a rising edge and sampled at a falling edge according to the clock cycle signal, such that the rising edge sampling signal is different from the falling edge sampling signal when jitter or glitch is included in the IO input signal.
In step S33, the rising edge sampling signal and the falling edge sampling signal are compared to obtain a comparison result.
In an embodiment, if the rising edge sampling signal is the same as the falling edge sampling signal, a first comparison signal having a first level is output. And outputting a second comparison signal having a second level opposite to the first level if the rising edge sampling signal is not identical to the falling edge sampling signal.
In one embodiment, comparing the rising edge sampled signal and the falling edge sampled signal to obtain a comparison result comprises: and performing an exclusive nor operation on the rising edge sampling signal and the falling edge sampling signal.
When the comparison result is obtained, the exclusive nor operation may be performed, or a circuit implementation manner having the same effect as that of the exclusive nor operation may be achieved, and the same effect means that the abnormal burr pulse may be isolated.
In step S34, a signal to be output is selected from the last sampled signal and the current sampled signal, which are the rising edge sampled signal or the falling edge sampled signal, according to the comparison result.
In an embodiment, the current sampling signal is selected according to the first comparison signal in a current clock cycle of the clock cycle signals, and the last sampling signal which has been output is selected according to the second comparison signal in the current clock cycle, the last sampling signal which has been output being output in the current clock cycle.
Specifically, the output signal of the exclusive or gate is to be input to the function of the unit to select one of the 0-port signal or the 1-port signal based on the output signal of the exclusive or gate. When the exclusive-or gate outputs 1, the 1-terminal input is selected, and when the exclusive-or gate outputs 0, the 0-terminal input is selected, and in practical application, the device for realizing the selection output function may be a selector in an electronic circuit.
And (3) isolating the abnormal burr pulse by using an exclusive-or gate calculation result, inputting a sampled rising edge sampling signal or a sampled falling edge sampling signal only when the exclusive-or gate calculation result is 1, otherwise, keeping the original state, namely selecting an output signal of the last clock for output. An exclusive or gate output signal of 1 indicates that the input result is relatively stable, rather than abnormal glitches.
In step S35, the signal to be output is output as a sampling signal corresponding to the IO input signal.
In an embodiment, the selected signal to be output is temporarily stored in a current clock cycle of the clock cycle signals, and the signal to be output is output as the sampling signal in a next clock cycle of the clock cycle signals.
In an embodiment, the IO sampling method may further include: receiving a selection signal, and selecting one sampling signal from the rising edge sampling signal and the falling edge sampling signal according to the selection signal to serve as the current sampling signal.
In an embodiment, the IO sampling method may further include: the clock period signal is down-converted or divided such that half of the clock period length is greater than the width of jitter or glitches contained in the IO input signal.
The protection scope of the IO sampling method according to the embodiments of the present disclosure is not limited to the execution sequence of the steps listed in the embodiments, and all the schemes implemented by adding or removing steps and replacing steps according to the prior art made by the principles of the present disclosure are included in the protection scope of the present disclosure.
The embodiment of the disclosure also provides an IO sampling device, which can implement the IO sampling method of the disclosure, but the implementation device of the IO sampling method of the disclosure includes, but is not limited to, the structure of the IO sampling device listed in the embodiment, and all structural modifications and substitutions made according to the principles of the disclosure in the prior art are included in the protection scope of the disclosure.
Fig. 4 is a schematic structural diagram of an IO sampling device according to an embodiment of the present disclosure. As shown in fig. 4, the present embodiment provides an IO sampling device 5 including an input terminal 51, a sampling circuit 52, an arithmetic circuit 53, a signal selecting circuit 54, and an output circuit 55.
The input terminal 51 is configured to receive an IO input signal.
The sampling circuit 52 is configured to sample the IO input signal in rising and falling edges according to a clock cycle signal to output a rising edge sampling signal and a falling edge sampling signal.
The arithmetic circuit 53 is configured to compare the rising-edge sampling signal and the falling-edge sampling signal to output a comparison result.
The signal selection circuit 54 is configured to select and output one signal to be output from the last sampled signal and the current sampled signal, which is the rising edge sampled signal or the falling edge sampled signal, which have been output, according to the comparison result.
The output circuit 55 is configured to output the signal to be output as a sampling signal corresponding to the IO input signal.
In several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus or method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, e.g., the division of modules/units of circuitry is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple modules or units may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules or units, which may be in electrical, mechanical or other forms.
The modules/units illustrated as separate components may or may not be physically separate, and components shown as modules/units may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules/units may be selected according to actual needs to achieve the objectives of the embodiments of the present disclosure. For example, functional modules/units in various embodiments of the present disclosure may be integrated into one processing module, or each module/unit may exist alone physically, or two or more modules/units may be integrated into one module/unit.
Those of ordinary skill would further appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
Fig. 5 shows a first circuit schematic of an IO sampling circuit according to an embodiment of the present disclosure. As shown in fig. 5, an embodiment of the present disclosure provides an IO sampling device 5, which includes: an input terminal 51, a sampling circuit 52, an arithmetic circuit 53, a signal selection circuit 54, and an output circuit 55.
The input terminal 51 is configured to receive an IO input signal gpio_in.
The sampling circuit 52 is configured to sample the IO input signal gpio_in on a rising edge and a falling edge according to the clock cycle signal db_clk to output a rising edge sampling signal gpio_in_pos and a falling edge sampling signal gpio_in_neg.
The arithmetic circuit 53 is configured to compare the rising-edge sampling signal gpio_in_pos and the falling-edge sampling signal gpio_in_neg to output a comparison result.
The signal selection circuit 54 is configured to select and output one signal to be output from the last sampled signal db_gpio_in and the current sampled signal gpio_in_pos, which is the rising edge sampled signal or the falling edge sampled signal, according to the comparison result xnor _vld.
The output circuit 55 is configured to output the signal db_gpio_in_d to be output as a sampling signal corresponding to the IO input signal.
In one embodiment, the output circuit 55 includes a register. The register is configured to receive the clock cycle signals and the signal to be output, temporarily store the signal to be output at a current clock cycle of the clock cycle signals, and output the signal to be output as the sampling signal at a next clock cycle of the clock cycle signals.
Specifically, register sampling is performed on the signal to be output to obtain db_gpio_in, so that the signal to be output db_gpio_in_d is output as a sampling signal corresponding to the IO input signal. In practical applications, the function of the register is implemented by using a D flip-flop. In practical applications, as shown in fig. 5, the input signal of the current clock (i.e. the 1-terminal input of the signal selection circuit 54) takes a fixed rising edge sampling signal gpio_in_pos as an input. In another practical application, the input signal of the current clock (i.e. the 1-terminal input of the signal selection circuit 54) may also take the fixed falling edge sampling signal gpio_in_neg as an input.
As shown in fig. 5, the sampling circuit 52 includes a first D flip-flop and a second D flip-flop.
The first D flip-flop is configured such that a first clk terminal (a non-circular clk terminal) receives the clock cycle signal, a first D input terminal receives the IO input signal, and samples the IO input signal according to a rising edge of the clock cycle signal to output the rising edge sampling signal.
The second D flip-flop is configured to receive the clock cycle signal at a second clk terminal (circled clk terminal), receive the IO input signal at a second D input terminal, and sample the IO input signal according to a falling edge of the clock cycle signal to output the falling edge sampling signal.
As shown in fig. 5, the arithmetic circuit 53 is configured to compare the rising-edge sampling signal and the falling-edge sampling signal to output a comparison result.
In one embodiment, the operation circuit includes an exclusive or gate. The exclusive-or gate is configured to receive the rising-edge sampling signal and the falling-edge sampling signal and exclusive-or the rising-edge sampling signal and the falling-edge sampling signal to output a first comparison signal having a first level or a second comparison signal having a second level opposite to the first level as the comparison result.
In one embodiment, the signal selection circuit includes a first selector. The first selector is configured to receive the comparison result, the current sampling signal, and the outputted last sampling signal, select and output the current sampling signal as the signal to be outputted when the comparison result is the first comparison signal, and select and output the outputted last sampling signal as the signal to be outputted when the comparison result is the second comparison signal.
Specifically, in response to the exclusive-ored output signal xnor _vld being 1, the signal selection circuit 54 is configured to select the input signal gpio_in_pos of the current clock for output; in response to the exclusive-ored output signal xnor _vld being 0, the first selector is configured to select the output signal db_gpio_in of the last clock for output.
In the disclosure, an IO input signal is sampled at a rising edge and a falling edge respectively, then sampling data at two different edges are subjected to an exclusive OR operation, when the exclusive OR result is 1, an edge selection signal (edge_sel) is used for selecting the input signal, a register is used for outputting a signal (db_gpio_in), and finally the signal is supplied to a GPIO circuit.
In this scheme, the glitches have been filtered after the first stage sampling of rising and falling edges. The signal of the second stage output db gpio in does not generate metastability. Therefore, the circuit can avoid the error sampling of IO input signals and well realize jitter elimination and filtering.
Fig. 6 shows a second circuit schematic of an IO sampling circuit according to an embodiment of the present disclosure. As shown in fig. 6, the circuit includes a second selector 56 in addition to an input terminal 51, a sampling circuit 52, an arithmetic circuit 53, a signal selection circuit 54, and an output circuit 55.
The input terminal 51, the sampling circuit 52, the arithmetic circuit 53, the signal selecting circuit 54, and the output circuit 55 shown in fig. 6 are the same as the corresponding modules or units in the embodiment described with reference to fig. 5, and are not described again.
Further, the second selector 56 is configured to receive a selection signal, the rising-edge sampling signal, and the falling-edge sampling signal, and select one sampling signal among the rising-edge sampling signal and the falling-edge sampling signal as the current sampling signal according to the selection signal.
As shown in fig. 6, the function of the selection signal, i.e., the unit (second selector 56) to which the edge_sel signal is to be input, is to select one of the 0-port signal or the 1-port signal based on the edge_sel signal. The edge_sel signal is configured through a system register, and the scheme can improve the flexibility of application scenes. When edge_sel outputs 1, the 1-terminal (rising edge sampling signal gpio_in_pos) is selected, and when edge_sel outputs 0, the 0-terminal (falling edge sampling signal gpio_in_neg) is selected. The device is a selector in an electronic circuit.
The rising and falling edge samples differ for different scene timing realizations. The rising edge sampling may be selected when it is difficult to meet the setup time requirements of the later stage register db_gpio_in, and the falling edge sampling may be selected when it is difficult to meet the hold time requirements thereof. For example, rising edge sampling may be selected in a key scenario of rising edges such as key detection, pulse counting, signal presence detection, etc.; the falling edge sampling may be selected at the falling edge of key release, pulse end, communication end, timer control, etc.
Fig. 7 shows a signal timing diagram of an IO sampling circuit according to an embodiment of the present disclosure. As shown in fig. 7, in conjunction with the circuit shown in fig. 6, db_clk represents the debounce clock, i.e., the clock cycle signal (clk clocks of the first D flip-flop and the second D flip-flop), gpio_in represents the IO input signal, gpio_in_pos represents the D flip-flop sampling result of rising edge sampling, gpio_in_neg represents the D flip-flop sampling result of falling edge sampling, xnor _vld represents the nor operation determination valid result, edge_sel represents the edge selection signal of the second selector 56, db_gpio_in_d represents the D terminal input signal of the register, and the final input signal after debounce is db_gpio_in.
At time 5 gpio_in is disturbed by the outside in the vicinity of the db_clk rising edge to produce a signal glitch, which is sampled at this time by gpio_in_pos. If this signal is output directly to db gpio in, it will result in an erroneous pulse determination. At the same time of sampling the clock falling edge, the signal is not sampled, at the moment xnor _vld is pulled low, and error pulses sampled by gpio_in_pos are isolated and filtered and cannot be transmitted to db_gpio_in_d, so that correct sampling is ensured.
In addition, the circuit has the effect of filtering out metastables, which may occur at time 5 if the glitch does not meet the setup hold time of the rising edge samples. When the metastable state stabilizes to result in 0 over a period of time, the output of db_gpio_in is not affected at this time. When the metastable state stable result is 1, the output of db_gpio_in is not affected due to the isolation of the exclusive nor logic.
At time 14 gpio_in outputs a stable signal, but when not glitches gpio_in_pos and gpio_in_neg are both sampled high, xnor _vld is pulled high, and only the signal can be transmitted to db_gpio_in_d.
Fig. 8 shows a third circuit schematic of an IO sampling circuit according to an embodiment of the present disclosure. As shown in fig. 8, the circuit configuration shown is compared with the circuit shown in fig. 6, in which the positions of the first D flip-flop and the second D flip-flop are interchanged in the sampling circuit 52, the first D flip-flop outputting gpio_in_pos and the second D flip-flop outputting gpio_in_neg.
Fig. 9 is a fourth schematic circuit diagram of an IO sampling circuit according to an embodiment of the present disclosure. As shown in fig. 9, the circuit configuration shown provides a modified circuit of the output circuit 55, which realizes a function of register sampling by 2 or more D flip-flops, compared with the circuit shown in fig. 6, and the probability of occurrence of metastable state when the frequency is increased is smaller although the area of this embodiment becomes larger and the data transfer delay becomes larger.
According to the technical scheme, as sampling values of the rising edge and the falling edge are utilized to carry out an exclusive OR operation, the jitter elimination time is limited to half a clock period. If the actual scene jitter time is longer, increasing the jitter time may be achieved by down-converting or dividing the jitter clock. The longer jitter time, i.e. the width of the abnormal pulse, means that the jitter eliminating effect cannot be ensured when the jitter eliminating time exceeds half a clock period. After the debounce clock is divided and down-converted, the frequency of the debounce clock is reduced, the clock period is prolonged, and the time corresponding to half the clock period is prolonged. Thus, the debounce time can be increased.
Referring to the timing diagram of fig. 7, the principle of the circuit is to sample the rising edge and the falling edge of db_clk at the same time, and only if the sampling result is identical to the or operation result, the input signal is valid. If a jitter or pulse is more than half a clock period, it is possible that both rising and falling edges sample the jitter pulse, resulting in a situation where the pulse is input. The debounce time is half a clock period.
The purpose of the frequency reduction and the frequency division is to reduce the frequency of the anti-jitter clock, increase the clock period and realize the increase of the anti-jitter time. For example, when the debounce clock is 20MHz, where one clock cycle is 50ns in length, the glitch that can be filtered out is 25ns in length for half the clock cycle. If the jitter length in the application scene is more than 25ns, the frequency of db_clk is reduced to 10MHz through the system, the half clock period length is 50ns, and jitter or burrs with the width of 50ns can be filtered.
Fig. 10 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure. As shown in fig. 10, an embodiment of the present disclosure provides an electronic device, including: the IO sampling device, and at least one of the sensor interface, the communication interface, and the touch screen interface as described above, are configured to receive the sampling signal from the IO sampling device.
The IO sampling device is a device or an IO sampling device corresponding to the IO sampling method described in the above embodiments, and will not be described herein.
The actual application scene of the present disclosure is as follows:
For a sensor interface: the system comprises a plurality of sensors, such as a temperature sensor, a pressure sensor or a motion sensor, noise can be generated during initial starting or environment change, and the IO sampling method and device and the IO jitter elimination function of the electronic equipment provided by the disclosure are helpful for filtering out the transient noise.
For the communication interface: in data communication, jitter on a signal line may cause data errors, and the IO sampling method and device and the IO jitter elimination function of the electronic equipment provided by the disclosure can improve the accuracy of data and the reliability of communication.
For touch screens and touch screen controllers: the touch screen may be interfered by the outside when detecting a touch event, and the IO sampling method and device and the IO jitter elimination function of the electronic equipment provided by the disclosure can reduce false touch and improve touch precision.
The descriptions of the processes or structures corresponding to the drawings have emphasis, and the descriptions of other processes or structures may be referred to for the parts of a certain process or structure that are not described in detail.
The above embodiments are merely illustrative of the principles of the present disclosure and its efficacy, and are not intended to limit the disclosure. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present disclosure. Accordingly, it is intended that all equivalent modifications and variations which a person having ordinary skill in the art would accomplish without departing from the spirit and technical spirit of the present disclosure be covered by the claims of the present disclosure.
Claims (17)
1. An IO sampling method, comprising:
Receiving an IO input signal;
Performing rising edge sampling and falling edge sampling on the IO input signal according to the clock period signal to obtain a rising edge sampling signal and a falling edge sampling signal;
comparing the rising edge sampling signal with the falling edge sampling signal to obtain a comparison result;
Selecting a signal to be output from the last sampling signal and the current sampling signal which are output according to the comparison result, wherein the current sampling signal is the rising edge sampling signal or the falling edge sampling signal; and
And outputting the signal to be output as a sampling signal corresponding to the IO input signal.
2. The IO sampling method of claim 1, wherein sampling the IO input signal at a rising edge and a falling edge according to a clock cycle signal to obtain a rising edge sampling signal and a falling edge sampling signal comprises:
The IO input signal is sampled according to a rising edge and a falling edge of one clock cycle of the clock cycle signals or according to a falling edge of one clock cycle of the clock cycle signals and a rising edge of a next clock cycle to obtain the rising edge sampling signal and the falling edge sampling signal.
3. The IO sampling method of claim 1, wherein sampling the IO input signal at a rising edge and a falling edge according to a clock cycle signal to obtain a rising edge sampling signal and a falling edge sampling signal comprises:
And carrying out rising edge sampling and falling edge sampling on the IO input signal according to the clock period signal, so that the rising edge sampling signal is different from the falling edge sampling signal when jitter or burr is contained in the IO input signal.
4. The IO sampling method of claim 1, wherein comparing the rising edge sampling signal and the falling edge sampling signal to obtain a comparison result comprises:
Outputting a first comparison signal having a first level if the rising edge sampling signal is identical to the falling edge sampling signal; and
And outputting a second comparison signal having a second level opposite to the first level if the rising edge sampling signal is not identical to the falling edge sampling signal.
5. The IO sampling method according to claim 4, wherein selecting one signal to be output from the last sampled signal and the current sampled signal that have been output according to the comparison result comprises:
Selecting the current sampling signal according to the first comparison signal in the current clock period in the clock period signals; and
And selecting the last sampling signal which is output according to the second comparison signal in the current clock cycle, wherein the last sampling signal which is output in the current clock cycle.
6. The IO sampling method of claim 1, wherein outputting the signal to be output as a sampling signal corresponding to the IO input signal comprises:
temporarily storing the selected signal to be output in the current clock period in the clock period signals; and
And outputting the signal to be output as the sampling signal in the next clock cycle of the clock cycle signals.
7. The IO sampling method of claim 1, wherein sampling the IO input signal at a rising edge and a falling edge according to a clock cycle signal to obtain a rising edge sampling signal and a falling edge sampling signal comprises:
sampling the IO input signal according to the clock period signal by using a rising edge sampling D trigger to obtain a rising edge sampling signal; and
And sampling the IO input signal according to the clock cycle signal by using a D trigger of falling edge sampling to obtain the falling edge sampling signal.
8. The IO sampling method of claim 1, wherein comparing the rising edge sampling signal and the falling edge sampling signal to obtain a comparison result comprises:
And performing an exclusive nor operation on the rising edge sampling signal and the falling edge sampling signal.
9. The IO sampling method of claim 1, further comprising:
Receiving a selection signal; and
And selecting one sampling signal from the rising edge sampling signal and the falling edge sampling signal according to the selection signal to serve as the current sampling signal.
10. The IO sampling method of claim 1, further comprising:
the clock period signal is down-converted or divided such that half of the clock period length is greater than the width of jitter or glitches contained in the IO input signal.
11. An IO sampling device, comprising:
an input terminal configured to receive an IO input signal;
A sampling circuit configured to perform rising edge sampling and falling edge sampling on the IO input signal according to a clock cycle signal to output a rising edge sampling signal and a falling edge sampling signal;
An arithmetic circuit configured to compare the rising edge sampling signal and the falling edge sampling signal to output a comparison result;
A signal selection circuit configured to select and output one signal to be output from the last sampled signal and the current sampled signal which are output according to the comparison result, wherein the current sampled signal is the rising edge sampled signal or the falling edge sampled signal; and
And an output circuit configured to output the signal to be output as a sampling signal corresponding to the IO input signal.
12. The IO sampling device of claim 11, wherein the sampling circuit comprises:
A first D flip-flop configured to receive the IO input signal and the clock cycle signal and sample the IO input signal according to a rising edge of the clock cycle signal to output the rising edge sampling signal; and
A second D flip-flop configured to receive the IO input signal and the clock cycle signal and sample the IO input signal according to a falling edge of the clock cycle signal to output the falling edge sampling signal.
13. The IO sampling device of claim 11, wherein the arithmetic circuit comprises:
an exclusive-or gate configured to receive the rising-edge sampling signal and the falling-edge sampling signal and exclusive-or the rising-edge sampling signal and the falling-edge sampling signal to output a first comparison signal having a first level or a second comparison signal having a second level opposite to the first level as the comparison result.
14. The IO sampling device of claim 13, wherein the signal selection circuit comprises:
A first selector configured to receive the comparison result, the current sampling signal, and the outputted last sampling signal, select and output the current sampling signal as the signal to be outputted when the comparison result is the first comparison signal, and select and output the outputted last sampling signal as the signal to be outputted when the comparison result is the second comparison signal.
15. The IO sampling device of claim 11, wherein the output circuit comprises:
And a register configured to receive the clock cycle signals and the signal to be output, temporarily store the signal to be output in a current clock cycle of the clock cycle signals, and output the signal to be output as the sampling signal in a next clock cycle of the clock cycle signals.
16. The IO sampling device of claim 11, further comprising:
And a second selector configured to receive a selection signal, the rising-edge sampling signal, and the falling-edge sampling signal, and select one sampling signal among the rising-edge sampling signal and the falling-edge sampling signal as the current sampling signal according to the selection signal.
17. An electronic device, comprising:
The IO sampling device according to any one of claims 11 to 16; and
At least one of a sensor interface, a communication interface, and a touch screen interface is configured to receive the sampling signal from the IO sampling device.
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| CN111211774A (en) * | 2018-11-21 | 2020-05-29 | 英业达科技有限公司 | Bounce removing circuit |
| CN116800229A (en) * | 2022-03-17 | 2023-09-22 | 澜起电子科技(上海)有限公司 | Burr removing circuit |
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| KR200222679Y1 (en) * | 2000-11-25 | 2001-05-15 | 엘지전자주식회사 | Apparatus for selective detecting rising edge and falling edge of input signal |
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| CN111211774A (en) * | 2018-11-21 | 2020-05-29 | 英业达科技有限公司 | Bounce removing circuit |
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