CN119003389A

CN119003389A - Equipment control method, processor architecture and computer equipment

Info

Publication number: CN119003389A
Application number: CN202411074785.7A
Authority: CN
Inventors: 杨维韬; 彭崇武
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2024-08-06
Filing date: 2024-08-06
Publication date: 2024-11-22

Abstract

The present application provides a device control method, a processor architecture and a computer device, which are applied to the field of computer technology. The method is applied to a processor architecture, which includes an application processor, an input-output processor and at least one peripheral controller. The input-output processor includes a processor core and an inter-core communication module. The inter-core communication module includes an inter-core channel corresponding to the peripheral controller one by one. The application processor stores request data in a target inter-core channel corresponding to the target peripheral controller, and triggers the processor core to access the target peripheral controller according to the request data, and generates a trigger for the application processor to obtain the response data after storing the corresponding response data in the target inter-core channel to complete data interaction. The input-output processor serves as a medium for interaction between the application processor and the peripheral controller. Changes in the peripheral controller will not affect the application processor, thereby minimizing the impact of changes in the peripheral controller on the application processor.

Description

Equipment control method, processor architecture and computer equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a device control method, a processor architecture, and a computer device.

Background

In existing applications, an operating system or bare metal application loaded on computer hardware requires control of external devices via drivers. Referring to fig. 1, taking a System on Chip (SoC) as an example, the SoC is communicatively connected to an external device through a communication bus and controls the operation of the external device, where the external device includes multiple devices such as a serial device, an audio device, and a storage device. In order to realize the control of the external equipment, an application processor and peripheral equipment controllers corresponding to the external equipment are integrated in the system on chip, each peripheral equipment controller also corresponds to a driving program, and the application processor can access the peripheral equipment controller by executing the driving program to realize the information interaction with the peripheral equipment controller, so that the control of the corresponding external equipment is realized by the peripheral equipment controller.

In practical application, when any peripheral controller performs adjustment, for example, when a function is newly added or iterative upgrade is performed, a driver corresponding to the peripheral controller needs to be updated synchronously, and because an application processor accesses the peripheral controller by executing the driver, the peripheral controller and the driver can be updated synchronously together with the application processor, and even before-silicon verification needs to be performed again, so that a great amount of manpower and material resource consumption is consumed, and the design period is prolonged.

Disclosure of Invention

In view of the foregoing, the present application is directed to a device control method, a processor architecture, and a computer device, so as to solve the problem in the prior art that the peripheral controller changes synchronization adjustment of the associated application processor, and even needs to re-perform pre-silicon verification.

In a first aspect, the present application provides a device control method, applied to a processor architecture, where the processor architecture includes an application processor, an input/output processor and at least one peripheral controller, where the input/output processor is used as an intermediary when the application processor interacts with the at least one peripheral controller, the input/output processor includes at least one dedicated processor core and an inter-core communication module, the inter-core communication module includes at least one inter-core channel, and the inter-core channels are in one-to-one correspondence with the peripheral controllers, and the processor cores are respectively connected to each peripheral controller in a communication manner, and the method includes the following steps performed by the processor core:

Acquiring a first interrupt signal, wherein the first interrupt signal is triggered after the application processor stores request data in a target inter-core channel, and the target inter-core channel corresponds to a target peripheral controller which the application processor needs to access;

responding to the first interrupt signal, and acquiring request data in the target inter-core channel;

accessing the target peripheral controller according to the request data and acquiring corresponding response data;

And storing the response data in the target inter-core channel, and triggering a second interrupt signal, wherein the second interrupt signal is used for triggering the application processor to acquire the response data.

Based on the above, the device control method provided by the application is applied to a processor architecture, the method integrates an input/output processor in the processor architecture, the input/output processor is used as an intermediate medium when the application processor interacts with the peripheral controllers, and further the control of corresponding external devices is realized through each peripheral controller, for the application processor, the application processor can realize the control of the external devices only by communicating with a processor core, compared with the prior art that the application processor accesses the corresponding peripheral controller through executing the driving program, the peripheral controller adjustment and the driving program adjustment caused by the peripheral controller adjustment can be synchronously updated with the application processor, the method can realize that any peripheral controller change can not affect the application processor, and only the internal driving of the processor core is required to be adjusted, so that the influence of the peripheral controller change on the application processor is reduced to the greatest extent, the verification before the silicon is carried out again is avoided, the manpower and material resource is saved, and the system design period is shortened.

In an alternative embodiment, the inter-core channel includes a shared memory unit, where the shared memory unit is configured to store a frame of request data;

Obtaining the request data in the target inter-core channel comprises the following steps:

and acquiring one frame of request data stored in a shared storage unit of the target inter-core channel.

In the application, an alternative implementation mode of the inter-core channel is provided, namely, the shared storage unit is used as the inter-core channel, and because the shared storage unit can only store one frame of data, the size of interaction data of two communication parties can be limited based on the shared storage unit, the data transmission rule is standardized, and the stability of the data transmission process is improved.

In an alternative embodiment, the inter-core channel includes a plurality of first storage units corresponding to the application processor, each of the first storage units being configured to store one frame of request data;

acquiring request data in at least one first storage unit in a plurality of first storage units of the target inter-core channel;

the number of frames of the extracted request data is counted.

In the application, another alternative implementation manner of the inter-core channel is provided, the inter-core channel comprises a plurality of first storage units corresponding to the application processor, the application processor can store one frame of data into each first storage unit, based on the first storage units, the processor core can determine and acquire one or more pieces of request data for processing according to actual software and hardware resources, the data quantity of the request data is flexibly selected, the resources of the processor core can be fully utilized, and meanwhile, the data processing efficiency can be improved.

In an alternative embodiment, the inter-core channel includes a plurality of second storage units corresponding to the input/output processor, each of the second storage units being configured to store one frame of response data;

Storing the response data in the target inter-core channel, including:

storing each frame of response data in one of said second memory locations of said target inter-core channel;

the number of frames of the stored response data is counted.

In the application, the inter-core channel comprises a plurality of second storage units corresponding to the input and output processors, each second storage unit can store one frame of data, and the processor core can store one or more frames of response data in the inter-core channel according to the data quantity of the response data, so as to support the synchronous storage of the multiple frames of data and be beneficial to improving the efficiency of the processor core for feeding back the response data to the application processor.

In an alternative embodiment, accessing the target peripheral controller according to the request data and acquiring corresponding response data includes:

Accessing a preset register in the target peripheral controller according to the request data;

acquiring response data recorded in the preset register;

Or alternatively

The request data is sent to the target peripheral controller so as to trigger the target peripheral controller to output a third interrupt signal;

and responding to the third interrupt signal, and acquiring response data recorded by a preset register in the target peripheral controller.

In the application, two modes of acquiring response data of the peripheral controller by the processor core are provided, one mode is that the processor core directly accesses a preset register of the peripheral controller to acquire recorded response data, the other mode is that the response data recorded in the preset register is acquired in response to an interrupt signal of the peripheral controller, in practical application, a data interaction mode between the processor core and the peripheral controller can be configured according to the actual requirement and the mode of the peripheral controller for feeding back the data, and further, the data interaction requirements under different scenes and the access limit requirements of the peripheral controller are met.

In a possible implementation manner, the device control method provided in the first aspect of the present application further includes:

Responding to a fourth interrupt signal, acquiring data to be uploaded of the peripheral controller, wherein the fourth interrupt signal is triggered by the peripheral controller under the condition that the peripheral controller needs to upload the data to the application processor;

storing the data to be uploaded to an inter-core channel corresponding to the peripheral controller;

and sending a fifth interrupt signal to trigger the application processor to acquire the data to be uploaded.

In the application, the peripheral controller informs the input/output processor to acquire the data to be uploaded in an interrupt mode, and after the input/output processor stores the data to be uploaded in the inter-core channel corresponding to the peripheral controller, the peripheral controller also informs the application processor to acquire the data to be uploaded in an interrupt mode, so that the transmission of the data to be uploaded is completed. In the uploading process of the data to be uploaded, the peripheral controller only interacts with the input/output processor, the input/output processor is used as an intermediate medium when the application processor interacts with the peripheral controller, the input/output processor feeds the data to be uploaded back to the application processor, so that the decoupling between the application processor and the peripheral controller is realized, compared with the prior art that the application processor interacts with the corresponding peripheral controller through executing a driving program, the peripheral controller adjustment and the driving program adjustment caused by the peripheral controller adjustment can be synchronously updated together with the application processor, and the method can realize that the application processor is not influenced by any change of the peripheral controller, and only the internal drive of the processor core is required to be adjusted, so that the influence of the change of the peripheral controller on the application processor is reduced to the greatest extent.

In a second aspect, the present application provides a device control method, applied to a processor architecture, where the processor architecture includes an application processor, an input/output processor and at least one peripheral controller, where the input/output processor is used as an intermediary when the application processor interacts with the at least one peripheral controller, the input/output processor includes at least one dedicated processor core and an inter-core communication module, the inter-core communication module includes at least one inter-core channel, and the inter-core channels are in one-to-one correspondence with the peripheral controllers, and the processor cores are respectively connected to each peripheral controller in communication, and the method includes the following steps performed by the application processor:

Storing request data in a target inter-core channel, wherein the target inter-core channel corresponds to a target peripheral controller which is required to be accessed by the application processor;

Triggering a first interrupt signal, wherein the first interrupt signal is used for triggering the processor core to access the target peripheral controller according to the request data and outputting a second interrupt signal after storing corresponding response data in the target inter-core channel;

And responding to the second interrupt signal, and acquiring the response data.

The storing the request data in the target inter-core channel includes:

And storing one frame of request data in a shared storage unit of the target inter-core channel.

The storing the request data in the target inter-core channel includes:

storing each frame of request data in one of the first storage units of the target inter-core channel;

The number of frames in which the requested data has been stored is counted.

In the application, another alternative implementation manner of the inter-core channel is provided, the inter-core channel comprises a plurality of first storage units corresponding to the application processor, the application processor can store one frame of data into each first storage unit, in practical application, the application processor can store one or more pieces of request data in the inter-core channel according to the occupation condition of the inter-core channel, flexibly select the data volume for sending the request data, and is beneficial to improving the data processing efficiency.

In an alternative embodiment, the inter-core channel further includes a plurality of second storage units corresponding to the input/output processor, each of the second storage units being configured to store a frame of response data;

obtaining the response data includes:

Acquiring response data in at least one second storage unit in a plurality of second storage units of the target inter-core channel;

The number of frames of the extracted response data is counted.

In the application, the inter-core channel comprises a plurality of second storage units corresponding to the input/output processor, each second storage unit can store response data written by one frame of input/output processor, and in practical application, the application processor can acquire the response data in at least one second storage unit according to the practical load condition, so that flexible processing of the response data is realized, resources of the application processor can be fully utilized, and the processing efficiency of the response data is improved.

In an optional implementation manner, the device control method provided in the first aspect of the present application further includes: creating the inter-core communication module at a startup phase of the processor architecture;

and configuring a one-to-one correspondence between the peripheral controllers and the inter-core channels.

In the application, the application processor is used for loading the application program so as to execute the application layer task, and the application processor creates the inter-core communication module and configures the one-to-one correspondence between the peripheral controllers and the inter-core channels, so that a user can configure the inter-core communication module by himself according to the actual application requirements and the specific conditions of the peripheral controllers, and allocate the corresponding inter-core channels for each peripheral controller, thereby meeting the control requirements of each peripheral controller, and further, the device control method provided by the application can be applied to different application scenes and meet different application requirements.

In a possible implementation manner, the device control method provided in the second aspect of the present application further includes:

and responding to a fifth interrupt signal, and acquiring data to be uploaded of the peripheral controller, wherein the fifth interrupt signal is triggered after the processor core stores the data to be uploaded into an inter-core channel corresponding to the peripheral controller.

In the application, the peripheral controller only interacts with the input/output processor in the uploading process of the data to be uploaded, the input/output processor is used as an intermediate medium when the application processor interacts with the peripheral controller, the input/output processor feeds the data to be uploaded back to the application processor, compared with the prior art that the application processor interacts with the corresponding peripheral controller through executing the driving program, the peripheral controller adjustment and the driving program adjustment caused by the peripheral controller adjustment can be synchronously updated with the application processor, and the method can realize that the application processor is not influenced by any change of the peripheral controller and only needs to adjust the internal driving of the processor core, so that the influence of the change of the peripheral controller on the application processor is reduced to the greatest extent.

In a third aspect, the present application provides a processor architecture comprising: an application processor, an input output processor, and at least one peripheral controller, wherein,

The input/output processor is used as an intermediate medium when the application processor interacts with the at least one peripheral controller;

The input/output processor comprises at least one special processor core and an inter-core communication module, wherein the inter-core communication module comprises at least one inter-core channel, and the inter-core channels are in one-to-one correspondence with the peripheral controllers;

the processor cores are respectively in communication connection with the peripheral controllers;

any peripheral controller is used for controlling external equipment connected with the peripheral controller;

The processor core is configured to perform the device control method according to any one of the first aspects of the present application;

the application processor is configured to perform the device control method according to any one of the second aspects of the present application.

In a fourth aspect, the present application provides a computer device comprising: at least one external device and a processor architecture as provided in the third aspect of the application, wherein,

The processor architecture is communicatively coupled to each of the external devices, respectively.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a connection relationship between a system on a chip and an external device in the prior art.

Fig. 2 is a schematic structural diagram of a processor architecture according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of an inter-core channel according to an embodiment of the present invention.

Fig. 4 is a schematic flow chart of a device control method according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of another inter-core channel according to an embodiment of the present invention.

Fig. 6 is a flowchart of another device control method according to an embodiment of the present invention.

Fig. 7 is a schematic diagram of another inter-core channel according to an embodiment of the present invention.

Fig. 8 is a schematic diagram of a message structure according to an embodiment of the present invention.

Fig. 9 is a schematic diagram of another inter-core channel according to an embodiment of the present invention.

Fig. 10 is a flowchart of still another device control method according to an embodiment of the present invention.

Fig. 11 is a flowchart of another device control method according to an embodiment of the present invention.

Fig. 12 is a flowchart of another device control method according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In the existing application, an operating system or a bare metal application program loaded on computer hardware needs to access a register inside the peripheral controller through a driver, and then the peripheral controller controls corresponding external equipment. Referring to fig. 1, taking a System on Chip (SoC) as an example, the SoC is communicatively connected to an external device through a communication bus and controls the operation of the external device, where the external device includes multiple devices such as a serial device, an audio device, and a storage device. In order to realize the control of the external equipment, the system on a chip is internally integrated with an application processor and peripheral controllers corresponding to the external equipment, and each peripheral controller also corresponds to a driving program. In the example shown in fig. 1, a peripheral controller supporting a universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART) standard, a peripheral controller supporting a serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI) standard, a peripheral controller supporting a high definition audio (High Definition Audio, HDA) standard, and a peripheral controller supporting a multimedia card (Multi-MEDIA CARD, MMC) standard are shown, respectively, and a driver corresponding to each peripheral controller. The application processor can access the peripheral controller through executing the driving program, so that information interaction with the peripheral controller is realized, and further, the peripheral controller is used for controlling the external equipment connected with the peripheral controller.

In practical applications, one standard protocol usually corresponds to peripheral controllers of different chip manufacturers on the market, in other words, peripheral controllers of different chip manufacturers can support the same standard protocol, taking UART standard as shown in fig. 1 as an example, multiple peripheral controllers (only one is shown in the figure) supporting the communication standard from different chip manufacturers can be integrated in the system on chip, and it is understood that, since peripheral controllers of different chip manufacturers are independently developed, while peripheral controllers support the same standard, drivers required for driving peripheral controllers are not the same, which means how many peripheral controllers supporting UART standard are integrated in the system on chip, and a corresponding number of drivers need to be configured simultaneously.

In order to control each external device, the application processor needs to interact with the driver of each peripheral controller, based on this, when any peripheral controller in the system makes an adjustment, such as a new function or performs an iterative upgrade, the driver corresponding to the peripheral controller needs to be updated synchronously.

In order to solve the above-mentioned problems, the present application provides a processor architecture, applied to an SoC, and as shown in fig. 2, the processor architecture includes: an Input/Output Processor (IOP) 10, an application Processor 20, at least one peripheral controller 30 (one shown in fig. 2), and a first interconnection network 40, the application Processor 20 being communicatively coupled to the Input/Output Processor 10 via the first interconnection network 40.

The input output processor 10 includes at least one dedicated processor core 110 (shown as one in fig. 2), a memory 120, a register array 130, and a second interconnection network 140, wherein the processor core 110, the memory 120, and the register array 130 are each mounted on the second interconnection network 140. Of course, other functional modules for implementing the preset functions may be included in the input/output processor 10, which are not listed here, and are also within the scope of the present application without exceeding the core concept of the present application. Further, each peripheral controller 30 is also mounted on the second interconnection network 140.

Specifically, as shown in fig. 2, the processor core 110 is respectively connected to each peripheral controller 30 through the second interconnection network 140 in a communication manner, and the processor core 110 can directly access the peripheral controller 30, that is, write data into an internal register of the peripheral controller 30 or obtain response data fed back by the peripheral controller 30. In the present application, the processor core 110 may be configured to perform the device control method provided in the following embodiment, so as to achieve the above-mentioned function of accessing the peripheral controller 30 and thus controlling the corresponding external device. As for the specific contents of the device control method provided by the present application, the following description will be omitted herein.

The memory 120 is integrated inside the input/output processor 10, and is a memory that can be directly accessed by the processor core 110 through the second interconnection network 140, and at the same time, the application processor 20 can also directly access the memory 120 through the first interconnection network 40 and the second interconnection network 140. Based on this communication connection, it can be seen that one of the roles of the memory 120 enables data transfer between the processor core 110 and the application processor 20. In particular, in the present application, the memory 120 and the register array 130 are used to construct an inter-core communication module, and to store interaction data between the application processor 20 and the processor core 110, and as for the specific implementation of the inter-core communication module, the specific implementation will be described in detail later herein. Further, the memory 120 stores the default system firmware of the i/o processor 10 during the start-up of the i/o processor 10, and the processor core 110 loads the default system firmware to implement the default system functions of the i/o processor 10.

The register array 130 is one of the components of the input/output processor 10, and is formed by a plurality of registers corresponding to different functions, for example, a register for triggering an interrupt signal, a register for recording a data read/write state, a register for recording a data write number, a register for recording a data read number, a register for configuring the capacity of the inter-core communication module, and the like. In the present application, register array 130, one of the most important roles, i.e., in cooperation with memory 120, builds an inter-core communication module for enabling application processor 20 to interact with processor core 110 data.

Based on this, the processor core 110 may further perform data interaction with the application processor 20 based on the inter-core communication module formed by the memory 120 and the register array 130, so as to implement data interaction between the application processor 20 and the peripheral controller 30, so that the application processor 20 may access the peripheral controller 30 through the input/output processor 10, and further control the corresponding external device, and the input/output processor 10 is used as an intermediary when the application processor 20 interacts with each peripheral controller 30.

The second interconnection network 140 serves as a path for data interaction, and data interaction between any two or more modules mounted on the second interconnection network 140 is achieved. For example, the processor core 110 accesses the memory 120 through the second interconnection network 140, writes data into the storage space of the memory 120, or reads data stored in the storage space of the memory 120 through the second interconnection network 140, for example, the processor core 110 performs a write operation on a certain register in the register array 130 through the second interconnection network 140, thereby triggering a corresponding interrupt signal. Further, the second interconnection network 140 also serves as a channel for the data interaction between the input/output processor 10 and the application processor 20, for example, the application processor 20 sends data to the IOP10 through the first interconnection network 40, the data is written into the memory 120 through the second interconnection network 140, and then the processor core 110 reads the data written into the memory 120 by the application processor 20 through the second interconnection network 140, so as to implement data transmission between the application processor 20 and the processor core 110, i.e. the IOP 10.

The application processor 20 is typically used to carry an operating system and application programs, perform most of the tasks of the application layer, and perform necessary information interactions with the user, and in the related art related to the present application, the application processor 20 is also used to control external devices. In the processor architecture provided by the present application, the application processor 20 realizes data interaction with each peripheral controller 30 through the IOP10, thereby realizing control of external devices. As for the data interaction process between the application processor 20 and the IOP10, it will be developed in the following, and will not be described in detail here.

The peripheral controller 30 is configured to implement control of the connected external device according to the instruction or data sent by the IOP 10. As mentioned above, in practical applications, the processor architecture may integrate different peripheral controllers according to the actual functional requirements, where the peripheral controllers may support the same protocol, or may support different protocols, and for the specific selection and implementation of the peripheral controller 30, reference may be made to the actual requirements of the processor architecture and the implementation of the related technologies, which is not limited in this disclosure. As shown in connection with FIG. 2, each peripheral controller 30 is mounted to a second interconnection network 140 of IOP10 for direct data interaction with processor core 110.

The first interconnection network 40 functions similarly to the second interconnection network 140, i.e. also as a path for data interaction, and may be used for data interaction between the input output processor 10 and the application processor 20. In practical applications, the processor architecture may further include other functional modules, which may be all mounted on the first interconnection network 40, so as to implement data transmission between each other. As for the specific implementation of the first interconnection network 40, reference may be made to the related art, which is not particularly limited by the present application.

The input/output processor 10 is integrated in a processor architecture, and is configured to share the pressure of the application processor 20, and serve as an intermediate medium when the application processor 20 and the peripheral controllers 30 interact with each other, so that the application processor 20 can access each peripheral controller 30 through the input/output processor 10, thereby implementing control of external devices connected to the peripheral controllers 30. As for the specific process of implementing the data interaction between the application processor 20 and the peripheral controller 30 based on the input/output processor 10, it will be described in the following, and will not be described in detail here.

It should be noted that, in the embodiment shown in fig. 2, the peripheral controller 30 is disposed outside the input/output processor 10, the input/output processor 10 is mainly used for implementing an intermediate medium for data interaction between the application processor 20 and the peripheral controller 30, and the specific external device control is implemented by the peripheral controller 30, so that the function of the input/output processor 10 is more specific, and the overall architecture is simple. In another alternative embodiment, the peripheral controller 30 may be integrated inside the i/o processor 10, so that the i/o processor 10 integrates the functions of the foregoing intermediate medium and controlling the external device, which further helps to realize unified design and layout of the peripheral controller 30 and the i/o processor 10, and the iterative upgrade of the peripheral controller is invisible to the user, so that the manufacturer does not need to provide any information of the peripheral controller to the user, thereby facilitating complete privatization of the peripheral controller, and meanwhile, ensuring that the application processor 20 cannot directly access the peripheral controller 30, and improving security.

As previously described, the memory and register arrays in the IOP are used to construct an inter-core communication module, based on which, in an alternative embodiment, an inter-core communication module as shown in fig. 3 may be constructed.

The inter-core communication module provided in this embodiment includes at least one inter-core channel (n inter-core channels are shown in fig. 3, where n is an integer greater than or equal to 1), each inter-core channel corresponds to one peripheral controller, and peripheral controllers corresponding to the inter-core channels are different from each other, that is, the inter-core channels and the peripheral controllers are in a one-to-one correspondence, and in combination with fig. 3, the inter-core channel 1 corresponds to the peripheral controller 1, and the inter-core channel n corresponds to the peripheral controller n.

In one possible implementation manner, in the inter-core communication module provided in this embodiment, the inter-core channel includes a first interrupt register, a second interrupt register, and a shared memory unit. The first interrupt register and the second interrupt register are both from the register array, the first interrupt register is used for triggering an interrupt signal by the application processor, and the second interrupt register is used for triggering an interrupt signal by the IOP. The shared memory unit is a memory space divided in advance in the memory.

It should be emphasized that in practical applications, the storage space of the shared storage unit includes two alternative divisions. In one possible implementation, the shared memory unit may further divide a first shared memory subunit and a second shared memory subunit, wherein the first shared memory subunit may be used to store one frame of request data, and the second shared memory subunit may be used to store one frame of response data, that is, the storage capacity of the shared memory unit is the sum of the sizes of one frame of request data and one frame of response data. In another possible embodiment, the shared memory unit can only store one frame of request data or one frame of response data at a time, for example, in the case that the request data is stored in the shared memory unit, if the response data needs to be stored, the request data needs to be overwritten, which means that the capacity of the shared memory unit needs to be determined according to the request data and the size of the response data, that is, the larger capacity of the shared memory unit is taken as the capacity of the shared memory unit.

In one possible implementation, the construction of the inter-core channels, such as the configuration of the first interrupt register and the second interrupt register, and the shared memory capacity, the configuration of the start address, whether the memory is further partitioned, etc., may be configured by the application processor during the startup of the processor architecture. Furthermore, the application processor may further configure a one-to-one correspondence between the peripheral controller and the inter-core channel, and as for a specific configuration manner of the correspondence, the specific configuration process may be implemented with reference to a related technology, which is not limited by the present application.

Of course, the inter-core communication module may be created in the IOP by other means, so as to allocate a corresponding inter-core channel to each peripheral controller, and any implementation manner capable of implementing the functions of the inter-core communication module described in the following description of the present application is optional, which falls within the scope of protection of the present application on the premise of not exceeding the core idea of the present application.

Based on the inter-core communication module shown in fig. 3, the application provides a device control method, through which the function of the IOP as a data interaction intermediate can be fully exerted, so that an application processor can access a peripheral controller through the IOP, and further control external devices. Referring to fig. 4, the apparatus control method provided in this embodiment includes the following steps.

S100, the application processor stores the request data in the target inter-core channel.

The processor architecture provided by the application comprises at least one peripheral controller, and in practical application, each peripheral controller can be used for controlling a corresponding external device, and the inter-core communication module comprises at least one inter-core channel, and the inter-core channels are in one-to-one correspondence with the peripheral controllers, namely, each peripheral controller is provided with one inter-core channel. For the application processor, the one-to-one correspondence between the inter-core channels and the peripheral controller is already known before the request data is sent.

Based on the above, the peripheral controller to be accessed by the application processor is taken as a target peripheral controller, and correspondingly, the inter-core channel corresponding to the target peripheral controller is taken as a target inter-core channel. When the application processor needs to access the target peripheral controller to control the corresponding external device, the request data is stored in the target inter-core channel.

In the case where the inter-core channel adopts the implementation manner shown in fig. 3, the application processor stores the request data in the shared storage unit of the target inter-core channel, and since the shared storage unit can only store one frame of request data, in practical application, the application processor stores one frame of request data in the shared storage unit of the target inter-core channel. As described above, in the case where the shared memory unit is further divided into the first shared memory subunit and the second shared memory subunit, the application processor stores one frame of request data in the first shared memory subunit of the target inter-core channel. It will be appreciated that when storing the requested data in the shared memory unit, the size of the requested data naturally cannot exceed the capacity of the shared memory unit (or the first shared memory subunit), which would otherwise potentially result in the loss of data information.

In an alternative embodiment, before storing the request data in the shared memory unit of the target inter-core channel, the application processor may first determine whether the shared memory unit is occupied, and store the request data in the shared memory unit of the target inter-core channel if the shared memory unit is unoccupied; conversely, if the shared memory unit of the target inter-core channel is occupied, the application processor may temporarily cancel the transmission of the request data and resume transmitting the request data if the shared memory unit is restored to be unoccupied.

S110, triggering a first interrupt signal by the application processor.

After storing the request data in the shared memory location of the target inter-core channel, the application processor triggers a first interrupt signal by which the processor core of the IOP is triggered to retrieve the request data. Specifically, in the case of using the inter-core channel shown in fig. 3, the application processor writes a target value, such as 1, in the first interrupt register of the target inter-core channel to trigger the first interrupt signal. Of course, other values capable of triggering the first interrupt signal may be written into the first interrupt register, which will not be described in detail herein, and the present application is also within the scope of protection of the present application without exceeding the core concept of the present application.

In one possible implementation, after triggering the first interrupt signal, the application processor exits the current request data transmission process, and performs the transmission of the next frame of request data or performs other application layer tasks, where the application processor operates in an asynchronous mode. It can be understood that, in the case of operating in the asynchronous mode, the application processor performs other tasks after sending a frame of request data, and is suitable for application scenarios with high requirements on the working efficiency.

In another possible implementation manner, after triggering the first interrupt signal, the application processor continues to wait to acquire the data fed back by the processor core until the response data fed back by the processor core is reached, and then sends the next frame of request data or performs other tasks, where the application processor operates in the synchronous mode. It can be appreciated that, in the case of operating in the synchronous mode, the application processor continuously waits for the response data fed back by the processor core, so that the response data can be acquired at the first time, and the method is suitable for an application scenario in which the response data needs to be processed in time.

S120, the processor core responds to the first interrupt signal to acquire the request data in the inter-core channel.

The processor core of the IOP acquires a first interrupt signal triggered by the application processor, and responds to the acquired first interrupt signal, accesses the shared memory unit in the target inter-core channel and acquires the request data in the shared memory unit. As described above, the inter-core communication module may include a plurality of inter-core channels, and after the processor core receives the first interrupt signal, how to determine the target inter-core channel corresponding to the first interrupt signal is a key for correctly acquiring the request data. In one possible implementation manner, the inter-core channels correspond to different interrupt identifiers, such as interrupt signal numbers, based on which, after the first interrupt signal is acquired, the target interrupt identifier of the first interrupt signal is extracted, and then, based on the correspondence between the interrupt identifier and the inter-core channel, the target inter-core channel corresponding to the target interrupt identifier can be determined in each inter-core channel, so as to acquire the request data in the target inter-core channel.

Based on the inter-core channel shown in fig. 3, in the case that the shared memory unit is further divided into a first shared memory subunit and a second shared memory subunit, the processor core obtains one frame of request data in the first shared memory subunit; correspondingly, in the case that the shared memory unit is not further divided, the processor core may directly acquire one frame of request data stored in the shared memory unit.

S130, the processor core accesses the target peripheral controller according to the request data and acquires corresponding response data.

It will be appreciated that in practical applications, the type of request data may be various, and the access operations that the processor core needs to perform may vary, based on which the processor core needs to access the target peripheral controller according to the request data after obtaining the request data.

In an alternative embodiment, the processor core directly accesses a preset register in the target peripheral controller according to the request data, for example, writes the request data into the preset register of the target peripheral controller, or performs corresponding control operation on the target peripheral controller based on the request data, where the target peripheral controller controls the external device connected to itself based on the obtained request data or the corresponding control operation, and may also obtain feedback data uploaded by the external device, and generate corresponding response data according to the obtained feedback data by the target peripheral controller and store the response data in the preset register. In this case, the processor core directly accesses a preset register of the target peripheral controller, and thus obtains the response data. For specific implementation of the processor core to perform different access operations on the target peripheral controller according to the specific type of the request data, reference may be made to the related art, which is not described in detail herein.

In another possible implementation manner, the processor core only sends request data to the target peripheral controller, the target peripheral controller controls the external device connected with the processor core according to the obtained request data and obtains feedback data uploaded by the external device, further, the target peripheral controller triggers a third interrupt signal after generating corresponding response data according to the feedback data, and the processor core responds to the third interrupt signal and obtains the response data recorded by a preset register in the target peripheral controller. It should be noted that, the response data described in this embodiment may include not only the communication data related to the control process, but also abnormal status, mislabel, etc. of the external device or the target peripheral controller, and in any case, any information that needs to interact between the processor core and the external device may be used as the response data described in this application. It can be appreciated that the peripheral controller actively triggers the interrupt signal to drive the processor core to acquire the response data, which is helpful for improving the data interaction efficiency between the processor core and the peripheral controller.

And S140, the processor core stores the response data in the target inter-core channel and triggers a second interrupt signal.

Similar to the foregoing process of storing request data in the target inter-core channel by the application processor, after obtaining the response data of the peripheral controller, the processor core stores the response data in the shared memory unit of the target inter-core channel, and of course, due to the limitation of the capacity of the shared memory unit, the processor core can only store one frame of response data in the shared memory unit at a time. It will be appreciated that in the case where the shared memory unit is further divided into a first shared memory subunit and a second shared memory subunit, the processor core stores one frame of response data in the second shared memory subunit.

In an alternative embodiment, referring to the process of storing request data in the target inter-core channel by the application processor, before storing the response data in the shared storage unit of the target inter-core channel, the processor core may also first determine whether the shared storage unit is occupied, and store the response data in the shared storage unit of the target inter-core channel if the shared storage unit is unoccupied; conversely, if the shared memory location of the target inter-core channel is occupied, the processor core may temporarily cancel the transmission of the response data and resume transmitting the response data if the shared memory location is restored to be unoccupied.

Further, the processor core triggers a second interrupt signal, and the application processor is triggered to acquire the request data through the second interrupt signal. Specifically, in the case of the inter-core channel shown in fig. 3, the processor core writes a target value, such as 1, in the second interrupt register of the target inter-core channel to trigger the second interrupt signal. Of course, other values capable of triggering the second interrupt signal may be written into the second interrupt register, which will not be described in detail herein, and thus, the present application is also within the scope of protection without exceeding the core concept of the present application.

And S150, the application processor responds to the second interrupt signal to acquire response data.

The application processor acquires a second interrupt signal triggered by the processor core, accesses the target inter-core channel and acquires response data in the target inter-core channel in response to the acquired second interrupt signal. As described above, the inter-core communication module may include a plurality of inter-core channels, and after receiving the second interrupt signal, the application processor determines how to determine the target inter-core channel corresponding to the second interrupt signal is a key for correctly acquiring the response data. In one possible implementation manner, the inter-core channels correspond to different interrupt identifiers, such as interrupt signal numbers, based on which, after the second interrupt signal is acquired, the target interrupt identifier of the second interrupt signal is extracted, then, based on the correspondence between the interrupt identifier and the inter-core channel, the target inter-core channel corresponding to the target interrupt identifier can be determined in each inter-core channel, so as to acquire a frame of response data stored in the shared storage unit of the target inter-core channel. It will be appreciated that in the case where the shared memory unit is further divided into a first shared memory subunit and a second shared memory subunit, the application processor obtains one frame of response data in the second shared memory subunit.

Thus, the primary data interaction process between the application processor and the peripheral controller is completed. After the above operations are completed, the application processor may further perform other operations related to controlling the operation of the external device based on the extracted response data, which will not be described in detail herein, and may be implemented in conjunction with the related art.

In another alternative embodiment, an inter-core communication module as shown in FIG. 5 may also be built based on memory and register arrays in the IOP. Similar to the inter-core communication module provided in the embodiment shown in fig. 3, the inter-core communication module provided in this embodiment includes at least one inter-core channel (shown as n inter-core channels in fig. 5, where n is an integer greater than or equal to 1), each inter-core channel corresponds to one peripheral controller, and the peripheral controllers corresponding to the inter-core channels are different from each other, that is, the inter-core channels and the peripheral controllers are in a one-to-one correspondence, and in conjunction with fig. 5, the inter-core channel 1 corresponds to the peripheral controller 1, and the inter-core channel n corresponds to the peripheral controller n.

In this embodiment, the inter-core channel includes a first interrupt register and a shared memory unit. The first interrupt register is from the register array, and is used for the application processor to trigger interrupt signals, and the shared memory unit is the memory space in the memory. It should be noted that, the shared memory units in the inter-core channel provided in this embodiment may also be further divided into two or even more shared memory subunits, and the specific dividing manner may refer to the relevant content of the embodiment shown in fig. 3, which will not be repeated here. It should be further noted that, regardless of the configuration of the shared memory unit, in this embodiment, only one frame of request data and/or one frame of response data can be stored in any inter-core channel.

With reference to the foregoing, in the inter-core communication module provided in this embodiment, the construction of each inter-core channel and the configuration of the one-to-one correspondence between the peripheral controller and the inter-core communication module may be configured by the application processor during the startup process of the processor architecture. And, the inter-core communication module can be created in the IOP by other methods, so that a corresponding inter-core channel is allocated to each peripheral controller, and any implementation manner capable of realizing the functions of the inter-core communication module described in the following description of the present application is optional, and the method also falls within the scope of protection of the present application under the premise of not exceeding the core idea of the present application.

Based on the inter-core communication module shown in fig. 5, the present application provides another device control method, as shown in fig. 6, and the device control method provided in this embodiment includes the following steps.

S200, the application processor stores the request data in the target inter-core channel.

In an alternative embodiment, before storing the request data in the inter-core channel, the application processor first determines whether the inter-core channel is idle, if the inter-core channel does not store any request data or the request data stored in the inter-core channel is processed, determines that the inter-core channel is idle, stores the request data in the inter-core channel, and conversely, if the inter-core channel stores unprocessed request data, determines that the inter-core channel is not idle, and outputs notification information indicating that the data writing fails.

As to whether the request data stored in the target inter-core channel has been processed, the present application provides two marking methods, in one possible implementation, the state of the request data is recorded through a special state register, based on which the application processor accesses the state register corresponding to the target inter-core channel, and if the state register stores a target value for representing that the request data has been processed, it is determined that the request data has been processed; conversely, if the target value is not stored in the status register, it is determined that the requested data is not processed. In another possible embodiment, the request data is carried in a message, the message comprising a message header and a message body, the message body being for storing the request data, the message header being for recording a status of the request data, based on which it is determined that the request data has been processed if a target value is recorded in the message header for characterizing the request data being processed, and conversely if the target value is not recorded in the message header, it is determined that the request data has not been processed. Since the status of the request data is updated by the processor core, the specific implementation of marking whether the request data has been processed is developed in the following, and will not be described in detail here.

For other relevant details required for performing this step, reference is made to the relevant content of S100 in the embodiment shown in fig. 4, and will not be repeated here.

S210, the application processor triggers a first interrupt signal and inquires whether the request data is processed by the processor core according to a preset polling period.

After storing the request data in the shared memory location of the target inter-core channel, the application processor triggers a first interrupt signal by which the processor core of the IOP is triggered to retrieve the request data. Specifically, in the case of using the inter-core channel shown in fig. 5, the application processor writes a target value, such as 1, in the first interrupt register of the target inter-core channel to trigger the first interrupt signal. Of course, other values capable of triggering the first interrupt signal may be written into the first interrupt register, which will not be described in detail herein, and the present application is also within the scope of protection of the present application without exceeding the core concept of the present application.

It may be understood that, based on actual application requirements, the application processor may need to access multiple peripheral controllers, that is, two or more peripheral controllers, where each peripheral controller to be accessed may be used as a target peripheral controller, and request data to be sent to each target peripheral controller may be stored in a shared storage unit of a corresponding target inter-core channel of each target peripheral controller, and further, after storing the request data of each target peripheral controller in the corresponding target inter-core channel, the application processor may further write the foregoing target value into a first interrupt register in each target inter-core channel, so as to trigger multiple interrupt signals, so as to determine, in the multiple interrupt signals, a first interrupt signal that is responded first, and develop in detail in the following.

After triggering the first interrupt signal, the application processor queries whether the request data is processed by the processor core according to a preset polling period, and until the processor core obtains the request data to access the peripheral controller and writes the response data into the target inter-core channel, the application processor can not send the request data of the next frame or execute other tasks, and in this case, the application processor works in a synchronous mode, specifically a synchronous polling mode, as can be seen from the foregoing. It can be appreciated that, in the case of operating in the synchronous polling mode, the application processor continuously waits for the response data fed back by the processor core, so that the response data can be acquired at the first time, and the method is suitable for an application scenario in which the response data needs to be processed in time. As for the duration of the preset polling period, it may be determined based on the actual computing power of the processor architecture and the requirement of the data interaction efficiency, which is not particularly limited in the present application.

S220, the processor core responds to the first interrupt signal to acquire the request data in the target inter-core channel.

The processor core of the IOP acquires a first interrupt signal triggered by the application processor, and responds to the acquired first interrupt signal, accesses the shared memory unit in the target inter-core channel and acquires the request data in the shared memory unit. As described above, the inter-core communication module may include a plurality of inter-core channels, and after the processor core receives the first interrupt signal, how to determine the target inter-core channel corresponding to the first interrupt signal is a key for correctly acquiring the request data. In one possible implementation manner, the inter-core channels correspond to different interrupt identifiers, such as interrupt signal numbers, based on which, after the first interrupt signal is acquired, the target interrupt identifier of the first interrupt signal is extracted, and then, based on the correspondence between the interrupt identifier and the inter-core channel, the target inter-core channel corresponding to the target interrupt identifier can be determined in each inter-core channel, so as to acquire the request data in the shared storage unit of the target inter-core channel.

Referring to the foregoing, in the case where the shared memory unit is further divided into the first shared memory subunit and the second shared memory subunit, the processor core acquires one frame of request data in the first shared memory subunit; correspondingly, in the case that the shared memory unit is not further divided, the processor core may directly acquire one frame of request data stored in the shared memory unit.

As described above, the application processor may need to access multiple peripheral controllers, that is, two or more peripheral controllers, in this case, each peripheral controller that needs to be accessed may be used as a target peripheral controller, and after storing the request data that needs to be sent to each target peripheral controller in the shared storage unit of the corresponding target inter-core channel, the application processor further writes the target value into the first interrupt register in each target inter-core channel, so as to trigger multiple interrupt signals.

In an optional embodiment, the device control method provided by the application configures different response priorities for each peripheral controller, and when the application processor triggers a plurality of interrupt signals, that is, accesses a plurality of peripheral controllers simultaneously, the processor core determines, according to the response priorities of the peripheral controllers, the interrupt signal corresponding to the peripheral controller with the highest priority as the first interrupt signal, that is, the access request of the peripheral controller with the highest priority is processed preferentially. According to the embodiment, different response priorities are configured, so that differentiated control of the access sequence of each peripheral controller is realized, meanwhile, the peripheral controllers with high priority can be ensured to access preferentially, and the control efficiency of corresponding external equipment is improved.

S230, the processor core accesses the target peripheral controller according to the request data and acquires corresponding response data.

In an alternative embodiment, the specific implementation of this step may refer to the relevant content of S130 in the embodiment shown in fig. 4, which will not be repeated here.

S240, the processor core stores the response data in the target inter-core channel, and marks the state of the request data as processed.

In an alternative embodiment, the processor core stores the response data in the specific implementation of the target inter-core channel, which is also referred to in the embodiment of fig. 4 for S140, and will not be described here.

After storing the response data in the target inter-core channel, the processor core marks the status of the request data stored in the target inter-core channel by the application processor as processed, so that the application processor acquires the response data after determining that the request data has been processed. Referring to the relevant matters in S210, the present application provides two methods of marking the requested data state.

Specifically, in an alternative embodiment, the inter-core channel corresponding to each peripheral controller adopts the structure shown in fig. 7, that is, a status register is further provided on the basis of the inter-core channel provided by the embodiment shown in fig. 5. Based on the inter-core path shown in fig. 7, after storing the response data in the shared memory location of the target inter-core path, the processor core writes a target value indicating that the corresponding request data has been processed, i.e., marks the state of the request data as processed, in the state register of the target inter-core path. Accordingly, the application processor accesses the status register of the target inter-core channel, determines that the request data has been processed if the status register stores the target value, and determines that the request data has not been processed if the status register does not store the target value.

In another possible implementation, the application processor and the IOP agree on a data format of the two-party communication, that is, agree on a specific parameter composition of each message, and request data and response data in the interaction process are carried by the two parties through the message. Specifically, the message provided by the embodiment of the application comprises two parts, namely a message header and a message body, wherein the formats of the message header for respectively sending the message are the same for the application processor and the IOP, and the message will not be different due to different communication modes of the two parties, and the message will be different due to different specific bearing data. It should be noted that, in practical application, the request data and the response data may be divided into different parameter items, so when the message body is used to store data, a corresponding structure body is created for each parameter item, and specific parameter values of the corresponding parameter item are stored by the structure body.

Referring to fig. 8, the message header is used to carry a command number and a command execution state, where the command number corresponds to a message uniquely and is used to identify the message, the command numbers corresponding to the messages are different from each other, and the command execution state is mainly used to indicate whether the data carried in the message body has been processed, for example, the data can be represented by a first numerical value, and correspondingly, the data is represented by a second numerical value, and in practical application, the application processor or the IOP can indicate whether the corresponding message has been processed by updating the command execution state in the message header.

Based on the above, in S200, the application processor stores the message carried in the request data in the shared memory space of the inter-target-core channel, based on which, when executing this step, the processor core records the response data in the message body, the request data stored by the application processor before will be overwritten, after which the processor core further writes in the message header a target value indicating that the request data has been processed, i.e. marks the status of the request data as processed.

S250, the application processor acquires response data in any polling period.

As described above, after triggering the first interrupt signal, the application processor queries whether the request data is processed by the processor core according to the preset polling period, and if it is determined that the request data has been processed in any polling period, the application processor acquires the response data stored in the target inter-core channel by the processor core, so as to complete the data interaction process between the application processor and the peripheral controller.

After the above operations are completed, the application processor may further perform other operations related to controlling the operation of the external device based on the extracted response data, which will not be described in detail herein, and may be implemented in conjunction with the related art.

As can be seen from the execution process of the device control method provided by the foregoing embodiments, only one frame of request data or response data can be transmitted between the application processor and the IOP each time, and when a large amount of data needs to be interacted between the application processor and the IOP, the data interaction manner is obviously difficult to satisfy the actual control requirement, so that in order to further improve the data interaction efficiency between the application processor and the IOP, the present application provides another inter-core communication module, which is the same as the inter-core communication module provided in the foregoing embodiment, and the inter-core communication module provided in this embodiment also includes at least one inter-core channel, where each inter-core channel corresponds to one peripheral controller, and the peripheral controllers corresponding to the inter-core channels are different from each other, that is, the inter-core channels and the peripheral controllers are in a one-to-one correspondence.

Unlike the foregoing embodiment, in the inter-core communication module provided in this embodiment, the inter-core channel supports simultaneous transmission of multi-frame data, and as shown in fig. 9, the inter-core channel provided in this embodiment includes: the system comprises a first interrupt register, a first count register, a second count register and m first storage units, wherein m is an integer greater than or equal to 2, and the first interrupt register, the first count register, the second count register, the fourth count register and k second storage units are respectively arranged for an application processor, wherein k is an integer greater than or equal to 2. In practical application, the values of m and k may be the same or different, and the application is not limited to the specific values of m and k, mainly depending on the data concurrency processing capability of the application processor and the processor core in the IOP and the actual capacity of the memory in the IOP.

Specifically, the first interrupt register is used for triggering the interrupt signal by the application processor, the second interrupt register is used for triggering the interrupt signal by the processor core of the IOP, the first count register is used for recording the number of the request data written by the application processor to each first storage unit, the second count register is used for recording the number of the request data read by the processor core of the IOP, the third count register is used for recording the number of the response data written by the processor core of the IOP to each second storage unit, the fourth count register is used for recording the number of the response data read by the application processor, the m first storage units are used for storing the request data written by the application processor, and the k second storage units are used for storing the response data written by the processor core of the IOP. It should be noted that, for any first storage unit, only one frame of request data can be stored, and for any second storage unit, only one frame of response data can be stored.

In an optional implementation manner, the inter-core communication module provided in this embodiment is further provided with a first configuration register and a second configuration register, where the first configuration register is used for configuring capacities of the first storage unit and the second storage unit, and the second configuration register is used for configuring numbers of the first storage unit and the second storage unit, that is, for configuring specific values of m and k. In this embodiment, the capacity of any memory cell and the total number of memory cells in each inter-core channel are uniformly configured, and therefore, the actual configuration and the total capacity of each inter-core channel are identical. Furthermore, as the channels among the cores are uniformly configured, the configuration process is simple and efficient, and meanwhile, the configuration can be realized only by setting two configuration registers, and the hardware cost of the inter-core communication module is lower.

In another possible embodiment, a first configuration register and a second configuration register may also be provided for each inter-core channel in the inter-core communication module, in which case, for any inter-core channel, the capacities of the first memory unit and the second memory unit may be configured by the own first configuration register, and the numbers of the first memory unit and the second memory unit may be configured by the own second configuration register. The configuration conditions of the inter-core channels are not mutually influenced, and in practical application, the inter-core channels meeting the communication requirements of the corresponding peripheral controllers can be configured according to the data volume interacted between the application processor and the peripheral controllers, so that personalized customization of the inter-core channels is realized. Of course, since each inter-core channel needs to be separately provided with two configuration registers, this results in higher overall hardware cost of the inter-core communication module.

It will be appreciated that the inter-core channel shown in fig. 9 essentially provides a ring buffer for each peripheral controller, which can be maintained by both the application processor and the IOP, to support simultaneous transmission or reading of multi-frame data, thereby releasing resources wasted by the application processor and the processor core waiting for the inter-core channel to be idle in the IOP, and improving data interaction efficiency. Based on the above, the first storage unit 1 to the first storage unit m form a request data queue of the application processor, the second storage unit 1 to the second storage unit k form a response data queue of the IOP, the first count register is used for recording the number of data frames written into the request data queue by the application processor, namely, recording the tail pointer of the request data queue, the second count register is used for recording the number of frames requested by the IOP in the request data queue, namely, recording the head pointer of the request data queue, the third count register is used for recording the number of frames of response data written into the response data queue by the IOP, namely, recording the tail pointer of the response data queue, and the fourth count register is used for recording the number of frames responded by the response data queue processed by the application processor, namely, recording the head pointer of the response data queue.

Based on the inter-core communication module shown in fig. 9, the present application provides another device control method, as shown in fig. 10, and the device control method provided in this embodiment includes the following steps.

S300, the application processor stores each frame of request data in a first storage unit of the target inter-core channel.

With reference to the foregoing, the processor architecture provided by the present application includes at least one peripheral controller, and in practical application, the inter-core communication module includes at least one inter-core channel, where the inter-core channel corresponds to the peripheral controller one by one, that is, one inter-core channel is configured for each peripheral controller. For the application processor, the one-to-one correspondence between the inter-core channels and the peripheral controller is already known before the request data is sent.

In the application, the peripheral controller which is required to be accessed by the application processor is taken as a target peripheral controller, and correspondingly, the inter-core channel corresponding to the target peripheral controller is taken as a target inter-core channel. When the application processor needs to access the target peripheral controller to control the corresponding external device, the request data is stored in the target inter-core channel.

In one possible implementation, the application processor first determines whether the inter-core channel is idle before storing the request data to the inter-core channel, if the inter-core channel is idle, may store the request data to the inter-core channel, and conversely, if the inter-core channel is not idle, temporarily cancels storing the request data to the inter-core channel, and in case that the subsequent inter-core channel is restored to the idle state, stores the request data again to the inter-core channel.

It will be appreciated that, as shown in fig. 9, the inter-core channel is provided with a plurality of first storage units on the application processor side, based on this, if at least one first storage unit in the target inter-core channel is idle, it is determined that the target inter-core channel is idle, the application processor may store request data in the first storage unit in the idle state in the target inter-core channel, and correspondingly, if each first storage unit in the target inter-core channel is occupied, it is determined that the target inter-core channel is in a non-idle state.

Further, under the condition that the inter-core channel is idle, at least one frame of request data can be stored in the inter-core channel according to the specific number of the first storage units in the idle state in the inter-core channel and the number of frames of request data currently required to be sent by the application processor, and each first storage unit can only accommodate one frame of request data, so that the application processor needs to store each frame of request data in one first storage unit of the inter-core channel. It can be understood that, compared with the foregoing embodiment that only one frame of request data can be sent at most during each data interaction, by the device control method provided by the embodiment, the application processor is allowed to send multiple request data to the target inter-core channel at the same time, so that the time required for the application processor to wait for the inter-core channel to be idle can be saved, which is beneficial to improving the utilization rate of the application processor and improving the data interaction efficiency.

S301, the application processor counts the number of frames of the stored request data.

After the request data storage operation is completed, the application processor counts the number of frames of the request data stored in the target inter-core channel, namely counts the occupation condition of the first storage unit in the target inter-core channel, and provides a basis for judging whether the target inter-core channel is idle.

In connection with the inter-core channel architecture shown in fig. 9, the application processor updates the value of the first count register after storing at least one frame of request data in the target inter-core channel, that is, updates the tail pointer of the request data queue, so that the number of frames of the request data stored in the request data queue can be simply and directly determined by the value stored in the first count register.

S302, triggering a first interrupt signal by the application processor.

After storing the request data in the target inter-core channel, the application processor triggers a first interrupt signal by which the processor core of the IOP is triggered to acquire the request data. Specifically, in the case of using the inter-core channel shown in fig. 9, the application processor writes a target value, such as 1, in the first interrupt register of the target inter-core channel to trigger the first interrupt signal. Of course, other values capable of triggering the first interrupt signal may be written into the first interrupt register, which will not be described in detail herein, and the present application is also within the scope of protection of the present application without exceeding the core concept of the present application.

Similar to the device control method provided in the embodiment shown in fig. 4, the application processor may choose to operate in the synchronous mode or in the asynchronous mode after triggering the first interrupt signal.

In one possible implementation, after triggering the first interrupt signal, the application processor exits the current request data transmission process, and performs the transmission of the next cycle of request data or performs other application layer tasks, where the application processor operates in an asynchronous mode.

In another possible implementation manner, after triggering the first interrupt signal, the application processor continues to wait to acquire the data fed back by the processor core until the response data fed back by the processor core is reached, and then sends the next cycle request data or performs other tasks, where the application processor operates in the synchronous mode.

S303, the processor core responds to the first interrupt signal to acquire the request data in at least one first storage unit in the target inter-core channel.

The processor core of the IOP acquires a first interrupt signal triggered by the application processor, accesses the target inter-core channel and acquires the request data in response to the acquired first interrupt signal. As described above, the inter-core communication module may include a plurality of inter-core channels, and after the processor core receives the first interrupt signal, how to determine the target inter-core channel corresponding to the first interrupt signal is a key for correctly acquiring the request data. In one possible implementation manner, the inter-core channels correspond to different interrupt identifiers, such as interrupt signal numbers, based on which, after the first interrupt signal is acquired, the target interrupt identifier of the first interrupt signal is extracted, and then, based on the correspondence between the interrupt identifier and the inter-core channel, the target inter-core channel corresponding to the target interrupt identifier can be determined in each inter-core channel, so as to acquire the request data in the target inter-core channel.

As mentioned above, the application processor may store at least one frame of request data in the request data queue of the inter-core channel, and correspondingly, when the processor core obtains the request data in the request data queue, the processor core may also obtain the request data in at least one first storage unit in the request data queue according to the actual number of the request data in the request data queue and the current data processing capability of the processor core. Compared with the embodiment, the device control method provided by the embodiment allows the processor core to acquire a plurality of request data simultaneously, so that the time required by the processor core to repeatedly acquire the request data and interact with the peripheral controller one by one can be saved, the utilization rate of the processor core can be improved, and the data interaction efficiency can be improved.

S304, the processor core counts the number of frames of the extracted request data.

After the request data acquisition operation is completed, the processor core counts the number of frames of the extracted request data, and similarly to the effect of counting the number of frames of the request data stored in the target inter-core channel, the processor core can also be used for determining the occupation condition of the first storage unit in the target inter-core channel by counting the number of frames of the extracted request data, so that a basis is provided for judging whether the target inter-core channel is idle.

In connection with the inter-core channel architecture shown in fig. 9, after at least one frame of request data is extracted, the processor core updates the value of the second count register, that is, updates the head pointer of the request data queue, so that the number of frames of the extracted request data in the request data queue can be simply and directly determined through the value stored in the second count register.

S305, the processor core accesses the target peripheral controller according to the request data and acquires corresponding response data.

It should be noted that, unlike the foregoing embodiment S130, if the processor core acquires the multi-frame request data in S304, when executing this step, the specific number and specific type of the request data may be combined, and at least one frame of the acquired request data may be simultaneously sent to the target peripheral controller.

S306, the processor core stores each frame of response data in a second storage unit of the target inter-core channel.

Similar to the foregoing process of storing the request data in the target inter-core channel by the application processor, after obtaining the response data of the peripheral controller, the processor core stores the response data in the second storage unit of the target inter-core channel.

In one possible implementation, before storing the response data to the inter-core channel, the processor core first determines whether the inter-core channel is idle, if the inter-core channel is idle, the response data may be stored to the inter-core channel, and conversely, if the inter-core channel is not idle, the storing of the response data to the inter-core channel is temporarily canceled, and if the inter-core channel is subsequently restored to the idle state, the response data is stored again to the inter-core channel.

It will be appreciated that, as shown in connection with fig. 9, the inter-core channel is provided with a plurality of second storage units on the processor core side, based on this, if at least one second storage unit in the target inter-core channel is idle, it is determined that the target inter-core channel is idle, the processor core may store response data in the second storage unit in the idle state in the target inter-core channel, and correspondingly, if each second storage unit in the target inter-core channel is occupied, it is determined that the target inter-core channel is in a non-idle state.

Further, under the condition that the inter-core channel is idle, at least one frame of response data can be stored in the inter-core channel according to the specific number of the second storage units in the idle state in the inter-core channel and the number of frames of response data currently required to be sent by the processor core. It can be understood that, compared with the foregoing embodiment that only one frame of response data can be sent at most during each data interaction, by the device control method provided by the embodiment, the processor core is allowed to send a plurality of response data to the target inter-core channel at the same time, so that the time required for the processor core to wait for the inter-core channel to be idle can be saved, which is beneficial to improving the utilization rate of the processor core and improving the data interaction efficiency.

S307, the processor core counts the number of frames of the stored response data.

After the response data storage operation is completed, the processor core counts the number of frames of the response data stored in the target inter-core channel, namely counts the occupation condition of the second storage unit in the target inter-core channel, and provides a basis for judging whether the target inter-core channel is idle.

In connection with the inter-core channel architecture shown in fig. 9, after storing at least one frame of response data in the target inter-core channel, the processor core updates the value of the third count register, that is, updates the tail pointer of the response data queue, so that the frame number of the response data stored in the response data queue can be simply and directly determined by the value stored in the third count register.

S308, triggering a second interrupt signal by the processor core.

After storing the response data in the target inter-core channel, the processor core triggers a second interrupt signal, and the application processor is triggered to acquire the response data through the second interrupt signal. Specifically, in the case of the inter-core channel shown in fig. 9, the processor core writes a target value, such as 1, in the second interrupt register of the target inter-core channel to trigger the second interrupt signal. Of course, other values capable of triggering the second interrupt signal may be written into the second interrupt register, which will not be described in detail herein, and thus, the present application is also within the scope of protection without exceeding the core concept of the present application.

S309, the application processor responds to the second interrupt signal to acquire response data in at least one second storage unit in the target inter-core channel.

The application processor acquires a second interrupt signal triggered by the processor core, and accesses the target inter-core channel and acquires response data in response to the acquired second interrupt signal. In one possible implementation manner, the inter-core channels correspond to different interrupt identifiers, such as interrupt signal numbers, based on which, after the application processor acquires the second interrupt signal, the application processor extracts the target interrupt identifier of the second interrupt signal, and then, based on the correspondence between the interrupt identifier and the inter-core channel, the target inter-core channel corresponding to the target interrupt identifier can be determined in each inter-core channel, so as to acquire response data in the target inter-core channel.

As described above, the processor core may store at least one frame of response data in the response data queue of the inter-core channel, and correspondingly, when the application processor acquires the response data in the response data queue, the application processor may also acquire the response data in at least one second storage unit in the response data queue according to the actual number of the response data in the response data queue and the current data processing capability of the application processor. Compared with the embodiment, the device control method provided by the embodiment allows the application processor to acquire a plurality of response data simultaneously, so that the time required for the application processor to acquire the response data one by one can be saved, the utilization rate of the application processor can be improved, and the data interaction efficiency can be improved.

S310, the application processor counts the number of frames of the extracted response data.

After the response data acquisition operation is completed, the application processor counts the number of frames of the extracted response data, and similarly to the effect of counting the number of frames of the response data stored in the inter-core channel of the target, the application processor can also be used for determining the occupation condition of the second storage unit in the inter-core channel of the target by counting the number of frames of the extracted response data, so that a basis is provided for judging whether the inter-core channel of the target is idle.

In connection with the inter-core channel architecture shown in fig. 9, the application processor updates the value of the fourth count register after extracting at least one frame of response data, that is, updates the head pointer of the response data queue, so that the number of frames of the extracted response data in the response data queue can be simply and directly determined through the value stored in the fourth count register.

It will be appreciated that after the above operations are completed, the application processor may further perform other operations related to controlling the operation of the external device based on the extracted response data, which will not be described in detail herein, and may be implemented in conjunction with the related art.

It should be noted that, in the foregoing embodiments, the concepts of the shared memory unit, the first memory unit, and the second memory unit are respectively related to the concepts of the shared memory unit, the first memory unit, and the second memory unit, where the nature of these memory units is the same, and the memory units are all corresponding to the memory space with a preset capacity in the memory of the IOP, as described above, the specific capacity of the memory space may be configured by the application processor in the boot stage of the processor architecture, so that, as an optional implementation, the inter-core channel provided by the present application is obtained by combining the memory space of the memory and the registers in the register array, and is not independent physical hardware, and of course, the inter-core channel capable of implementing the foregoing functions may also be created by providing independent physical hardware, which is within the scope of the present application without exceeding the core concept of the present application.

Based on the above-mentioned related content of each embodiment, the device control method provided by the application integrates the input/output processor in the processor architecture, the input/output processor is used as an intermediate medium when the application processor interacts with the peripheral controllers, and further, the control of the corresponding external devices is realized through each peripheral controller, for the application processor, the application processor can realize the control of the external devices only by communicating with the processor core, compared with the prior art that the application processor accesses the corresponding peripheral controller through executing the driving program, the peripheral controller adjustment and the driving program adjustment caused by the peripheral controller are synchronously updated together with the application processor, any peripheral controller change can be realized by the method without affecting the application processor, only the internal driving of the processor core needs to be adjusted, the differentiated configuration of the peripheral controller is minimized for the application processor, thereby, the influence of the peripheral controller on the application processor is reduced to the greatest extent, the verification before the silicon is avoided, the manpower and material resources are saved, and the system design period is shortened.

Further, compared with the prior art, for the application processor, each preset register in each peripheral controller is invisible, when the external device is controlled, the application processor only needs to interact data with the IOP, and does not need to know the specific configuration of each peripheral controller, which is equivalent to providing a software encapsulation interface for the preset register of each peripheral controller, and the application processor only needs to access the software encapsulation interface to realize the control of the corresponding external device.

It may be appreciated that in the device control method provided in the foregoing embodiments, the data interaction process is triggered by the application processor, that is, the application processor initiates transmission of the request data, and the peripheral controller feeds back the response data through the input/output processor after receiving the corresponding request data, which may be regarded as a downlink data communication process from the application processor to the peripheral controller. In practical applications, the peripheral controller may also actively feed back the upload data to the application processor, that is, the peripheral controller actively initiates data transmission, and the process of uploading data to the application processor by the peripheral controller may be understood as an uplink data communication process, compared with the downlink data communication process corresponding to the foregoing embodiment.

Based on this, the present application also provides a device control method for uplink data transmission, and it should be noted that the device control method for uplink data transmission provided by the present application may be applied to the inter-core communication module provided by any one of the foregoing processor architectures, and the specific implementation of the device control method provided by the present embodiment is described below by taking the inter-core communication module provided by the embodiment shown in fig. 3 as an example.

Referring to fig. 11, the apparatus control method provided in this embodiment includes the following steps.

And S400, the processor core responds to the fourth interrupt signal to acquire data to be uploaded of the peripheral controller.

In the actual running process, the peripheral controller needs to actively feed back the uploading data to the application processor, for example, actively update the state information of the peripheral controller, feed back the user operation information, feed back the necessary data collected based on the device function, and the like, and of course, other situations that the peripheral controller needs to actively feed back the data to the application processor are also possible, and the situation is not listed here. In these cases, after the peripheral controller is ready to upload data that needs feedback, the peripheral controller may store the data to be uploaded in the foregoing preset register, and then the peripheral controller sends a fourth interrupt signal to the processor core of the input/output processor to characterize that the data needs to be uploaded to the application processor. As for the specific implementation manner of triggering the fourth interrupt signal by the peripheral controller, the implementation manner may be referred to the related art, which is not limited in the present application.

And the processor core of the input/output processor responds to the fourth interrupt signal and accesses a preset register of the peripheral controller to acquire corresponding data to be uploaded. As previously mentioned, the processor architecture includes at least one peripheral controller, and in the case where the processor architecture includes a plurality of peripheral controllers, it is necessary for the processor core to distinguish between the specific sources of the fourth interrupt signal. As an optional implementation manner, the peripheral controllers correspond to different interrupt identifiers, such as interrupt signal numbers, based on which, after the processor core acquires the fourth interrupt signal, the processor core extracts the target interrupt identifier of the fourth interrupt signal, and then, based on the correspondence between the interrupt identifier and the peripheral controller, the peripheral controller corresponding to the target interrupt identifier can be determined in the peripheral controllers, so as to acquire the data to be uploaded stored in the preset register of the peripheral controller.

And S410, the processor core stores the data to be uploaded to an inter-core channel corresponding to the peripheral controller.

As described above, in the processor architecture provided by the present application, the inter-core channels in the inter-core communication module are in one-to-one correspondence with the peripheral controllers, and based on this, after the processor core obtains the data to be uploaded, the data to be uploaded is stored in the inter-core channel corresponding to the peripheral controllers. In the case of the inter-core channel shown in fig. 3, the processor core specifically stores the data to be uploaded into the shared memory unit of the inter-core channel.

S420, the processor core sends a fifth interrupt signal.

After the data uploading is stored, the processor core sends out a fifth interrupt signal. With reference to the triggering process of the second interrupt signal, the processor core writes a target value, such as 1, in the second interrupt register of the inter-core channel to trigger the fifth interrupt signal. Of course, other values capable of triggering the fifth interrupt signal may be written into the second interrupt register, which will not be described in detail herein, and are also within the scope of the present application without exceeding the core concept of the present application.

And S430, the application processor responds to the fifth interrupt signal to acquire the data to be uploaded of the peripheral controller.

The application processor acquires a fifth interrupt signal triggered by the processor core, and responds to the acquired fifth interrupt signal, accesses an inter-core channel corresponding to the peripheral controller and acquires data to be uploaded in the inter-core channel. In a possible implementation manner, the inter-core channels correspond to different interrupt identifiers, such as interrupt signal numbers, based on which, after the fifth interrupt signal is acquired, the target interrupt identifier of the fifth interrupt signal is extracted, then, based on the correspondence between the interrupt identifier and the inter-core channel, the inter-core channel corresponding to the target interrupt identifier can be determined in each inter-core channel, so as to acquire the data to be uploaded stored in the shared storage unit of the inter-core channel.

So far, the interaction process that the peripheral controller uploads data to the application processor is completed. After the above operations are completed, the application processor may further perform other operations related to controlling the operation of the external device based on the extracted data, which will not be described in detail herein, and may be implemented in conjunction with the related art.

Furthermore, the present application also provides another device control method for uplink data transmission, and the device control method provided by the present application is equally applicable to the inter-core communication module provided by any of the foregoing embodiments of the processor architecture, and the specific implementation of the device control method provided by this embodiment is described below by taking the inter-core communication module provided by the embodiment shown in fig. 3 as an example.

Referring to fig. 12, the apparatus control method provided by the present embodiment includes the following steps.

S500, the processor core responds to the fourth interrupt signal to acquire data to be uploaded of the peripheral controller.

In an alternative implementation, S500 may be implemented with reference to the relevant content of S400 in the embodiment shown in fig. 11, which will not be repeated here.

S510, the processor core stores the data to be uploaded to an inter-core channel corresponding to the peripheral controller.

In an alternative implementation, S510 may be implemented with reference to the relevant content of S410 in the embodiment shown in fig. 11, which is not described herein.

S520, the application processor acquires data to be uploaded stored in an inter-core channel corresponding to each peripheral controller in any polling period.

The application processor inquires whether the inter-core channels corresponding to the peripheral controllers store data to be uploaded according to a preset polling period, and if the fact that the inter-core channels store the data to be uploaded is determined in any polling period, the data to be uploaded in the corresponding inter-core channels is obtained, so that the process that the peripheral controllers upload the data to the application processor is completed.

After the above operations are completed, the application processor may further perform other operations related to controlling the operation of the external device based on the extracted data, which will not be described in detail herein, and may be implemented in conjunction with the related art.

In combination with the foregoing and as shown in fig. 1, there may be a plurality of peripheral controllers supporting the same standard in the processor architecture, and in this case, the peripheral controllers are from different chip suppliers, taking the peripheral controllers supporting the UART standard as an example, compared with the driver program required to be configured for each peripheral controller in the prior art, the application processor can implement data interaction with each peripheral controller supporting the UART standard by using the device control method provided by the present application and using IOP as an intermediate medium, but does not need to configure the driver program of each peripheral controller, and it is to be understood that in this case, the device control method provided by the present application, that is, the driver program for implementing data interaction with each peripheral controller supporting the UART standard can be defined as a standard driver program in practical application. Based on the above, the processor architecture supports several standards, and several standard drivers can be configured according to the device control method provided by the application, namely, the controller supporting the same standard only needs to configure one driver, the application processor can access the peripheral controllers supporting the corresponding standard by directly calling each standard driver, and the difference between different peripheral controllers supporting the same standard is processed by setting different drivers by the IOP, the change of the peripheral controllers only has an influence on the IOP, the application processor almost does not need to make any adjustment or only needs to make small adjustment, the difference between the peripheral controllers is almost invisible to the application processor, and the difference between the peripheral controllers naturally does not have an influence on the application processor.

It should be noted that the technical features of the device control method provided in each of the above embodiments may be combined with or replaced by other embodiments, alone or in combination, so as to obtain more feasible device control methods.

Further, the present application also provides a computer device, including: at least one external device and a processor architecture as provided by the foregoing embodiments, wherein,

In some embodiments, the present embodiment further provides a computer readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a usb disk, an SD (Secure Digital Memory Card, secure digital Card) Card, an MMC (Multimedia Card) Card, or the like, in which one or more instructions for implementing the foregoing steps are stored, where the one or more instructions are executed by one or more processors, and cause the processors to perform the foregoing device control method. For a related implementation, refer to the foregoing description, which is not repeated herein.

In addition to the methods and apparatus described above, embodiments of the application may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform steps in an apparatus control method according to various embodiments of the application described in the foregoing of the specification.

The computer program product may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.

Those skilled in the art will appreciate that various modifications and improvements can be made to the disclosure. For example, the various devices or components described above may be implemented in hardware, or may be implemented in software, firmware, or a combination of some or all of the three.

Further, while the present disclosure makes various references to certain elements in a system according to embodiments of the present disclosure, any number of different elements may be used and run on a client and/or server. The units are merely illustrative and different aspects of the systems and methods may use different units.

A flowchart is used in this disclosure to describe the steps of a method according to an embodiment of the present disclosure. It should be understood that the steps that follow or before do not have to be performed in exact order. Rather, the various steps may be processed in reverse order or simultaneously. Also, other operations may be added to these processes.

Those of ordinary skill in the art will appreciate that all or a portion of the steps of the methods described above may be performed by a computer program that instructs associated hardware, and that the program may be stored on a computer readable storage medium, such as a read only memory, etc. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module/unit in the above embodiment may be implemented in the form of hardware, or may be implemented in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The foregoing is illustrative of the present disclosure and is not to be construed as limiting thereof. Although a few exemplary embodiments of this disclosure have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. It is to be understood that the foregoing is illustrative of the present disclosure and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The disclosure is defined by the claims and their equivalents.

Claims

1. A device control method, characterized in that it is applied to a processor architecture, the processor architecture includes an application processor, an input-output processor and at least one peripheral controller, the input-output processor serves as an intermediate medium when the application processor interacts with the at least one peripheral controller, the input-output processor includes at least one dedicated processor core and an inter-core communication module, the inter-core communication module includes at least one inter-core channel, and the inter-core channel corresponds to the peripheral controller one-to-one, the processor core is respectively connected to each of the peripheral controllers, and the method includes the following steps performed by the processor core:

Obtaining a first interrupt signal, where the first interrupt signal is triggered after the application processor stores the request data in a target inter-core channel, where the target inter-core channel corresponds to a target peripheral controller that the application processor needs to access;

In response to the first interrupt signal, obtaining the requested data in the target inter-core channel;

Accessing the target peripheral controller according to the request data and obtaining corresponding response data;

The response data is stored in the target inter-core channel, and a second interrupt signal is triggered, where the second interrupt signal is used to trigger the application processor to obtain the response data.

2. The method according to claim 1, characterized in that the inter-core channel includes a shared storage unit, and the shared storage unit is used to store a frame of request data;

Obtaining the request data in the target inter-core channel includes:

A frame of request data stored in a shared storage unit of the target inter-core channel is obtained.

3. The method according to claim 1, characterized in that the inter-core channel comprises a plurality of first storage units corresponding to the application processor, each of the first storage units being used to store a frame of request data;

Obtaining the request data in the target inter-core channel includes:

Acquire request data in at least one first storage unit among a plurality of first storage units of the target inter-core channel;

Counts the number of frames of requested data that have been extracted.

4. The method according to claim 1, characterized in that the inter-core channel comprises a plurality of second storage units corresponding to the input and output processors, each of the second storage units being used to store a frame of response data;

Storing the response data in the target inter-core channel comprises:

storing each frame response data in one of the second storage units of the target inter-core channel;

Count the number of frames of stored response data.

5. The method according to claim 1, wherein accessing the target peripheral controller according to the request data and obtaining corresponding response data comprises:

Acquire the response data recorded in the preset register;

or,

Sending the request data to the target peripheral controller to trigger the target peripheral controller to output a third interrupt signal;

In response to the third interrupt signal, response data recorded in a preset register in the target peripheral controller is acquired.

6. The method according to claim 1, characterized in that the method further comprises:

In response to a fourth interrupt signal, acquiring data to be uploaded by the peripheral controller, wherein the fourth interrupt signal is triggered by the peripheral controller when data needs to be uploaded to the application processor;

The data to be uploaded is stored in the inter-core channel corresponding to the peripheral controller;

A fifth interrupt signal is sent to trigger the application processor to obtain the data to be uploaded.

7. A device control method, characterized in that it is applied to a processor architecture, the processor architecture includes an application processor, an input-output processor and at least one peripheral controller, the input-output processor serves as an intermediate medium when the application processor interacts with the at least one peripheral controller, the input-output processor includes at least one dedicated processor core and an inter-core communication module, the inter-core communication module includes at least one inter-core channel, and the inter-core channel corresponds to the peripheral controller one-to-one, the processor core is respectively connected to each of the peripheral controllers, and the method includes the following steps performed by the application processor:

storing the request data in a target inter-core channel, where the target inter-core channel corresponds to a target peripheral controller that the application processor needs to access;

triggering a first interrupt signal, wherein the first interrupt signal is used to trigger the processor core to access the target peripheral controller according to the request data, and output a second interrupt signal after storing the corresponding response data in the target inter-core channel;

In response to the second interrupt signal, the response data is acquired.

8. The method according to claim 7, characterized in that the inter-core channel includes a shared storage unit, and the shared storage unit is used to store a frame of request data;

The storing of the request data in the target inter-core channel comprises:

A frame of request data is stored in a shared storage unit of the target inter-core channel.

9. The method according to claim 7, characterized in that the inter-core channel comprises a plurality of first storage units corresponding to the application processor, each of the first storage units being used to store a frame of request data;

The storing of the request data in the target inter-core channel comprises:

storing each frame request data in one of the first storage units of the target inter-core channel;

Count the number of frames of stored request data.

10. The method according to claim 7, characterized in that the inter-core channel further comprises a plurality of second storage units corresponding to the input and output processors, each of the second storage units being used to store a frame of response data;

Obtain the response data, including:

Acquire response data in at least one second storage unit among a plurality of second storage units of the target inter-nuclear channel;

Counts the number of frames of extracted response data.

11. The method according to claim 7, characterized in that the method further comprises: creating the inter-core communication module during the startup phase of the processor architecture;

And, a one-to-one correspondence between the peripheral controller and the inter-core channel is configured.

12. The method according to claim 7, characterized in that the method further comprises:

In response to a fifth interrupt signal, data to be uploaded of the peripheral controller is obtained, wherein the fifth interrupt signal is triggered after the processor core stores the data to be uploaded in an inter-core channel corresponding to the peripheral controller.

13. A processor architecture, comprising: an application processor, an input/output processor, and at least one peripheral controller, wherein:

The input-output processor acts as an intermediary when the application processor interacts with the at least one peripheral controller;

The input-output processor includes at least one dedicated processor core and an inter-core communication module, the inter-core communication module includes at least one inter-core channel, and the inter-core channel corresponds to the peripheral controller one by one;

The processor core is respectively connected to each of the peripheral controllers for communication;

Any of the peripheral controllers is used to control an external device connected to the peripheral controller;

The processor core is used to execute the device control method according to any one of claims 1 to 6;

The application processor is used to execute the device control method according to any one of claims 7 to 12.

14. A computer device, comprising: at least one external device and the processor architecture according to claim 13, wherein:

The processor architecture is respectively connected to each of the external devices for communication.