CN119011074B

CN119011074B - A universal input/output interface oversampling circuit and method

Info

Publication number: CN119011074B
Application number: CN202410880561.9A
Authority: CN
Inventors: 魏云蛟; 文翰
Original assignee: Yutaiwei Shanghai Electronics Co ltd
Current assignee: Yutaiwei Shanghai Electronics Co ltd
Filing date: 2024-07-02
Publication date: 2025-10-14
Anticipated expiration: 2044-07-02

Abstract

The invention provides an oversampling circuit and method of a general input/output interface, belonging to the technical field of communication, and comprising a receiving channel connected between an input/output interface group and peripheral equipment, wherein the oversampling circuit comprises a sampling unit, an adding unit and a packaging unit, wherein the sampling unit is used for sampling a plurality of general input/output signals of the input/output interface group to obtain effective load data, the adding unit is used for adding cyclic redundancy check sum message count into the effective load data to obtain effective load data with cyclic redundancy check sum message count, and the packaging unit is used for packaging the effective load data with cyclic redundancy check sum message count into a data packet with a preset format and sending the data packet to the peripheral equipment. The method has the beneficial effects that the method is realized aiming at oversample modes in the protocol, and an implementation scheme is provided, so that the general input and output signals are effectively sampled and processed, and the reliability and the accuracy of data are improved.

Description

Oversampling circuit and method for universal input/output interface

Technical Field

The present invention relates to the field of communications technologies, and in particular, to an oversampling circuit and method for a universal input/output interface.

Background

With the development of assisted driving and automatic driving, the number of cameras and display screens on automobiles is increasing. There is currently no clear standardized solution between the car manufacturer and the supplier to achieve a high speed interface between the camera and the ECU. In order to meet the needs of the automotive industry for high speed, low latency, functional safety, light weight, low power consumption, and required economies of scale, the mobile industry processor interface (Mobile Industry Processor Interface, MIPI) alliance has proposed a unified in-vehicle connection specification protocol stack.

A-PHY Protocol Adaptation Layer Specification for GPIO, A-PHYPAL GPIO (hereinafter referred to as protocol) is a protocol disclosed by MIPI alliance in month 9 of 2020. The protocol specifies the automotive physical layer (A-PHY) general purpose input/output interface (A-PHY GENERAL-input/output, A-PHY GPIO) protocol adaptation layer (ProtocolAdaptation Layer, PAL) and requires support of GPIO channels on the A-PHY. The protocol requires that the GPIO signal pattern received at the local side be the same as the signal pattern generated at the remote side and mentions two modes of implementation, an oversampling (oversample) mode and an event (event) mode.

As an emerging protocol, the implementation of the protocol is very limited in the market at present, and specific implementation details are not mentioned in the protocol, the specification is rough, and a great deal of technical blank exists.

Disclosure of Invention

In order to solve the technical problems, the invention provides an oversampling circuit and an oversampling method for a universal input/output interface.

The technical problems solved by the invention can be realized by adopting the following technical scheme:

A first aspect of the present invention provides an oversampling circuit for a universal input-output interface, comprising a transmit channel coupled between a set of input-output interfaces and a peripheral device, the transmit channel comprising:

The sampling unit is connected with the input/output interface group and is used for sampling a plurality of general input/output signals of the input/output interface group to obtain effective load data;

an adding unit, connected to the sampling unit, for adding the cyclic redundancy check sum message count to the payload data to obtain payload data with the cyclic redundancy check sum message count;

And the packing unit is respectively connected with the adding unit and the peripheral equipment, and is used for packing the payload data with the cyclic redundancy check sum message count into a data packet with a preset format and sending the data packet to the peripheral equipment.

Preferably, the sampling unit includes:

A first sampling module, configured to sample the plurality of general input/output signals based on a plurality of consecutive sampling periods;

Each sampling period comprises a first preset number of state groups, each state group comprises a second preset number of states, and each state corresponds to a state mask;

wherein the product of the first preset number and the second preset number is a multiple of the bits of one payload page, and the status masks are all 1.

Preferably, the sampling unit further comprises:

the second sampling module is used for sampling the plurality of general input and output signals when a preset sampling triggering condition is met;

the preset sampling triggering condition is that at least one general input/output signal is judged to be a rising edge when the first sampling point of each sampling period is used.

Preferably, the sampling unit further comprises:

a third sampling module, configured to sample the plurality of general input/output signals according to a preset sampling logic;

the preset sampling logic samples a plurality of general input/output signals once every third preset number of chip clocks.

Preferably, the third preset number is a ratio of a chip clock frequency to a general input/output sampling frequency.

Preferably, a payload page is used as a carrier for carrying the payload data in the data packet;

the sampling unit further comprises a storage module for storing the payload data into the payload page.

Preferably, the storage module includes:

A first shift register for shift-storing the payload data into the payload page.

Preferably, the peripheral device further comprises a receiving channel connected between the input/output interface group and the peripheral device, and the receiving channel comprises:

The verification unit is connected with the peripheral equipment and used for acquiring the data packet from the peripheral equipment, analyzing the data packet and verifying the cyclic redundancy check sum message count to obtain the payload data;

The analysis unit is connected with the verification unit and is used for analyzing the effective load data to obtain an analysis result;

And the control unit is connected with the analysis unit and is used for generating corresponding control signals according to the analysis result and transmitting the control signals to the input/output interface group.

The parsing unit includes:

And the second shift register is used for resolving the payload data from the payload page by adopting a shift operation mode to obtain the resolving result.

A second aspect of the present invention provides an oversampling method for a universal input/output interface, applied to an oversampling circuit of the universal input/output interface, where the transmitting channel includes the following steps:

sampling a plurality of general input/output signals of the input/output interface group to obtain effective load data;

Adding a cyclic redundancy check sum message count to the payload data to obtain payload data with the cyclic redundancy check sum message count;

And packaging the payload data with the cyclic redundancy check sum message count into a data packet with a preset format, and sending the data packet to the peripheral equipment.

The technical scheme of the invention has the advantages that:

The over-sampling circuit is realized aiming at oversample modes in a protocol, and provides an implementation scheme, a transmitting channel samples a plurality of general input and output signals of an input and output interface group through a sampling unit, cyclic redundancy check and message counting are added into effective load data through an adding unit to ensure the integrity and accuracy of the data, and finally the data is packaged according to a preset format through a packaging unit and sent to peripheral equipment for further processing, so that the general input and output signals are effectively sampled and processed, and the reliability and accuracy of the data are improved.

Drawings

FIG. 1 is a block diagram of an over-sampling circuit transmit channel of a general purpose input/output interface in accordance with a preferred embodiment of the present invention;

FIG. 2 is a schematic diagram of an aggregate waveform of three general purpose input/output signals in the prior art;

FIG. 3 is a schematic diagram of 16-bit payload data in the prior art;

FIG. 4 is a block diagram showing a structure of a sampling unit according to a preferred embodiment of the present invention;

FIG. 5 is a schematic diagram of an aggregate waveform of three general purpose input/output signals according to a preferred embodiment of the present invention;

FIG. 6 is a block diagram of the transmit and receive channels of the over-sampling circuit of the general purpose input/output interface in accordance with the preferred embodiment of the present invention;

fig. 7 is a flow chart of an oversampling method of the universal input output interface in the preferred embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.

The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.

Referring to fig. 1, in accordance with the above-mentioned problems occurring in the prior art, there is now provided an oversampling circuit for a universal input/output interface, comprising a transmit channel 3 connected between an input/output interface group 1 and a peripheral device 2, the transmit channel 3 comprising:

A sampling unit 31, connected to the input/output interface group 1, for sampling a plurality of general input/output signals of the input/output interface group to obtain payload (payload) data;

An adding unit 32, connected to the sampling unit 31, for adding the cyclic redundancy check sum message count to the payload data to obtain payload data with cyclic redundancy check () and message count;

A packing unit 33 is connected to the adding unit 32 and the peripheral device 2, respectively, for packing the payload data with the cyclic redundancy check and the message count into a data packet of a predetermined format, and transmitting the data packet to the peripheral device.

Specifically, in this embodiment, the invention provides an oversampling circuit of a general purpose input/output interface, which aims at the problem that the existing emerging a-PHY PAL GPIO protocol lacks specific implementation details in an oversampling (oversample) mode, and implements the oversampling mode of the a-PHY PAL GPIO protocol, and provides an implementation scheme.

The over-sampling circuit comprises a transmit channel 3 connected between the input-output interface group 1 and the peripheral device 2, wherein the transmit channel 3 comprises a sampling unit 31, an adding unit 32 and a packing unit 33. The method comprises the steps of firstly, sampling a plurality of general input and output signals through a sampling unit 31 to obtain payload data, then, adding Cyclic Redundancy (CRC) check sum message count into the payload data through an adding unit 32 to ensure the integrity and the accuracy of the data, and finally, packaging the data output by the adding unit 32 through a packaging unit 33 according to a preset format, sending the data to peripheral equipment for further processing, and effectively sampling and processing the general input and output signals to improve the reliability and the accuracy of the data.

Further, performing a CRC check on the payload data may ensure the integrity of the data. CRC (cyclic redundancy check) is a common error detection technique that calculates a check value from data and then appends the check value to the data. After receiving the data, the receiver also performs CRC calculation, compares the calculated check value with the received check value, and if the calculated check value is inconsistent with the received check value, the receiver indicates that the data may be tampered or an error occurs in the transmission process.

Further, for Message Counter (MC), it is used to ensure the sequence and uniqueness of messages. Each time a message is sent, the counter is incremented itself and the value of the counter is appended to the message. After receiving the message, the receiver can determine whether the order of the messages is correct by comparing the values of the counters, and can detect whether there are duplicate messages.

In some embodiments, the input output interface group 1 includes a plurality of general purpose input output interfaces (GPIOs), which may be provided in three, four, or more. The following embodiments of the present invention take setting three GPIOs as examples, including GPIO0, GPIO1, and GPIO2. It should be noted that the number of GPIOs actually used may be set according to specific requirements.

In the prior art, the data length of oversample mode sampling is disclosed in the a-PHY PAL GPIO protocol as constrained by three parameters, namely a state number (state) SGS, a state group number (state) GTS and a state mask STATEMASK, and specifically constrained by the following formula:

Wherein PayloadByteLength denotes the byte length of the payload data, ceil denotes the rounding up, GTS denotes the number of state (state) groups in one sampling period (transaction), in an implementation application the state group index may start from 0, i.e. 0, 1..gts-1, SGS denotes the number of states (states) in each state (state) group, i denotes the index of the state (state) group, in an implementation application the index i may start from 0, i.e. i=0, 1..sgs-1;f (STATEMASK _i) denotes the number of states calculated from the state mask, the function being specified by the protocol and not described here.

As shown in fig. 2, an aggregate waveform diagram of three general input/output signals at STATEMASK =3b '011/3b'110 is shown, and in fig. 2, the sampling period (transaction) is continuous during sampling, i.e., transaction0, transaction 1. Sgs=2, gts=3 means that in a transaction comprising 3 state groups, each state group comprises 2 states, i.e. a total of 6 states, STATEMASK of which are cycled according to the 3b '011, 3b '110 state mask, where 3b ' represents a 3-bit binary number corresponding to the number of GPIOs set, e.g. STATEMASK should be a 4-bit binary number if GPIOs are set to 4. The numbers following 3b' correspond from left to right to indicate the validity of the GPIO0 to high-order GPIO signals at that sample point, respectively. I.e., numbers 011 and 110 following 3b', the first bit corresponds to GPIO0, the second bit corresponds to GPIO1, and the third bit corresponds to GPIO2.

An invalid sample point is indicated when STATEMASK =0, i.e. the GPIO signal is invalid at that sample point, and an valid sample point is indicated when STATEMASK =1, i.e. the GPIO signal is valid at that sample point. As an example, 011 indicates that GPIO1 and GPIO2 are active and GPIO0 is inactive at this sample point. While 110 indicates that at this sampling point GPIO0 and GPIO1 are active and GPIO2 is inactive.

Note that, in the embodiment of the present invention, the value range of SGS is [0, SGS-1], and the value range of GTS is [0, GTS-1], so that sgs=2, gts=3 corresponds to fig. 2. However, in actual process, the value range of SGS is [0, SGS ], that is, SGS should be set to 1, and similarly, the value range of GTS is [0, GTS ], that is, GTS should be set to 2. Since SGS and GTS start from 0 in practical application, SGS may be represented as a state index, and GTS may be represented as a state group index, which is set by 1 smaller than the number.

The three GPIOs are subjected to signal sampling by using the sampling period configuration shown in fig. 2, and payload data (payload data) obtained by sampling is shown in fig. 3, one transaction is 16 bits (bits), and a part of bits (bits) in the last byte (byte) of the payload data may be invalid, namely, 12 bits are valid, and 4 bits are rounded invalid data.

It should be noted that, in the actual process, the user may aggregate any number of GPIOs through the configuration register, and the number of invalid bits in the Payload data is uncertain. Thus, the design, when implemented, needs to distinguish which data is valid and which data is invalid, and additional complex circuit design guarantees must be added, which increases power consumption and area overhead.

As a preferred embodiment, wherein, as shown in fig. 4, the sampling unit 31 includes:

a first sampling module 311, configured to sample a plurality of General Purpose Input Output (GPIO) signals based on a plurality of consecutive sampling periods (transactions);

wherein the product of the first preset number and the second preset number is a multiple of one bit of a payload page (payload word), and the status masks are all 1.

Specifically, aiming at the problem that the invalid bit number in the Payload data is uncertain, additional complex circuit design is required to be added, so that power consumption and area overhead are increased, the embodiment design of the invention realizes effective data alignment of the Payload data by analyzing reasonable STATEMASK, GTS and STS proportioning rules in the range of a protocol, effectively avoids invalid data redundancy and data loss, and reduces the implementation complexity.

Specifically, by constraining STATEMASK, GTS and STS, the specific constraint is that the product of GTS and STS is an integer multiple of the bits of a payload word, and at the same time the state masks are all 1, i.e. the corresponding GPIOs are all valid at the sampling point.

As an example, if the payload word is 16 bits, the product of the GTS and STS is an integer multiple of 16 bits, which may be 16, 32, 48, 64, or more.

Further, the configuration relationships of SGS, GTS and STATEMASK under 16bit payload word under the constraint of the embodiment of the present invention are shown in table 1 below:

table 116bit payload word lower SGS, GTS and STATEMASK configuration relationship

Option	SGS	GTS	StateMask
				0 (Default)	4	4	All 1
1	4	8	All 1
				2	4	8	All 1
3	8	8	All 1

In practice, all optional (Option) configurations under this constraint may be used as fixed configurations, so that the user may select a fixed configuration through the configuration registers.

Any number of GPIOs may be aggregated by the constraints described above, with bits of one payloadword of the sample-generated a-packets (e.g., 16 bits of Payload data described above) aligned. Each bit in the payload data is effective, so that the design is simplified, an additional complex circuit is not required to be added to determine the data validity, and the area and the power consumption are saved.

Further, aggregate sampling is performed on the multiple GPIOs, and the Byte number of the corresponding data is 2 times that of the GPIOs, that is, aggregate sampling is performed on the N GPIOs, so as to generate 2*N bytes. Taking Option0 in FIG. 5 as an example, 3 GPIOs are aggregated, and the payload data of one transaction is 2*3 bytes as shown in FIG. 5.

It should be noted that, since SGS and GTS start from 0 in practical application, the constraint may be that the product of (gts+1) and (sts+1) is an integer multiple of the bits of a payload word in practical application, and the state masks are all 1. The corresponding configuration relation table is shown in table 2:

table 216bit payload word lower SGS, GTS and STATEMASK configuration relationship

Option	SGS	GTS	StateMask
				0 (Default)	3	3	All 1
1	3	7	All 1
				2	3	7	All 1
3	7	7	All 1

As a preferred embodiment, wherein, as shown in fig. 4, the sampling unit 31 further includes:

A second sampling module 312, configured to sample the plurality of general purpose input/output signals when a preset sampling trigger condition is satisfied;

the preset sampling trigger condition is that at least one general input/output signal is judged to be a rising edge at the first sampling point of each sampling period.

In particular, considering that whether sampling is continued when the GPIO pin is not pulsed is not explicitly described in the MIPI protocol, problems in terms of validity, boundary, timing, etc. of data may be caused, the reliability and applicability of the protocol are limited.

In this embodiment, by designing an implementation manner of event triggering, unnecessary invalid a-packet transmissions are reduced, and a-PHY network bandwidth overhead is reduced. The specific implementation mode is as follows:

When the aggregate sampling of the N GPIO signals is started, if all signals are low level at the moment of the first sampling point of one transaction, no sampling event is triggered during the transaction until the level state of the N GPIO signals is continuously judged at the moment of the first sampling point of the next transaction, so that whether sampling is triggered during the next transaction is determined.

When at least one signal is at a rising edge (or at a high level) at the moment of the first sampling point of the transaction, a sampling event is triggered, the sampling frequency can be set to be OSR, and sampling is continuously carried out under the condition that whether all signals are at a low level can not exist during the present transaction or not until the level states of N GPIO signals are continuously judged at the moment of the first sampling point of the next transaction, so that whether sampling is triggered during the next transaction or not is determined.

According to the embodiment of the invention, through the implementation mode, when the GPIO signal is in a low level and no data is transmitted, sampling logic is not performed, so that the power consumption and the occupation of the channel bandwidth are reduced.

As a preferred embodiment, as shown in fig. 4, the sampling unit further includes:

The third sampling module is used for sampling a plurality of general input/output signals according to a preset sampling logic;

the preset sampling logic samples the plurality of general input/output signals once every third preset number of chip clocks.

As a preferred embodiment, the third preset number is a ratio of the chip clock frequency and the general input/output sampling frequency.

Specifically, in this embodiment, a configurable sampling frequency design based on a CHIP clock is used, the clock frequency of the CHIP is chip_hz, and the sampling frequency of the GPIO is sample_hz. The sampling logic may sample the GPIO signal once by passing a third preset number (Counter) of chip clocks.

Wherein, the calculation formula of Counter is:

Counter=CHIP_HZ/SAMPLE_HZ。

Further, the user may configure the dedicated sampling rate according to his own actual frequency scenario. This may be achieved by modifying the value of SAMPLE HZ. According to the actual situation, the sampling rate is adjusted and optimized so as to improve the performance and efficiency of the system.

Furthermore, a Counter can be set, and the GPIO signal is sampled every time the Counter chip clocks pass according to the value of the Counter. At each sampling, the state of the GPIO is read and processed or recorded accordingly. According to actual demands, a timer or interrupt can be set to trigger sampling operation, so that the accuracy and timeliness of sampling are ensured.

As a preferred embodiment, the data packet has a payload page as a carrier for carrying payload data;

as shown in fig. 4, the sampling unit 31 further comprises a storage module 314 for storing the payload data into the payload page.

As a preferred embodiment, wherein the storage module comprises:

a first shift register (not shown) for shift-storing the payload data into the payload page.

Specifically, a payload page (payload word) is a carrier of payload data. payload word refers to the portion of the data packet transmitted in the computer network that carries the actual transmitted data content. It is the part of the packet other than the header information that contains the actual data that needs to be transmitted. The payload word may be various forms of data such as text, images, audio, video, etc.

Payload Word is the valid data sampled or parsed in RX and TX. PayloadWord takes Word (16 bits) as the smallest unit of data. In the scenario of aggregation processing of M GPIO signals, payloadWord contains M words.

As shown in fig. 6, at the Transmitting (TX) end, the sampling unit 3 samples N GPIO input signals at a sampling point with a sampling frequency OSR (determined according to a Counter) to obtain N bits of payload data, where each bit corresponds to one GPIO input signal, and then adds a CRC check and a message Counter to aggregate to generate an a-packet that conforms to the a-PHY protocol format, and sends the a-packet to the APPI interface of the peripheral device 2.

Further, the sampling unit 3 adopts a shift register to process, shifts N times, stores the sampled N-bit data in Word, and waits for the next sampling point to continue the shift operation.

As a preferred embodiment, as shown in fig. 6, the device further includes a receiving channel 4 connected between the input/output interface group 1 and the peripheral device 2, where the receiving channel 4 includes:

a verification unit 41 connected to the peripheral device 2, for obtaining a data packet from the peripheral device, analyzing the data packet, and performing a cyclic redundancy check and a verification of the message count to obtain payload data;

A parsing unit 42, coupled to the verification unit 41, for parsing the payload data to obtain a parsing result;

and a control unit 43 connected with the analysis unit 42 for generating corresponding control signals according to the analysis result and transmitting the control signals to the input/output interface group 1.

Specifically, as shown in fig. 6, at the Receiving (RX) end, after receiving the a-packet from the APPI interface of the peripheral device 2, the receiving end analyzes the a-packet to obtain PayloadWord, and analyzes the Word in the Payload Word by using a shift register, that is, for the a-packet formed by aggregating N GPIO input signals, after shifting N times to analyze the N-bit GPIO signal, waits for the next sampling point to continue the shifting operation.

In the verification unit 41, the a-packet is parsed, CRC check and MC check are performed, and then the payload data passed by the CRC check and MC check is sent to the parsing (Parse) unit 42 for further parsing, and then the parsing result is sent to the control (pin_mux) unit 43 to drive the signal to the GPIO output signal on the system on chip Soc.

The analysis unit includes:

A second shift register (not shown) for resolving the payload page by shifting the payload data to obtain a resolved result.

Furthermore, a shift register is adopted at the TX end to splice the sampled data into payload word, and a shift register is also adopted at the RX end to convert 16bit payload data into GPIO signals.

In the embodiment of the invention, the TX end and the RX end both use the shift register, so that the area cost is smaller compared with an algorithm (such as for circulation) for realizing a sampling and analyzing circuit.

In some embodiments, the set of input/output interfaces may be a general purpose input/output interface of a system on chip Soc, or may be a general purpose input/output interface of an external device. In a system on chip Soc, a general purpose input output interface is typically used to connect to external devices such as a keyboard, a mouse, a display, a storage device, etc. These interfaces may communicate with external devices via standard communication protocols, such as UART, SPI, I C, etc. Through these interfaces, the system on chip Soc can perform data exchange and control operations with external devices.

Referring to fig. 7, a second aspect of the present invention provides an oversampling method of a universal input output interface, applied to an oversampling circuit of the universal input output interface, wherein a transmit channel includes the following steps:

S1, sampling a plurality of general input/output signals of an input/output interface group to obtain effective load data;

S2, adding the cyclic redundancy check sum message count into the payload data to obtain payload data with the cyclic redundancy check sum message count;

s3, the payload data with the cyclic redundancy check sum message count is packaged into a data packet with a preset format, and the data packet is sent to the peripheral equipment.

With respect to more implementation details of this method, an oversampling circuit is already disclosed, and this embodiment will not be described again.

The over-sampling circuit has the advantages that the over-sampling circuit is realized aiming at oversample modes in a protocol, the realization scheme is provided, a transmitting channel samples a plurality of general input and output signals of an input and output interface group through a sampling unit, then cyclic redundancy check sum message count is added into payload data through an adding unit to ensure the integrity and accuracy of the data, finally the data is packaged according to a preset format through a packaging unit and sent to peripheral equipment for further processing, and the general input and output signals are effectively sampled and processed, so that the reliability and accuracy of the data are improved.

Meanwhile, the problem of payload data valid bit ambiguity is solved in the implementation process, the configuration of any sampling rate is realized, a sampling mode triggered by a rising edge is innovatively adopted, and the occupation of an invalid packet to bandwidth is reduced.

The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations herein, which should be included in the scope of the present invention.

Claims

1. A general purpose input/output interface oversampling circuit, comprising a transmission channel connected between an input/output interface group and a peripheral device, the transmission channel comprising:

a sampling unit connected to the input/output interface group, configured to sample a plurality of general input/output signals of the input/output interface group to obtain payload data;

an adding unit, connected to the sampling unit, configured to add a cyclic redundancy check and a message count to the payload data to obtain payload data with the cyclic redundancy check and the message count;

A packing unit is connected to the adding unit and the peripheral device respectively, and is used to pack the payload data with cyclic redundancy check and message count into a data packet in a predetermined format and send the data packet to the peripheral device.

2. The oversampling circuit of a universal input/output interface according to claim 1, wherein the sampling unit comprises:

a first sampling module, configured to sample the plurality of universal input and output signals based on a plurality of consecutive sampling periods;

Each of the sampling periods includes a first predetermined number of state groups, each state group includes a second predetermined number of states, and each state corresponds to a state mask;

The product of the first preset number and the second preset number is a multiple of bits of a payload page; and the status mask is all 1.

3. The oversampling circuit of a universal input/output interface according to claim 1 , wherein the sampling unit further comprises:

a second sampling module, configured to sample the plurality of universal input and output signals when a preset sampling trigger condition is met;

The preset sampling trigger condition is to determine that at least one of the universal input and output signals is a rising edge at the first sampling point of each sampling period.

4. The oversampling circuit of a universal input/output interface according to claim 1 , wherein the sampling unit further comprises:

a third sampling module, configured to sample the plurality of universal input and output signals according to a preset sampling logic;

The preset sampling logic samples the plurality of general input and output signals once every third preset number of chip clocks.

5 . The GPIO oversampling circuit according to claim 4 , wherein the third preset number is a ratio of a chip clock frequency to a GPIO sampling frequency.

6. The oversampling circuit of a universal input/output interface according to claim 1, wherein a payload page in the data packet is used as a carrier for carrying the payload data;

The sampling unit further includes: a storage module, configured to store the payload data in the payload page.

7. The oversampling circuit of a universal input/output interface according to claim 6, wherein the storage module comprises:

A first shift register is used to shift the payload data and store them in the payload page.

8. The universal input/output interface oversampling circuit according to claim 1, further comprising a receiving channel connected between the input/output interface group and the peripheral device, the receiving channel comprising:

a verification unit, connected to the peripheral device, configured to obtain the data packet from the peripheral device, parse the data packet, and perform cyclic redundancy check and message count verification to obtain the payload data;

a parsing unit, connected to the verification unit, configured to parse the payload data to obtain a parsing result;

A control unit is connected to the analyzing unit and is used to generate a corresponding control signal according to the analyzing result and transmit the control signal to the input and output interface group.

9. The oversampling circuit of a universal input/output interface according to claim 8, wherein a payload page in the data packet is used as a carrier for carrying the payload data;

The parsing unit includes:

A second shift register is used to parse the payload data from the payload page by shifting the payload data to obtain the parsing result.

10. A method for oversampling a universal input/output interface, characterized in that the method is applied to the oversampling circuit of the universal input/output interface according to any one of claims 1 to 9, wherein the transmitting channel comprises the following steps:

Sampling a plurality of general input and output signals of the input and output interface group to obtain payload data;

Adding a cyclic redundancy check and a message count to the payload data to obtain payload data with the cyclic redundancy check and the message count;

The effective load data with the cyclic redundancy check and the message count is packaged into a data packet in a predetermined format and sent to the peripheral device.