CN119013892A - Determination of gain of a pulse width modulation amplifier system - Google Patents
Determination of gain of a pulse width modulation amplifier system Download PDFInfo
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- CN119013892A CN119013892A CN202380033676.8A CN202380033676A CN119013892A CN 119013892 A CN119013892 A CN 119013892A CN 202380033676 A CN202380033676 A CN 202380033676A CN 119013892 A CN119013892 A CN 119013892A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
- H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
- H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
- H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
- H03F3/45991—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using balancing means
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Abstract
开关模式放大器系统可以包括开关模式放大器、包括反馈网络以及校准系统，该开关模式放大器具有放大器输入端和放大器输出端，该放大器输入端被耦合到模拟积分器的输出端，该反馈网络被耦合在放大器输出端和模拟积分器的输入端之间。该校准系统可以被配置为将模拟积分器的输入强制到固定的已知输入值，将放大器输出强制到固定的已知占空比，测量响应于将模拟积分器的输入强制到固定值而在模拟积分器的输出端处生成的模拟信号，基于该模拟信号确定开关模式放大器系统的偏移，并校正该偏移。
A switch-mode amplifier system may include a switch-mode amplifier having an amplifier input and an amplifier output, the amplifier input being coupled to an output of an analog integrator, the feedback network being coupled between the amplifier output and the input of the analog integrator, and a calibration system. The calibration system may be configured to force the input of the analog integrator to a fixed known input value, force the amplifier output to a fixed known duty cycle, measure an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, determine an offset of the switch-mode amplifier system based on the analog signal, and correct the offset.
Description
Technical Field
The present disclosure relates generally to circuits for audio devices, including but not limited to personal audio devices such as wireless telephones and media players, and more particularly to systems and methods for calibrating pulse width modulated amplifier systems.
Background
Personal audio devices, including wireless telephones such as mobile/cellular telephones, cordless telephones, mp3 players, and other consumer audio devices are being used extensively. Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. Such circuits typically include a power amplifier for driving the audio output signal to a headset or speaker. In general, a power amplifier amplifies an audio signal by taking energy from a power supply and controlling the audio output signal to match the shape of the input signal but with a larger amplitude.
One example of an audio amplifier is a class D amplifier. Class D amplifiers (also referred to as "switching amplifiers") may include electronic amplifiers in which an amplifying device (e.g., a transistor, typically a metal oxide semiconductor field effect transistor) operates as an electronic switch. In a class D amplifier, a signal to be amplified may be converted into a series of pulses by pulse-width modulation (PWM), pulse-density modulation (PDM), or another modulation method, such that the signal is converted into a modulated signal, wherein the pulse characteristics (e.g., pulse width, pulse density, etc.) of the modulated signal are a function of the magnitude of the signal. After amplification with the class D amplifier, the output pulse train may be converted to an unmodulated analog signal by a passive low pass filter, where such a low pass filter may be a load inherent in or driven by the class D amplifier. Class D amplifiers are often used due to the fact that they can be more energy efficient than linear analog amplifiers in that they consume less power (as heat) in the active devices than linear analog amplifiers.
In amplifier systems including those having class D amplifiers, it may be critical to determine and correct for any signal offset that may be present in the amplifier path. For example, some examples of signal offsets may be offsets inherent in the integrator stage of a pre-amplifier stage of an amplifier system, or mismatches of resistors used to set the gain of an amplifier system. Without correction of such signal offsets, signal distortion, signal inaccuracy, and/or other undesirable conditions may persist.
Disclosure of Invention
One or more of the disadvantages and problems associated with previous approaches to minimizing offset in pulse width modulated amplifier systems may be reduced or eliminated in accordance with the teachings of the present disclosure.
According to an embodiment of the present disclosure, a switch-mode amplifier system may include a switch-mode amplifier having an amplifier input coupled to an output of an analog integrator, and an amplifier output, a feedback network coupled between the amplifier output and the input of the analog integrator, the loop filter configured to generate a digital loop filter output, a quantizer configured to generate a pulse width modulated representation of the digital loop filter output, and a calibration system. The calibration system may be configured to force the input of the analog integrator to a fixed known input value, low-pass filter the pulse width modulated representation of the digital loop filter output generated by the quantizer to generate a filtered quantizer output signal, determine an offset of the switch-mode amplifier system based on the filtered quantizer output signal, and correct the offset.
In accordance with these and other embodiments of the present disclosure, a method may be provided for use in a switch-mode amplifier system having a switch-mode amplifier, having a feedback network coupled between an amplifier output and an input of an analog integrator, having a loop filter configured to generate a digital loop filter output, and having a quantizer configured to generate a pulse width modulated representation of the digital loop filter output, and having an amplifier input coupled to the output of the analog integrator. The method may include forcing an input of an analog integrator to a fixed known input value, low-pass filtering a pulse width modulated representation of a digital loop filter output generated by a quantizer to generate a filtered quantizer output signal, and determining an offset of a switch-mode amplifier system based on the filtered quantizer output signal and correcting the offset.
In accordance with these and other embodiments of the present disclosure, a calibration system for use with a switch-mode amplifier system having a switch-mode amplifier, having a feedback network, having a loop filter, and having a quantizer, the switch-mode amplifier comprising an amplifier input coupled to an output of an analog integrator and an amplifier output, the feedback network coupled between the amplifier output and the input of the analog integrator, the loop filter configured to generate a digital loop filter output, the quantizer configured to generate a pulse-width modulated representation of the digital loop filter output, may be provided. The calibration system may be configured to force an input of the analog integrator to a fixed known input value, low-pass filter the pulse width modulated representation of the digital loop filter output generated by the quantizer to generate a filtered quantizer output signal, determine an offset of the switch-mode amplifier system based on the filtered quantizer output signal, and correct the offset.
In accordance with these and other embodiments of the present disclosure, a switch-mode amplifier system may include a switch-mode amplifier having an amplifier input coupled to an output of an analog integrator and an amplifier output, and include a calibration system. The calibration system may be configured to force the input of the analog integrator to a fixed known input value, force the amplifier output to a fixed known duty cycle, measure an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to a fixed value, determine an offset of the switch mode amplifier system based on the analog signal, and correct the offset.
In accordance with these and other embodiments of the present disclosure, a method may be provided for use in a switch-mode amplifier system having a switch-mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output. The method may include forcing an input of the analog integrator to a fixed known input value, forcing an amplifier output to a fixed known duty cycle, measuring an analog signal generated at an output of the analog integrator in response to forcing the input of the analog integrator to a fixed value, determining an offset of the switch mode amplifier system based on the analog signal, and correcting the offset.
In accordance with these and other embodiments of the present disclosure, a calibration system for use with a switch-mode amplifier system having a switch-mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output may be provided. The calibration system may force the input of the analog integrator to a fixed known input value, force the amplifier output to a fixed known duty cycle, measure an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to a fixed value, determine an offset of the switch mode amplifier system based on the analog signal, and correct the offset.
According to these and other embodiments of the present disclosure, a switch-mode amplifier system may include a switch-mode amplifier including a circuit having an amplifier input coupled to an output of an analog integrator and an amplifier output, and a calibration system configured to force an input of the analog integrator to a fixed known input value, determine a slew rate of an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, and determine an integrator gain of the switch-mode amplifier system based on the slew rate.
In accordance with these and other embodiments of the present disclosure, a method may be provided for use in a switch-mode amplifier system having a switch-mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output. The method may include forcing an input of the analog integrator to a fixed known input value, determining a slew rate of an analog signal generated at an output of the analog integrator in response to forcing the input of the analog integrator to a fixed value, and determining an integrator gain of the switched mode amplifier system based on the slew rate.
In accordance with these and other embodiments of the present disclosure, a calibration system for use with a switch-mode amplifier system having a switch-mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output may be provided. The calibration system may be configured to force the input of the analog integrator to a fixed known input value, determine a slew rate of an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to a fixed value, and determine an integrator gain of the switched mode amplifier system based on the slew rate.
Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, descriptions, and claims included herein. The objects and advantages of the embodiments will be realized and attained by means of the elements, features, and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the claims as set forth in this disclosure.
Drawings
A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:
FIG. 1 is a diagram of an example personal audio device, according to an embodiment of the present disclosure;
FIG. 2 illustrates a block diagram of selected components of an example audio integrated circuit of a personal audio device, in accordance with an embodiment of the present disclosure;
FIG. 3 illustrates a flowchart of an example method for open loop calibration of the audio integrated circuit depicted in FIG. 2, in accordance with an embodiment of the present disclosure;
FIG. 4 illustrates a flowchart of an example method for determining a gain of the audio integrated circuit depicted in FIG. 2, in accordance with an embodiment of the present disclosure; and
Fig. 5 illustrates a flowchart of an example method for closed loop calibration of the audio integrated circuit depicted in fig. 2, in accordance with an embodiment of the present disclosure.
Detailed Description
Fig. 1 is an illustration of an example personal audio device 1 in accordance with an embodiment of the present disclosure. Fig. 1 depicts a personal audio device 1 coupled to a headset 3 in the form of a pair of earpiece speakers 8A and 8B. The headset 3 depicted in fig. 1 is merely an example, and it is understood that the personal audio device 1 may be used in connection with a variety of audio transducers, including but not limited to headphones, earphones, in-ear headphones, and external speakers. The plug 4 may provide a connection of the head mounted device 3 to the electrical terminals of the personal audio device 1. The personal audio device 1 may provide a display to the user and receive user input using the touch screen 2, or alternatively, a standard Liquid Crystal Display (LCD) may be combined with various buttons, sliders and/or dials provided on the front and/or side of the personal audio device 1. As also shown in fig. 1, the personal audio device 1 may comprise an audio integrated circuit (INTEGRATED CIRCUIT, IC) 9 for generating an analog audio signal for transmission to the head mounted device 3 and/or to another audio transducer.
Fig. 2 shows a block diagram of selected components of an example audio IC 9 of a personal audio device, according to an embodiment of the disclosure. In some embodiments, the example audio IC 9 may be used to implement the audio IC 9 of fig. 1. As shown IN fig. 2, the microcontroller core 18 may provide a digital-to-analog converter (DAC) 14 with a digital audio input signal dig_in, which may convert the digital audio input signal to an analog input signal V IN. DAC 14 may provide an analog input signal V IN to amplifier 16, which may amplify or attenuate analog input signal V IN to provide an audio output signal V OUT, which audio output signal V OUT may operate a speaker, a headphone transducer, a line level signal output, and/or other suitable output.
As also shown in fig. 2, the amplifier 16 may include a signal input network 24, a first stage 22 (e.g., analog front end), a quantizer 34, a final output stage, a signal feedback network 26, and a control system 28, the first stage 22 configured to receive the analog input signal V IN at an amplifier input of the amplifier 16 and to generate an intermediate signal V INT (which is a function of the analog input signal V IN), the final output stage including a class D audio output stage 42 configured to generate an audio output signal V OUT at an amplifier output of the amplifier 16, the signal feedback network 26 coupled between the amplifier output and the amplifier input, the control system 28 to control operation of certain components of the amplifier 16, as described in more detail below.
The signal input network 24 may comprise any suitable input network that receives an amplifier input of the amplifier 16. For example, as shown in fig. 2, the signal input network 24 may include a variable input resistor 46, wherein the resistance of the variable input resistor 46 may be controlled by a control signal received from the control system 28, as described in more detail below.
The first stage 22 may include any suitable analog front end circuitry for conditioning the analog input signal V IN for use by the class D audio output stage 42. For example, the first stage 22 may include one or more analog integrators 30 and 32 cascaded in series, as shown in fig. 2.
Quantizer 34 may comprise any system, device, or apparatus configured to quantize intermediate signal V INT to generate equivalent digital PWM signal V QUANT. Thus, quantizer 34 may be referred to as a digital pulse width modulator. As shown in fig. 2, quantizer 34 may receive one or more control signals from control system 28, which may control the operation of quantizer 34 during a calibration phase of audio IC 9, as described in more detail below.
Class D audio output stage 42 may comprise any system, device, or apparatus configured to receive the output of quantizer 34 and drive output signal V OUT, which output signal V OUT is an amplified version of analog input signal V IN. Accordingly, the class D audio output stage 42 may include a plurality of output switches configured to generate the output signal V OUT from the modulated signal V QUANT generated by the quantizer 34. After amplification by the class D audio output stage 42, its output pulse train may be converted back to an unmodulated analog signal by passing through a passive low pass filter, where such a low pass filter may be inherent in the output circuitry of the class D audio output stage 42 or a load driven by the class D audio output stage 42.
The signal feedback network 26 may comprise any suitable feedback network for feeding back a signal indicative of the audio output signal V OUT to the amplifier input of the amplifier 16. For example, as shown in fig. 2, signal feedback network 26 may include a variable feedback resistor 48, wherein the resistance of variable feedback resistor 48 is controlled by a control signal received from control system 28, as described in more detail below. Those skilled in the art will recognize that the closed loop gain of amplifier 16 may be set by the ratio of the resistance of variable feedback resistor 48 to the resistance of variable input resistor 46.
As also shown in fig. 2, the example audio IC 9 may also include a control system 28. Control system 28 may include any suitable system, device, or apparatus configured to receive information indicative of a signal within the signal path of amplifier 16 (e.g., voltage V INT' and/or modulated signal V QUANT output by integrator 30) and perform calibration of audio IC 9 based at least on the information. For example, IN some embodiments, control system 28 may generate a digital trim signal that is combined with digital audio input signal dig_in by combiner 20 to effectively modify digital audio input signal dig_in to correct for the detected offset within the amplifier system of audio IC 9. As another example, in these and other embodiments, control system 28 may generate one or more analog trim signals to modify the resistance of one or more input resistors 46, one or more feedback resistors 48, and/or parameters of integrator 30 (e.g., modify the current source of an operational amplifier of integrator 30, modify an external current source or apply an external offset to integrator 30, etc.).
Fig. 3 illustrates a flowchart of an example method 300 for open loop calibration of an amplifier system of an audio IC 9, according to an embodiment of this disclosure. According to some embodiments, the method 300 may begin at step 302. As noted above, the teachings of the present disclosure may be implemented in various configurations of audio IC 9. Thus, the preferred initialization point of method 300 and the order in which the steps comprising method 300 are included may depend on the implementation chosen.
At step 302, control system 28 may initialize the digital trim values and the analog trim values to default values. For example, the digital trim value may be set to zero, while the analog trim value may be set according to the desired nominal gain for amplifier 16. At step 304, control system 28 may communicate a control signal to microcontroller core 18 such that microcontroller core 18 outputs a zero value for digital audio input signal dig_in. At step 306, control system 28 may communicate a control signal to quantizer 34 to cause quantizer 34 to generate a zero differential modulation signal V QUANT to class D audio output stage 42 (e.g., by outputting the same square wave signal on each of its differential outputs) regardless of the intermediate voltage V INT generated by first stage 22. By doing so, control system 28 effectively interrupts/opens the signal feedback loop that exists during normal operation of audio IC 9 during such an open loop calibration mode.
At step 308, control system 28 may determine whether the magnitude of voltage V INT' is below a first predetermined threshold. The substantially non-zero value of voltage V INT' may indicate the presence of an offset within the signal path of amplifier 16, including, but not limited to, an offset inherent to integrator 30, an offset due to mismatch between input resistors 46, and/or an offset due to mismatch between feedback resistors 48. Accordingly, control system 28 may attempt to minimize voltage V INT 'during the open loop calibration mode by changing one or more of the digital trim and/or the analog trim in order to reduce the magnitude of voltage V INT' below the first predetermined threshold. Thus, if the magnitude of the voltage V INT' is below the first predetermined threshold, the method 300 may proceed to step 312. Otherwise, the method 300 may proceed to step 310.
At step 310, control system 28 may change one or more of the digital trim and/or the analog trim in an effort to reduce the magnitude of voltage V INT'. After completing step 310, the method 300 may proceed again to step 308.
At step 312, control system 28 may store digital trim and/or analog trim settings to invoke and apply such trim settings during normal operation of the amplifier system.
While the above steps may detect and correct for overall offset of the amplifier system, such steps may not isolate any particular offset sources. However, the following steps may isolate the offset due to mismatch between the input resistors 46 and/or mismatch between the feedback resistors 48.
At step 314 (while maintaining digital audio input signal DIG IN at zero), control system 28 may communicate a control signal to quantizer 34 to cause quantizer 34 to generate a differential PWM output of quantizer 34 at a first duty cycle (e.g., 25% duty cycle) while maintaining differential modulation signal V QUANT of quantizer 34 at zero and determining a voltage V INT' resulting therefrom. At step 316 (while maintaining digital audio input signal DIG IN at zero), control system 28 may communicate a control signal to quantizer 34 to cause quantizer 34 to generate a differential PWM output of quantizer 34 at a second duty cycle (e.g., 75% duty cycle) while maintaining differential modulation signal V QUANT of quantizer 34 at zero and determining a voltage V INT' resulting therefrom.
Operating at different duty cycles while maintaining the differential modulation signal V QUANT of the quantizer 34 at zero may achieve the effect of varying the common mode voltage of the output voltage V OUT. Thus, at steps 314 and 316, instead of changing the duty cycle of the differential output of quantizer 34, in some embodiments, control system 28 may generate a control signal that changes the common mode voltage of output voltage V OUT between two different levels (e.g., by changing the supply voltage to class D audio output stage 42). The difference between the values of the first duty cycle/first output common mode voltage and the voltage V INT' at the second duty cycle/second output common mode voltage may be indicative of a mismatch resistance between the input resistors 46 and/or a mismatch resistance between the feedback resistors 48.
In some embodiments, instead of operating at two different duty cycles as described above, control system 28 may generate control signals that change the common mode voltage of output voltage V OUT between at least three different levels (e.g., at least three different duty cycles), determine differences in voltage V INT' at the different duty cycles, and correct for such differences, including correcting for linear and nonlinear mismatch of input resistor 46 and/or linear and nonlinear mismatch of feedback resistor 48.
At step 318, control system 28 may determine whether the magnitude of the difference in voltage V INT' between the first duty cycle/first output common mode voltage and the second duty cycle/second output common mode voltage is below a second predetermined threshold. If the magnitude of the difference is below the second predetermined threshold, the method 300 may proceed to step 322. Otherwise, the method 300 may proceed to step 320.
At step 320, control system 28 may change one or more of the digital trim and/or the analog trim in an effort to reduce the magnitude of voltage V INT'. After completing step 320, method 300 may proceed again to step 314.
At step 322, control system 28 may store digital trim and/or analog trim settings to invoke and apply such trim settings during normal operation of the amplifier system. After completing step 322, method 300 may end.
The steps of method 300 may be applied to each gain setting of an amplifier system to determine an offset and perform calibration on each gain setting.
Although fig. 3 discloses a particular number of steps to be taken relative to method 300, the method may be performed with more or fewer steps than depicted in fig. 3. Furthermore, although FIG. 3 discloses a certain order of steps to be taken with respect to method 300, the steps comprising method 300 may be accomplished in any suitable order. For example, in some embodiments, steps 314 through 322 for isolating and calibrating for resistor mismatch may be performed before steps 302 through 312 for determining and calibrating for overall offset.
Method 300 may be implemented using control system 28, components thereof or coupled thereto, or any other system operable to implement method 300. In certain embodiments, the method 300 may be implemented in part or in whole in software and/or firmware embodied in a computer readable medium.
Fig. 4 illustrates a flowchart of an example method 400 for determining the gain of an amplifier system of an audio IC 9, according to an embodiment of this disclosure. According to some embodiments, the method 400 may begin at step 402. As noted above, the teachings of the present disclosure may be implemented in various configurations of audio IC 9. Thus, the preferred initialization point of the method 400 and the order in which the steps of the method 400 are included may depend on the implementation chosen.
At step 402, control system 28 may communicate a control signal to quantizer 34 to cause quantizer 34 to generate a zero differential modulation signal V QUANT to class D audio output stage 42 (e.g., by outputting the same square wave signal on each of its differential outputs) regardless of the intermediate voltage V INT generated by first stage 22. By doing so, control system 28 effectively breaks/opens the signal feedback loop that exists during normal operation of audio IC 9 during such an open loop calibration mode.
At step 404, control system 28 may communicate a control signal to microcontroller core 18 such that microcontroller core 18 outputs a value for digital audio input signal dig_in such that DAC 14 generates a square wave signal at its output with a small duty cycle (e.g., a minimum possible duty cycle or a minimum non-zero value for DAC 14). As a result of the application of such square wave signals to the input of the amplifier 16 in such open loop configurations, the output voltage V INT' generated by the integrator 30 may generate a periodic signal between its minimum and maximum values, with a limited slew rate when the periodic signal increases from its minimum value to its maximum value, and vice versa. In some embodiments, the square wave signal may cause the output of the voltage V INT' generated by the integrator 30 to saturate. In these and other embodiments, the input voltage may be slowly ramped.
At step 406, control system 28 may determine a slew rate of output voltage V INT'. At step 408, control system 28 may estimate the integrator gains of the amplifier system based on the slew rate because the integrator gains from the input of integrator 30 (e.g., analog input signal V IN) and the output of integrator 30 (e.g., voltage V INT ') may be a function of the slope of voltage V INT'.
After completing step 408, the method 400 may end.
Although fig. 4 discloses a particular number of steps to be taken relative to method 400, the method may be performed with more or fewer steps than depicted in fig. 4. Furthermore, although FIG. 4 discloses a certain order of steps to be taken with respect to method 400, the steps comprising method 400 may be accomplished in any suitable order.
Method 400 may be implemented using control system 28, components thereof or coupled thereto, or any other system operable to implement method 400. In some embodiments, method 400 may be implemented in part or in whole in software and/or firmware embodied in a computer-readable medium.
When method 300 interrupts or opens the amplifier feedback loop to perform calibration, control system 28 may perform calibration while maintaining the amplifier system in a closed-loop configuration in addition to or instead of the open-loop calibration of method 300, as described below with reference to method 500.
Fig. 5 illustrates a flowchart of an example method 500 for closed loop calibration of an amplifier system of an audio IC 9, according to an embodiment of this disclosure. According to some embodiments, method 500 may begin at step 502. As noted above, the teachings of the present disclosure may be implemented in various configurations of audio IC 9. Thus, the preferred initialization point of method 500 and the order in which the steps of method 500 are included may depend on the implementation chosen.
At step 502, control system 28 may initialize digital trim values and analog trim values to default values. For example, the digital trim value may be set to zero, while the analog trim value may be set according to the desired nominal gain for amplifier 16. At step 504, control system 28 may communicate a control signal to microcontroller core 18 such that microcontroller core 18 outputs a zero value for digital audio input signal dig_in.
At step 506, control system 28 may low pass filter (e.g., with an averaging filter) modulated signal V QUANT generated by quantizer 34. At step 508, control system 28 may determine whether the magnitude of low-pass filtered modulated signal V QUANT is below a first predetermined threshold. The substantially non-zero value of the low-pass filtered modulated signal V QUANT may indicate the presence of an offset within the signal path of the amplifier 16, including, but not limited to, an offset inherent to the integrator 30, an offset due to mismatch between the input resistors 46, and/or an offset due to mismatch between the feedback resistors 48. Accordingly, control system 28 may attempt to minimize low-pass filtered modulation signal V QUANT during the closed-loop calibration mode by changing one or more of the digital and/or analog fine adjustments in order to reduce the magnitude of low-pass filtered modulation signal V QUANT below the first predetermined threshold. Thus, if the magnitude of the low-pass filtered modulated signal V QUANT is below the first predetermined threshold, the method 500 may proceed to step 512. Otherwise, the method 500 may proceed to step 510.
At step 510, control system 28 may change one or more of the digital fine adjustments and/or the analog fine adjustments in an effort to reduce the magnitude of low-pass filtered modulation signal V QUANT. After completing step 510, method 500 may proceed again to step 506.
At step 512, control system 28 may store digital trim and/or analog trim settings to invoke and apply such trim settings during normal operation of the amplifier system.
While the above steps may detect and correct for overall offset of the amplifier system, such steps may not isolate any particular offset sources. However, the following steps may isolate the offset due to mismatch between the input resistors 46 and/or mismatch between the feedback resistors 48.
At step 514, control system 28 may communicate a control signal to quantizer 34 to cause quantizer 34 to generate a differential PWM output of quantizer 34 at a first duty cycle (e.g., 25% duty cycle) and determine a low-pass filtered modulation signal V QUANT resulting therefrom. At step 516, control system 28 may communicate a control signal to quantizer 34 to cause quantizer 34 to generate a differential PWM output of quantizer 34 at a second duty cycle (e.g., 75% duty cycle) and determine a low-pass filtered modulation signal V QUANT resulting therefrom.
Operating at different duty cycles while maintaining the differential modulation signal V QUANT of the quantizer 34 near zero may achieve the effect of varying the common mode voltage of the output voltage V OUT. Thus, at steps 514 and 516, instead of changing the duty cycle of the differential output of quantizer 34, in some embodiments, control system 28 may generate a control signal that changes the common mode voltage of output voltage V OUT between two different levels (e.g., by changing the supply voltage to class D audio output stage 42). The difference between the values of the low-pass filtered modulation signal V QUANT at the first duty cycle/first output common mode voltage and the second duty cycle/second output common mode voltage may be indicative of a mismatch resistance between the input resistors 46 and/or a mismatch resistance between the feedback resistors 48.
In some embodiments, instead of operating at two different duty cycles as described above, control system 28 may generate control signals that change the common mode voltage of output voltage V OUT between at least three different levels (e.g., at least three different duty cycles), determine differences in voltage V INT' at the different duty cycles, and correct for such differences, including correcting for linear and nonlinear mismatch of input resistor 46 and/or linear and nonlinear mismatch of feedback resistor 48.
At step 518, control system 28 may determine whether the magnitude of the difference in low-pass filtered modulation signal V QUANT between the first duty cycle/first output common mode voltage and the second duty cycle/second output common mode voltage is below a second predetermined threshold. If the magnitude of the difference is below the second predetermined threshold, the method 500 may proceed to step 522. Otherwise, the method 500 may proceed to step 520.
At step 520, control system 28 may change one or more of the digital fine adjustments and/or the analog fine adjustments in an effort to reduce the magnitude of low-pass filtered modulation signal V QUANT. After completing step 520, method 500 may again proceed to step 514.
At step 522, control system 28 may store digital trim and/or analog trim settings to invoke and apply such trim settings during normal operation of the amplifier system. After completing step 522, method 500 may end.
The steps of method 500 may be applied to each gain setting of an amplifier system to determine an offset and perform calibration on each gain setting.
Although fig. 5 discloses a particular number of steps to be taken relative to method 500, the method may be performed with more or fewer steps than depicted in fig. 3. Furthermore, although FIG. 5 discloses a certain order of steps to be taken with respect to method 500, the steps comprising method 300 may be accomplished in any suitable order. For example, in some embodiments, steps 514 through 522 for isolating and calibrating for resistor mismatch may be performed before steps 502 through 512 for determining and calibrating for overall offset.
Method 500 may be implemented using control system 28, components thereof or coupled thereto, or any other system operable to implement method 500. In certain embodiments, the method 300 may be implemented in part or in whole in software and/or firmware embodied in a computer readable medium.
The calibration operations performed by control system 28 and described above may be performed at any suitable time, including, but not limited to, during a calibration phase that occurs when audio IC 9 is powered on, during a calibration phase that occurs after audio IC 9 is assembled, during a calibration phase that occurs when the amplifier system of audio IC 9 is not in use (e.g., does not generate audio content), and/or during a calibration phase that occurs in response to a temperature change proximate to audio IC 9.
As used herein, when two or more elements are referred to as being "coupled" to each other, such term indicates that such two or more elements are in electronic or mechanical communication, whether indirectly connected or directly connected, with or without intervening elements, as appropriate.
The present disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that one of ordinary skill would understand. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person of ordinary skill in the art would understand. Furthermore, references in the appended claims to an apparatus or system or component of an apparatus or system being adapted, arranged, capable, configured, enabled, operable, or operable to perform a particular function include the apparatus, system, or component whether or not it or that particular function is activated, or unlocked, provided that the apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operable. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, components of the systems and devices may be integrated or separated. Moreover, the operations of the systems and apparatus disclosed herein may be performed by more, fewer, or other components and the described methods may include more, fewer, or other steps. In addition, the steps may be performed in any suitable order. As used in this document, "each" refers to each member of a collection or each member of a subset of a collection.
Although exemplary embodiments are illustrated in the accompanying drawings and described below, the principles of the present disclosure may be implemented using any number of techniques, whether presently known or not. The present disclosure should in no way be limited to the exemplary embodiments and techniques illustrated in the accompanying drawings and described above.
The items depicted in the drawings are not necessarily drawn to scale unless specifically indicated otherwise.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the present disclosure.
Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Further technical advantages may become apparent to one of ordinary skill in the art after reviewing the preceding figures and description.
To assist the patent office and any readers of any patent issued to the present application in interpreting the appended claims of the present application, the applicant wishes to note that unless terms such as "means for … …" or "step for … …" are expressly used in a particular claim, they are not intended to refer to 35u.s.c. ≡112 (f) by any element of the appended claims or claims.
Claims (15)
1. A switch-mode amplifier system, comprising:
A switch-mode amplifier, comprising:
an amplifier input coupled to an output of the analog integrator; and
An amplifier output; and
A calibration system configured to:
Forcing the input of the analog integrator to a fixed known input value;
measuring a slew rate of an analog signal generated at an output of the analog integrator in response to forcing an input of the analog integrator to the fixed value; and
An integrator gain of the switch-mode amplifier system is determined based on the slew rate.
2. The switch-mode amplifier system of claim 1, wherein the fixed known value is a value that causes the integrator to saturate.
3. The switched-mode amplifier system of claim 1 or 2, wherein the calibration system is configured to disable feedback of the switched-mode amplifier system when determining the slew rate.
4. A switched mode amplifier system according to any one of claims 1 to 3, further comprising a feedback network coupled between the amplifier output and the input of the analog integrator.
5. The switch-mode amplifier system of claim 4, wherein the calibration system disables the feedback network by forcing the amplifier output to a fixed known duty cycle.
6. In a switch-mode amplifier system having a switch-mode amplifier, the switch-mode amplifier comprising an amplifier input and an amplifier output, the amplifier input coupled to an output of an analog integrator, a method comprising:
Forcing the input of the analog integrator to a fixed known input value;
Determining a slew rate of an analog signal generated at an output of the analog integrator in response to forcing an input of the analog integrator to the fixed value; and
An integrator gain of the switch-mode amplifier system is determined based on the slew rate.
7. The method of claim 6, wherein the fixed known value is a value that causes the integrator to saturate.
8. The method of claim 6 or 7, further comprising disabling feedback of the switch-mode amplifier system when determining the slew rate.
9. The method of any of claims 6 to 8, the switch-mode amplifier system further having a feedback network coupled between the amplifier output and the input of the analog integrator.
10. The method of claim 9, further comprising disabling the feedback network by forcing an amplifier output to a fixed known duty cycle.
11. A calibration system for use with a switch-mode amplifier system having a switch-mode amplifier and having a feedback network, the switch-mode amplifier comprising an amplifier input coupled to an output of an analog integrator and an amplifier output, the feedback network coupled between the amplifier output and the input of the analog integrator, the calibration system configured to:
Forcing the input of the analog integrator to a fixed known input value;
Determining a slew rate of an analog signal generated at an output of the analog integrator in response to forcing an input of the analog integrator to the fixed value; and
An integrator gain of the switch-mode amplifier system is determined based on the slew rate.
12. The calibration system of claim 11, wherein the fixed known value is a value that causes saturation of the integrator.
13. The calibration system of claim 11 or 12, wherein the calibration system is configured to disable feedback of the switch-mode amplifier system when determining the slew rate.
14. The calibration system of any of claims 11 to 13, the switch-mode amplifier system further having a feedback network coupled between the amplifier output and the input of the analog integrator.
15. The calibration system of claim 14, wherein the calibration system disables the feedback network by forcing an amplifier output to a fixed known duty cycle.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/720,936 | 2022-04-14 | ||
| US17/720,936 US11764741B1 (en) | 2021-11-09 | 2022-04-14 | Determination of gain of pulse width modulation amplifier system |
| PCT/US2023/017852 WO2023200680A1 (en) | 2022-04-14 | 2023-04-07 | Determination of gain of pulse width modulation amplifier system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN119013892A true CN119013892A (en) | 2024-11-22 |
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|---|---|---|---|
| CN202380033676.8A Pending CN119013892A (en) | 2022-04-14 | 2023-04-07 | Determination of gain of a pulse width modulation amplifier system |
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| Country | Link |
|---|---|
| KR (1) | KR20250002331A (en) |
| CN (1) | CN119013892A (en) |
| GB (1) | GB2631632A (en) |
| WO (1) | WO2023200680A1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106575950A (en) * | 2014-06-30 | 2017-04-19 | 高通股份有限公司 | An audio switching amplifier |
| US20180212569A1 (en) * | 2017-01-20 | 2018-07-26 | Cirrus Logic International Semiconductor Ltd. | Offset calibration for amplifier and preceding circuit |
-
2023
- 2023-04-07 GB GB2414048.5A patent/GB2631632A/en active Pending
- 2023-04-07 WO PCT/US2023/017852 patent/WO2023200680A1/en not_active Ceased
- 2023-04-07 KR KR1020247036717A patent/KR20250002331A/en active Pending
- 2023-04-07 CN CN202380033676.8A patent/CN119013892A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106575950A (en) * | 2014-06-30 | 2017-04-19 | 高通股份有限公司 | An audio switching amplifier |
| US20180212569A1 (en) * | 2017-01-20 | 2018-07-26 | Cirrus Logic International Semiconductor Ltd. | Offset calibration for amplifier and preceding circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023200680A1 (en) | 2023-10-19 |
| KR20250002331A (en) | 2025-01-07 |
| GB202414048D0 (en) | 2024-11-06 |
| GB2631632A (en) | 2025-01-08 |
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