CN119050074B - A power chip packaging structure - Google Patents
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- CN119050074B CN119050074B CN202411528642.9A CN202411528642A CN119050074B CN 119050074 B CN119050074 B CN 119050074B CN 202411528642 A CN202411528642 A CN 202411528642A CN 119050074 B CN119050074 B CN 119050074B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 33
- 230000017525 heat dissipation Effects 0.000 claims abstract description 52
- 238000003466 welding Methods 0.000 claims abstract description 49
- 230000005540 biological transmission Effects 0.000 claims description 21
- 230000001154 acute effect Effects 0.000 claims description 4
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- 229910052710 silicon Inorganic materials 0.000 abstract description 2
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- 238000005476 soldering Methods 0.000 description 15
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- 238000012536 packaging technology Methods 0.000 description 11
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- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000011056 performance test Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a power chip packaging structure, and relates to the technical field of chip packaging. The chip stacking structure comprises a welding seat dish, a contact protecting cover and a chip stacking structure, wherein the welding seat dish is arranged on the surface of a circuit board and is communicated with a circuit path in the circuit board, the contact protecting cover is arranged at a dish opening on the top surface of the welding seat dish, when the welding seat dish is assembled with the contact protecting cover, the bottom surface of the contact protecting cover presses the chip stacking structure arranged in the welding seat dish, the chip stacking structure is communicated with the circuit path by means of the welding seat dish, and the top surface of the contact protecting cover is sunken based on the chip arrangement position in the chip stacking structure. According to the invention, the stacking mode among the chips is changed, the concave surfaces corresponding to the top surfaces of the chips are arranged on the top surfaces of the contact protecting covers, and the heat dissipation silicon paste is smeared on each concave surface, so that the heat generated by the chips can be rapidly conducted to the contact protecting covers, and further, the heat is dissipated through other heat dissipation measures (such as a heat dissipation sheet, a fan and the like), so that the normal operation of the chips is ensured.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a power chip packaging structure.
Background
The power chip packaging structure is used for improving the energy efficiency and the stability of the electronic equipment, and the packaging structure forms a compact and reliable whole by packaging the power chip and an external circuit, so that the power loss can be effectively reduced, the thermal management performance can be improved, and the chip can be ensured to maintain stable temperature under long-time high-load operation.
Through searching, the Chinese patent of publication number CN115101492A discloses a 3D chip packaging heat dissipation structure, and the application can prevent water from entering the chip under the condition of water leakage of the structure by arranging a water leakage detection assembly, and the possibility of water leakage is maximum at the joint of a micro-channel pipe and a water diversion pipe or the joint of the micro-channel pipe and the water diversion pipe because of the integrated structure of the micro-channel pipe;
in addition, the Chinese patent of the publication No. CN115346936A discloses a 3D chip packaging structure and a packaging method, and the application enables a first insulating packaging layer to be formed on the first surface of a first chip and wrapped on the surface of the second chip by arranging the second chip on the first surface of the first chip, so that the transmission speed of the chip can be improved, the packaging size is optimized, meanwhile, the packaging process of the first chip and the second chip can be simplified, the complexity of the packaging process is reduced, and the total packaging cost is reduced;
However, since the two disclosed chip packaging structures are constructed based on the principle of the 3D chip packaging technology, and since each chip is completely stacked together in the 3D chip packaging technology, in actual use, functions of different chip layers in the 3D chip packaging are different, so that when a single-core project is operated, power and instruction data can flow to a specific chip in the power chip, and also need to be transferred and distributed through other chip layers in the power chip, energy consumption is increased, and thermal management of the whole system becomes more complex.
Disclosure of Invention
The present invention is directed to a power chip package structure, which solves the above-mentioned problems in the prior art.
In order to achieve the above purpose, the invention provides a power chip packaging structure, comprising:
the welding seat vessel is arranged on the surface of the circuit board and is communicated with a circuit path in the circuit board;
the contact protecting cover is arranged at the dish opening on the top surface of the welding seat dish;
When the welding seat dish and the contact protecting cover are assembled, the bottom surface of the contact protecting cover presses the chip stacking structure arranged in the welding seat dish, and the chip stacking structure is communicated with the circuit path by virtue of the welding seat dish;
The chip stacking structure is characterized in that position differences exist between adjacent chips in the chip stacking structure, stacking contact areas between two adjacent chips are not completely overlapped, the top surface of the contact protecting cover is recessed based on the arrangement positions of the chips in the chip stacking structure, a plurality of recessed surfaces are formed, the top surface of each chip in the chip stacking structure is correspondingly attached to one recessed surface of the top surface of the contact protecting cover, and the surface of each recessed surface is used for smearing silicon paste for heat dissipation.
As a further preferred aspect of the present invention, the chip stacking structure includes:
the chips with different functions are stacked and mounted in the welding seat dish from bottom to top, and a first angle which is not an acute angle is formed between the chip located at the bottommost part of the welding seat dish and the chip located at the topmost part of the welding seat dish and the bottom of the welding seat dish.
As a further preferred proposal, the circuit of the stacking contact area between two adjacent chips is communicated, a plurality of buffer pad bonds are arranged between the chips and the bottom end inside the welding seat dish in a pressing way, and the buffer pad bonds are used for communicating the circuit of the chips with the circuit path in the circuit board;
A first interval is reserved between each chip and the chip positioned at the bottommost part of the welding seat dish, the first interval is gradually increased, and the volume of the cushion pad bonding is increased along with the increase of the first interval.
As a further preferred aspect of the present invention, the chip stacking structure includes:
the plurality of chips with different functions are uniformly attached to the side wall positions inside the welding seat dish based on the number of corners of the welding seat dish, a second angle is formed between each chip and the welding seat dish, and two adjacent chips are stacked and form a third angle;
the sum of the third angle and the second angle does not exceed 90 degrees.
As a further preferable mode of the technical scheme, a central source chip is arranged in the central position of the welding seat vessel, the central source chip is arranged in the central position of the chip stacking structure in a stacking mode, each edge of the outer surface of the central source chip corresponds to one chip, and a lead wire for interconnection is fixed between the chip and the outer surface of the central source chip.
As a further preferable mode of the technical scheme, a wafer bonding pad is fixed in the welding seat dish, and a plurality of guide pins are arranged at the bottom of the welding seat dish and used for being connected with a circuit path;
and transmission channels corresponding to the guide pins in number are arranged in the wafer bonding pad, and the aperture of the transmission channels in the wafer bonding pad and the overall thickness of the wafer bonding pad gradually decrease from two sides of the bonding seat dish to the central area of the bonding seat dish.
As a further preferred aspect of the present invention, a plurality of cushion pad bonds are filled between the chip and the wafer pad, and each cushion pad bond corresponds to one of the transmission channels;
The cushion pad is bonded to form an inclined base for supporting the chip, an inclined angle is formed between the inclined base and the welding seat dish, the chip is attached to and fixed to the top surface of the inclined base, and the radiating surface of the chip is inclined to the plane of the wafer bonding pad based on the inclined angle.
As a further preferable mode of the technical scheme, through holes from top to bottom are formed in the adjacent two chip stacking contact areas, through column bonding is filled in the through holes, and the through column bonding is used for communicating all circuit combinations in the chip stacking structure.
As a further preferable mode of the technical scheme, the top surface of the contact protecting cover is provided with a plurality of radiating fins which are uniformly distributed based on the arrangement positions of chips in the chip stacking structure and are in one-to-one correspondence with the top surfaces of the chips;
the bottom surface of the radiating fin is attached to the concave surface contacting the top surface of the protecting cover, the top surface of the radiating fin protrudes out of the top surface contacting the protecting cover, the top surface of the radiating fin is an inclined surface, and the inclined angle of the inclined surface is matched with the inclined angle of the chip in the chip stacking structure.
As a further preferable mode of the technical scheme, a plurality of radiating holes for discharging heat generated in the operation of the chip stacking structure are formed in each side wall of the welding seat dish, and the radiating holes in each side wall correspond to the positions of the chips in the chip stacking structure.
Drawings
FIG. 1 is an isometric view of the present invention;
FIG. 2 is a front cross-sectional view of a second embodiment of the present invention;
FIG. 3 is a first block diagram of a third embodiment of the present invention;
FIG. 4 is a second construction diagram of a third embodiment of the present invention;
fig. 5 is a cross-sectional view of a package structure of a stacked power chip according to the prior art;
FIG. 6 is a structural diagram of a chip package structure according to the present invention;
FIG. 7 is an assembly view of the tilting base of the present invention;
FIG. 8 is a schematic diagram of a prior art stacked power chip within a circuit board;
FIG. 9 is a schematic circuit diagram of a second embodiment of a chip of the present invention;
FIG. 10 is a schematic circuit diagram of a third embodiment of the chip of the present invention.
In the figure, 1, a contact protecting cover, 2, a chip stacking structure, 201, a middle source chip, 202, a side wing chip, 203, an inclined base, 204, a lead wire, 205, an inclined sensing wafer, 206, cushion bonding, 207, through column bonding, 208, a horizontal sensing wafer, 3, a welding seat dish, 4, a guide pin and 5, and a wafer bonding pad.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Before the technical scheme provided by the invention is known, it is clear that the 3D chip packaging technology in the prior art refers to that interlayer interconnection is realized by stacking a plurality of chips and utilizing micro-bumps and micro-through holes, so as to construct an integrated circuit with a three-dimensional structure.
In the first embodiment, since the 3D chip package stacks each chip completely, but because the functions of different chip layers are different, when the power chip runs a single core project, power and instruction data will not only flow to a specific chip in the power chip, but also need to be transferred and distributed through other chip layers in the power chip, so that the energy consumption is increased and the thermal management of the whole system becomes more complex.
As is clear from fig. 1 to 7, in the present embodiment, the power chip package structure includes a bonding pad 3, a contact protecting cover 1, and a chip stacking structure 2.
Specifically, in this embodiment, the soldering socket 3 is mounted on the surface of the circuit board and is connected to the circuit path in the circuit board, and the contact protecting cover 1 is mounted at the socket opening on the top surface of the soldering socket 3 and is used for sealing the soldering socket 3, so that when the soldering socket 3 and the contact protecting cover 1 are assembled, the bottom surface of the contact protecting cover 1 is pressed onto the chip stacking structure 2 in the soldering socket 3, and the chip stacking structure 2 is connected to the circuit path by means of the soldering socket 3.
It should be added that in this embodiment, each layer of chips in the chip stacking structure 2 needs to transmit electrical signals with an external circuit or other chip layers, where the solder socket 3 is used as a bridge between the chip stacking structure 2 and the circuit board, and provides necessary electrical connection points, so that the chip stacking structure 2 can be smoothly connected with a circuit path in the circuit board, and signal transmission and processing are implemented, and in addition, the solder socket 3 not only provides electrical connection, but also plays a role in supporting and fixing the chip stacking structure 2 during actual operation, and by mounting the chip stacking structure 2 on the solder socket 3, the relative position stability between the chip layers can be ensured, and chip displacement or damage caused by vibration or temperature change in the working process can be prevented.
It should be further noted that, referring to fig. 1 to fig. 4, in this embodiment, there is a position difference between adjacent chips in the chip stacking structure 2, and stacking contact areas between two adjacent chips are not completely overlapped, the top surface of the contact protecting cover 1 is recessed based on the arrangement positions of the chips in the chip stacking structure 2, and a plurality of recessed surfaces are formed, each top surface of the chips in the chip stacking structure 2 is correspondingly attached to a recessed surface of the top surface of the contact protecting cover 1, and the surface of each recessed surface is used for smearing the silicone paste for heat dissipation.
Specifically, since a large amount of heat is generated during operation of the chips in the chip stacking structure 2, the conventional 3D chip packaging technology causes chips in the chip stacking structure 2 to be stacked as shown in fig. 5, so that when a single-core or multi-core task is performed, as shown in fig. 8, a heat transfer path needs to be long through each layer of chips in the chip stacking structure 2, which results in low heat dissipation efficiency, and further affects the heat dissipation performance of the chip stacking structure 2, however, in the present embodiment, due to the arrangement of the position difference between adjacent chips in the chip stacking structure 2, the chips in the chip stacking structure 2 and the chips are not completely stacked together as in the conventional 3D chip packaging technology, and a certain space is provided between the chips, as shown in fig. 9 and 10, when such a design performs a single-core or multi-core task, the combination between each chip is independent with respect to the chip combination in the 3D chip packaging technology, so that heat can be transferred from the chip generating heat to the surrounding environment more quickly without passing through each layer of chips, thereby greatly improving the heat dissipation efficiency, and the heat dissipation efficiency needs to be supplemented by the voltage of fig. 8, vo and v, respectively, fig. 9 and v represent input voltage v and v.
In addition, referring to fig. 2-4, by arranging concave surfaces corresponding to the top surfaces of the chips on the top surfaces of the contact protecting covers 1 and coating heat dissipation silicone paste on each concave surface, heat generated by the chips can be quickly conducted to the contact protecting covers 1, and further, heat is dissipated through other heat dissipation measures (such as heat dissipation fins, fans and the like), so that normal operation of the chips is ensured.
It is also to be added that, because the design of the concave surface also increases the contact area between the chip stacking structure 2 and the contact protecting cover 1, the connection strength between the chip stacking structure 2 and the contact protecting cover is improved, so that the chip stacking structure 2 is more stable when being impacted or vibrated externally, and is not easy to displace or damage.
In the second embodiment, since the 3D chip packaging technology is to completely stack different chip layers together to realize data transmission, in actual operation, a certain amount of magnetic fields are generated between each layer of chips during power-on operation, and influence is generated between the magnetic fields, so that signal interference is caused during data transmission, and stability and speed of data transmission are affected.
It should be noted that, in this embodiment, the chip stacking structure 2 includes a plurality of chips with different functions, and the chips are stacked and mounted inside the solder socket 3 from bottom to top, and a first angle which is not an acute angle is formed between the chip located at the bottom of the solder socket 3 and the chip located at the top of the solder socket 3 and the bottom of the solder socket 3.
It should be clear that, in this embodiment, the limitation of the first angle is used for reducing the magnetic field interference between the adjacent chip layers, and the first angle is not set as an acute angle, so that the chips at the bottommost part of the soldering boat 3 and the chips at the topmost part of the soldering boat 3 are not located at different heights in the same position, and the effect that the chip stacking structure 2 presents a step stacking is further limited.
It should be added that, in this embodiment, by setting the first angle, a certain space interval is formed between the adjacent chip layers, so that the direct action between magnetic fields is reduced, thereby reducing the possibility of signal interference, improving the reliability and speed of data transmission, in addition, the design of the step stacking type is also conducive to optimizing the heat dissipation performance, since the chips can generate heat during operation, the traditional 3D chip packaging technology is tightly stacked to easily cause heat to accumulate between the chips, and is difficult to effectively dissipate, and the step stacking type structure can more rapidly dissipate heat to the surrounding environment by increasing the space interval between the chip layers, thereby improving the heat dissipation efficiency of the whole packaging structure and guaranteeing the stable operation of the chips.
Furthermore, it should be further noted that, referring to fig. 2, in this embodiment, the circuit of the stacked contact area between two adjacent chips is connected, a plurality of cushion pads 206 are mounted between the chips and the bottom end inside the soldering boat 3 in a pressing manner, the cushion pads 206 are used for connecting the circuit of the chips and the circuit path inside the circuit board, a first space is reserved between each chip and the chip located at the bottommost part of the soldering boat 3, the first space is gradually increased, and the cushion pads 206 are increased in volume along with the increase of the first space.
It should be clear that, in the present embodiment, the first space is used to ensure that a sufficient space is maintained between two adjacent chips to prevent physical contact or electromagnetic interference between them, and in addition, due to the arrangement that the first space is gradually increased, the cushion bond 206 increases in volume along with the increase of the first space, so that when thermal expansion or pressure changes, the cushion bond 206 can better adapt and disperse the stress caused by these changes, thereby protecting the connection between the chips from being broken, and meanwhile, the first space and the volume of the cushion bond 206 corresponding thereto optimize the packaging density and performance while meeting the requirements of physical isolation and electromagnetic protection.
In the third embodiment, due to the 3D chip packaging technology, in the practical assembly process, the power chip manufactured by the 3D chip packaging technology is limited by application scenarios due to thickness, for example, in some light and thin devices, due to space limitations, the chip layers are directly stacked in the form of fig. 5, which results in overlarge volume and reduced portability of the light and thin device, and therefore, referring to fig. 3, a chip stacking structure 2, specifically, a spliced power chip package is proposed.
It should be noted that, in this embodiment, the chip stacking structure 2 includes a plurality of chips with different functions, the plurality of chips are uniformly attached to the edge wall position inside the soldering socket 3 based on the number of corners of the soldering socket 3, a second angle is formed between each chip and the soldering socket 3, and a third angle is formed between two adjacent chips, wherein the sum of the third angle and the second angle is not more than 90 degrees.
In addition, in this embodiment, a central position inside the bonding seat vessel 3 is provided with a central source chip 201, the central source chip 201 is mounted in a stacked manner on a central position of the chip stacking structure 2, each side of an outer surface of the central source chip 201 corresponds to one chip, and a lead 204 for interconnection is fixed between the chip and the outer surface of the central source chip 201.
It should be clear that, in the present embodiment, referring to fig. 1 and 6, a plurality of chips with different functions are divided into a plurality of side chips 202 and a central chip 201 based on the positions in the bonding pad 3, wherein the side chips 202 are uniformly attached to the side wall positions in the bonding pad 3, and a second angle is formed between each side chip 202 and the bonding pad 3, which is embodied as a first structure and a second structure in the present embodiment.
As can be seen from fig. 3, the first structure has the intermediate source chip 201 placed in the middle due to the plurality of side chips 202, and the intermediate source chip 201 is located lower than all of the side chips 202.
It should be clear that, the features of the first structure enable the chip stacking structure 2 provided in this embodiment to be in a lower position when actually running, so that the heat dissipation and the heat dissipation of the central source chip 201 and the heat dissipation of the central recess surface of the contact cover 1 are facilitated, and the heat dissipation performance of the whole chip is optimized.
It should be noted that, referring to fig. 4, the second structure is that the middle source chip 201 is placed in the middle by the plurality of side chips 202, so that the middle source chip 201 is located lower than all the side chips 202, but the heat dissipation surface of the side chip 202 is far away from the middle source chip 201 and faces the outside of the bonding pad 3.
It should be clear that, in the practical operation of the chip stacking structure 2 according to the present embodiment, the heat dissipation surface of the side chip 202 in the second structure directly faces the external environment, so as to reduce the accumulation of heat in the chip, further improve the heat dissipation efficiency, and in addition, the design of the second structure also allows a larger space between the side chip 202 and the middle source chip 201, which is beneficial to air circulation, thereby accelerating the dissipation of heat.
It is noted that, whether it is the first structure or the second structure, the chip stacking structure 2 in this embodiment realizes the optimized layout in the limited space by smartly adjusting the angle and the position between the chips, thereby not only meeting the requirement of the light and thin device on the volume, but also ensuring the efficient operation and good heat dissipation of the power chip.
In the fourth embodiment, as a supplement to the three-phase content of the first embodiment and the third embodiment, it should be clear that in the present embodiment, a wafer bonding pad 5 is fixed inside the bonding pad 3, a plurality of guide pins 4 are provided at the bottom of the bonding pad 3, the guide pins 4 are used for connecting with the circuit paths, transmission channels corresponding to the number of the guide pins 4 are provided in the wafer bonding pad 5, the aperture of the transmission channel in the wafer bonding pad 5 and the overall thickness of the wafer bonding pad 5 gradually decrease from two sides of the bonding pad 3 to the central area of the bonding pad 3, a plurality of cushion bonds 206 are filled between the chip and the wafer bonding pad 5, each cushion bond 206 corresponds to one transmission channel, the plurality of cushion bonds 206 form an inclined base 203 for supporting the chip, an inclination angle is formed between the inclined base 203 and the soldering boat 3, the chip is attached and fixed on the top surface of the inclined base 203, and the heat dissipation surface of the chip is inclined to the plane of the wafer bonding pad 5 based on the inclination angle, besides, in the application, the top of the chip is fixed with a wafer, which is the construction material of the chip, in the application, the wafer provides a stable base for the circuits in the chip, in particular in the application, the wafer on the top of the chip is divided into an inclined sensing wafer 205 and a flat sensing wafer 208 due to the position, wherein the inclined sensing wafer 205 is mounted on the top of the flank chip 202, and the flat sensing wafer 208 is mounted on the top of the central chip 201.
It should be noted that, in this embodiment, the wafer bonding pad 5 is not only used for fixing the guide pin 4, but also enables the buffer pad bond 206 to transmit the data in the chip to the guide pin 4 through the transmission channel, and in addition, in the actual assembly, the aperture of the transmission channel in the wafer bonding pad 5 and the overall thickness of the wafer bonding pad 5 are gradually reduced from two sides of the bonding pad 3 to the central area of the bonding pad 3, so that in the actual assembly, the bonding pad 3 is actually assembled, and as can be seen with reference to fig. 7, the chip stacking structure 2 assembled in the bonding pad 3 can realize the inclined arrangement of the bottommost chip in the chip stacking structure 2 due to the arrangement that the bottom is in contact with the inclined base 203.
Therefore, when the chip stacking structure is applied to the structure provided in the third embodiment, since the bottommost chip in the chip stacking structure 2 is arranged obliquely, not only is the compactness of the whole packaging structure optimized, but also the heat dissipation efficiency of the chip is further improved, in addition, the oblique bottom chip can guide heat to the edge of the soldering socket dish 3 more effectively, and the heat dissipation surface of the flanking chip 202 directly dissipates into the external environment, so that the accumulation of heat in the chip is avoided, in addition, the oblique design is also helpful for reducing the thermal stress between the chips, improving the stability and reliability of the packaging structure, and meanwhile, the transmission channel design of the wafer bonding pad 5 ensures the efficient transmission of the data in the chip, so that the whole packaging structure has good data transmission capability while maintaining high performance.
In the fifth embodiment, the first, second and third embodiments are supplemented, and it is to be noted that, in the 3D chip packaging technology in the prior art, by stacking a plurality of chips and using a micro bump and a micro via structure to implement interlayer interconnection, an integrated circuit with a three-dimensional structure is constructed, specifically, in this embodiment, top-down through holes (micro vias) are formed in two adjacent chip stacking contact areas, through-hole pillars 207 (micro bumps) are filled in the through holes, and through-pillar bonds 207 (micro bumps) are used to communicate all circuit combinations in the chip stacking structure 2.
In order to improve the actual heat dissipation effect of the first, second and third embodiments, the present embodiment proposes the following features, referring to fig. 1, where the top surface of the contact cover 1 is provided with a plurality of heat dissipation fins, the heat dissipation fins are uniformly distributed based on the arrangement positions of the chips in the chip stacking structure 2, the heat dissipation fins 101 are in one-to-one correspondence with the top surfaces of the chips, the bottom surfaces of the heat dissipation fins 101 are attached to the concave surfaces of the top surfaces of the contact cover 1, the top surfaces of the heat dissipation fins 101 protrude from the top surfaces of the contact cover 1, the top surfaces of the heat dissipation fins 101 are inclined surfaces, and the inclination angle of the inclined surfaces is matched with the inclination angle of the chips in the chip stacking structure 2.
It should be noted that, in this embodiment, through the design of adding the heat dissipation fins 101 on the contact protecting cover 1, not only the heat dissipation area is increased, but also the air flow efficiency is further improved by utilizing the design of the inclined plane, so that the heat can be dissipated into the surrounding environment more quickly, meanwhile, the heat dissipation fins and the top surface of the chip are arranged in a one-to-one correspondence manner, so that the heat can be directly led to the heat dissipation system from the chip source, the pertinence and the efficiency of heat dissipation are improved, in addition, the heat dissipation holes formed in the side wall of the welding seat dish 3 correspond to the positions of the chips, the heat dissipation path is further optimized, the retention of the heat in the package structure is reduced, the overall heat dissipation performance is further improved, and due to the comprehensive heat dissipation design, the heat dissipation difficulty of the power chip in the light and thin equipment due to the limited volume is solved, and the good balance of the heat dissipation efficiency and the compactness of the package is also realized.
In order to further improve the technical scheme provided in the first embodiment, the present embodiment provides a method for constructing a chip stacking structure 2, which includes S100-S600.
S100, preparing each component required by the chip stacking structure 2, including the mesogenic chip 201, the flanking chips 202, the wafer bonding pads 5, the guide pins 4 and the cushion bonding 206, and ensuring that the specification and the number of the components meet the design requirements.
Specifically, the design requirements include that the middle source chip 201 needs to have high integration and low power consumption characteristics to meet the requirements of complex circuit systems, the side wing chip 202 needs to be compatible with the middle source chip 201 and to be complementary in function, so that the overall performance is improved together, the wafer bonding pad 5 needs to have excellent conductivity and stability, the accuracy and reliability of signal transmission between chips are ensured, the material, the diameter and the elasticity of the guide pin 4 need to be considered for selection, so that the chips can be ensured to be stable in the connection process, damage to the chips can be avoided, and parameters such as temperature, pressure and the like need to be strictly controlled in the assembly process, so that thermal stress or mechanical damage to the chips is avoided.
And S200, primarily positioning the central source chip 201, and placing the central source chip 201 on a preset workbench or a clamp to ensure that the position and the angle of the chip are accurate.
Specifically, the mode of preliminary positioning is to scan the chip by using a high-precision visual recognition system of a computer in the prior art, identify the edge and the mark point of the chip by using an image processing technology, calculate the deviation between the chip and an ideal position according to a chip model preset in the computer, and then slightly move and rotate the chip by using a micro-adjusting mechanical arm or a clamp until the edge and the mark point of the chip completely coincide with the preset position, wherein the computer needs to continuously repeat the processes of scanning, calculating and adjusting until reaching the preset positioning precision, thus completing the preliminary positioning of the central source chip 201.
And S300, stacking the flanking chips 202 with the middle source chip 201 according to a preset angle and a preset position.
S400, fixing the wafer bonding pad 5 in the welding seat pan 3, and ensuring that the guide pin 4 is correctly abutted with a transmission channel in the wafer bonding pad 5 so as to prepare for subsequent data transmission.
And S500, filling cushion pad bonding 206 between the wafer bonding pad 5 and the chip, constructing an inclined base 203 for supporting the chip, and adjusting the inclination angle of the inclined base 203 according to the thought requirement so as to ensure that the heat radiation surface of the chip can be inclined to the plane of the wafer bonding pad 5.
And S600, performing comprehensive inspection and test on the constructed chip stacking structure 2, including but not limited to electrical performance test and heat dissipation performance test, so as to ensure that the chip stacking structure meets the design requirements and has stable and reliable performance.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended embodiments and equivalents thereof.
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| CN115831888A (en) * | 2022-11-26 | 2023-03-21 | 泓林微电子（昆山）有限公司 | Double-side packaged chip heat radiation structure |
| CN118280950A (en) * | 2024-03-29 | 2024-07-02 | 中汽创智科技有限公司 | Multilayer wafer heat dissipation packaging structure based on core particle technology |
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| CN115831888A (en) * | 2022-11-26 | 2023-03-21 | 泓林微电子（昆山）有限公司 | Double-side packaged chip heat radiation structure |
| CN118280950A (en) * | 2024-03-29 | 2024-07-02 | 中汽创智科技有限公司 | Multilayer wafer heat dissipation packaging structure based on core particle technology |
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