CN119069431A - A semiconductor structure, packaging structure and manufacturing method - Google Patents
A semiconductor structure, packaging structure and manufacturing method Download PDFInfo
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- CN119069431A CN119069431A CN202310610403.7A CN202310610403A CN119069431A CN 119069431 A CN119069431 A CN 119069431A CN 202310610403 A CN202310610403 A CN 202310610403A CN 119069431 A CN119069431 A CN 119069431A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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Abstract
The present disclosure relates to a semiconductor structure, a package structure, and a method of fabrication, the semiconductor structure including a substrate having a middle region and an edge region surrounding the middle region, a device layer disposed on the substrate, the device layer including devices located in the edge region and devices located in the middle region, and a barrier layer located between the device layer and the substrate and located in the edge region, the barrier layer configured to block the devices located in the edge region from transferring charge to the substrate. By arranging the blocking layer between the device layer and the substrate, the blocking layer is positioned in the edge area of the substrate, and the blocking layer can be used for blocking the device in the edge area from transferring charges to the substrate, so that arc discharge is prevented from happening when the semiconductor structure is etched later, the protection of the semiconductor structure is enhanced, the yield of the semiconductor structure is improved, and in addition, the yield of a package structure formed by subsequent packages is also improved, and the cost is reduced.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure, a packaging structure and a manufacturing method.
Background
With the development of semiconductor manufacturing technology, stacked package is one of the mainstream technologies for improving the integration level of chip package, and in the process of stacked package, bonding is generally achieved between stacked semiconductor structures through Bonding pads (Bonding pads). However, before the bonding pad of the semiconductor structure is fabricated, an exposed metal layer exists in the edge region of the semiconductor structure, the exposed metal layer gathers charges, and when the bonding pad is formed by plasma etching, plasma bombards the exposed metal layer, causing arc discharge (arcing) of the metal layer in the edge region, thereby causing burning or damage of the semiconductor structure and reducing the yield of the semiconductor structure.
Disclosure of Invention
To overcome the problems in the related art, the present disclosure provides a semiconductor structure, a package structure, and a method of manufacturing the same.
According to some embodiments, a semiconductor structure provided in a first aspect of an embodiment of the present disclosure includes:
A substrate having a middle region and an edge region surrounding the middle region;
the device layer is arranged on the substrate and comprises a device positioned in the edge area and a device positioned in the middle area;
and a blocking layer between the device layer and the substrate, the blocking layer being located at the edge region, the blocking layer being configured to block devices at the edge region from transferring charge to the substrate.
In some embodiments of the present disclosure, the edge region is provided with a groove, the groove being disposed around the intermediate region;
The barrier layer is a dielectric layer disposed within the recess.
In some embodiments of the disclosure, the groove is an annular half groove with both top and outer sides open. In some embodiments of the present disclosure, the dielectric layer includes a plurality of dielectric material layers stacked in sequence.
In some embodiments of the present disclosure, the barrier layer includes a P-type semiconductor layer and an N-type semiconductor layer stacked on the edge region, the N-type semiconductor layer is located above the P-type semiconductor layer, and an interface of the P-type semiconductor layer and the N-type semiconductor layer forms a PN junction.
In some embodiments of the present disclosure, an upper surface of the barrier layer is flush with an upper surface of the substrate.
According to some embodiments, the package structure provided by the second aspect of the embodiments of the present disclosure comprises at least two phase-bonded semiconductor structures as described in the first aspect;
The packaging structure is provided with a trimming area, the trimming area is positioned at the circumferential edge of the packaging structure, and the width of the trimming area is smaller than that of the edge area.
In some embodiments of the present disclosure, the width of the trimming area is 1.5 to 3mm;
The height H1 of the barrier layer, the height H2 of the device layer, the height H3 of the trimming area and the height H4 of the substrate meet the relational expression that H1 is less than or equal to H3-2H 2-H4;
Wherein H3 is 150+ -15 mm.
According to some embodiments, a method for fabricating a semiconductor structure provided in a third aspect of embodiments of the present disclosure includes:
Providing a substrate, wherein the substrate is provided with a middle area and an edge area surrounding the middle area;
Forming a barrier layer in the edge region of the substrate, including etching the edge region of the substrate, forming a groove which is positioned in the edge region and surrounds the middle region, and forming a dielectric layer in the groove, or forming a P-type semiconductor layer and an N-type semiconductor layer in the edge region of the substrate through a doping process, wherein the N-type semiconductor layer is positioned above the P-type semiconductor layer, and a PN junction is formed at the interface of the P-type semiconductor layer and the N-type semiconductor layer;
Forming a device layer on the substrate and the barrier layer, wherein the device layer comprises a device positioned in the edge region and a device positioned in the middle region;
Wherein the blocking layer is configured to block devices of the edge region from transferring charge to the substrate.
According to some embodiments, a method for manufacturing a package structure provided in a fourth aspect of the embodiments of the present disclosure includes:
providing at least two semiconductor structures as described in the first aspect;
bonding the semiconductor structures to form a bonding structure;
And removing part of the edge structure of the bonding structure to form a packaging structure, wherein the packaging structure is provided with a trimming area, the trimming area is positioned at the circumferential edge of the packaging structure, and the width of the trimming area is smaller than that of the edge area.
The embodiment of the disclosure has the advantages that the blocking layer is arranged between the device layer and the substrate and is positioned in the edge area of the substrate, and the blocking layer can be used for blocking devices in the edge area to transfer charges to the substrate, so that arc discharge is prevented from occurring in the subsequent etching of the semiconductor structure, the protection of the semiconductor structure is enhanced, the yield of the semiconductor structure is improved, and in addition, the yield of a package structure formed by subsequent packaging is also improved, and the cost is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic diagram of a related art semiconductor structure for arc discharge.
Fig. 2 is a schematic diagram of a semiconductor structure shown in an exemplary embodiment of the present disclosure.
Fig. 3 is a top view of a substrate shown in an exemplary embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a substrate shown in an exemplary embodiment of the present disclosure.
Fig. 5 is a schematic diagram of a blocking layer blocking charge transfer according to an exemplary embodiment of the present disclosure.
Fig. 6 is a schematic diagram of a substrate with grooves formed, as shown in an exemplary embodiment of the present disclosure.
Fig. 7 is a schematic diagram of a substrate and a barrier layer according to an exemplary embodiment of the present disclosure.
Fig. 8 is a schematic diagram of a substrate and a barrier layer shown in another exemplary embodiment of the present disclosure.
Fig. 9 is a schematic diagram of a substrate and a barrier layer shown in another exemplary embodiment of the present disclosure.
Fig. 10 is a schematic diagram of a semiconductor structure shown in another exemplary embodiment of the present disclosure.
Fig. 11 is a partial enlarged view at a in fig. 10, shown in an exemplary embodiment of the present disclosure.
Fig. 12 is a schematic diagram of a package structure shown in an exemplary embodiment of the present disclosure.
Fig. 13 is a schematic diagram of two semiconductor structures shown prior to bonding in accordance with an exemplary embodiment of the present disclosure.
Fig. 14 is a schematic diagram of a bonding structure shown in an exemplary embodiment of the present disclosure.
Fig. 15 is an electron microscope scan of the location of the trimming area of the package structure shown in an exemplary embodiment of the present disclosure.
Fig. 16 is a flow chart of a method of a semiconductor structure shown in an exemplary embodiment of the present disclosure.
Fig. 17 is a flowchart illustrating a method of forming a barrier layer at an edge region of a substrate according to an exemplary embodiment of the present disclosure.
Fig. 18 is a flowchart illustrating a method of forming a device layer on a substrate and a barrier layer according to an exemplary embodiment of the present disclosure.
Fig. 19 is a flow chart of a method of a package structure shown in an exemplary embodiment of the present disclosure.
Reference numerals illustrate:
a 10-substrate, 11-edge region;
12-intermediate region, 20-barrier layer;
30-device layer, 31-device;
a 32-pad, 33-top metal layer;
a 35-pad layer;
36-via hole, 40-dielectric layer;
a 41-silicon dioxide layer, a 42-silicon nitride layer;
a 43-silicon oxynitride layer, a 51-N type semiconductor layer;
a 52-P type semiconductor layer, a 60-trimming region;
70-groove, 80-photoresist;
90-height of metal layer, H1-barrier layer;
height of H2-device layer, height of H3-trim region;
H4-height of the substrate.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.
In the related art, as shown in fig. 1, a semiconductor structure includes an edge region 11 and an intermediate region 12 surrounded by the edge region 11, wherein devices are disposed on both the edge region 11 and the intermediate region 12. A device formed on the edge region 11 includes a metal layer 90, for example, a metal layer such as a first metal layer (M1), a second metal layer (M2), a third metal layer (M3), a fourth metal layer (M4), and the like, which constitute the device. The metal layer 90 is limited to a process, the metal layer 90 in the edge region 11 is easily exposed, not covered by the photoresist 80, and the exposed metal layer 90 accumulates charges. When the bonding pad of the semiconductor structure is formed by plasma etching or other processes, the plasma bombards the metal layer 90 exposed in the edge region 11, so that arc discharge is generated in the metal layer 90 exposed in the edge region 11, and the discharge charges enter the middle region through the substrate 10, so that the semiconductor structure is burned or damaged, and the yield of the semiconductor structure is reduced.
Based on the above, the exemplary embodiments of the present disclosure provide a semiconductor structure, in which a blocking layer is disposed between a device layer and a substrate, and the blocking layer is located in an edge region of the substrate, so as to block devices in the edge region from transferring charges to the substrate, prevent arc discharge from occurring during subsequent etching of the semiconductor structure, enhance protection of the semiconductor structure, and improve yield of the semiconductor structure.
In one exemplary embodiment, as shown in fig. 2, the semiconductor structure provided in the embodiment of the disclosure includes a substrate 10, a device layer 30 and a barrier layer 20, where the substrate 10 has a middle region 12 and an edge region 11 surrounding the middle region 12, the device layer 30 is disposed on the substrate 10, the device layer 30 includes a plurality of devices 31, a part of the devices 31 of the plurality of devices 31 are disposed in the middle region 12, and another part of the devices are disposed in the edge region 11, that is, the plurality of devices 31 are divided into two parts, i.e., the devices 31 disposed in the edge region 11 and the devices disposed in the middle region 12.
The barrier layer 20 is located between the device layer 30 and the substrate 10, and the barrier layer 20 is located at the edge region 11, the barrier layer 20 being configured to block devices 31 of the edge region 11 from transferring charge to the substrate 10.
The substrate 10 may be, for example, a silicon substrate, a silicon germanium substrate, a carbon silicon substrate, or the like, and the shape of the substrate 10 may be, for example, a circular shape as shown in fig. 3. As shown in fig. 3 and 4, the substrate 10 has a middle region 12 and an edge region 11 surrounding the middle region 12, i.e., the middle region 12 is a middle region of the substrate 10, the edge region 11 is a peripheral region of the substrate 10, and the edge region 11 is an annular region circumferentially disposed along the middle region 12.
The substrate 10 is provided with a device layer 30, and the device layer 30 includes a device 31 located in an edge region 11 of the substrate 10 and a device 31 located in a middle region 12, where the device 31 may be, for example, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a dynamic Random Access Memory (Dynamic Random Access Memory, DRAM), a Static Random Access Memory (SRAM), a magnetoresistive Random Access Memory (Magnetoresistive Random Access Memory, MRAM), or the like, which implement a semiconductor structure function.
The barrier layer 20 is located at the edge region 11 of the substrate 10 and between the substrate 10 and the device layer 30, the upper surface of the barrier layer 20 is flush with the upper surface of the substrate 10, the peripheral edge of the barrier layer 20 is flush with the peripheral edges of the substrate 10 and the device layer 30, and the barrier layer 20 is capable of blocking the devices 31 of the edge region 11 from transferring charge to the substrate 10.
During formation of device layer 30, the photoresist thickness of edge region 11 is typically greater than the photoresist thickness of intermediate region 12, and the photoresist of edge region 11 is typically removed, resulting in exposure of some or all of the metal layer of edge region 11, which may accumulate charge.
Illustratively, as shown in fig. 5, portions of the metal layer 90 located in the edge regions 11 are not covered by the photoresist 80, resulting in charge accumulation in the exposed metal layer 90. When the photoresist 80 is used as a mask and the plasma is used to etch the semiconductor structure, the plasma bombards the exposed metal layer 90, so that the exposed metal layer 90 generates flowable discharge charges, and the barrier layer 20 is disposed below the exposed metal layer 90 in the edge region 11, so that the discharge charges can be blocked from being transferred from the devices in the edge region 11 to the substrate 10, thereby preventing the discharge charges from burning out the devices in the middle region 12 and improving the yield of the semiconductor structure.
In this embodiment, by disposing the barrier layer 20 between the device layer 30 and the substrate 10, the barrier layer 20 is located in the edge region 11 of the substrate 10 to block the device 31 in the edge region 11 from transferring charges to the substrate 10, so as to prevent arcing during subsequent etching of the semiconductor structure, enhance the protection of the semiconductor structure, and improve the yield of the semiconductor structure.
In some embodiments, as shown in fig. 6 and 7, the edge region 11 is provided with a recess 70, the recess 70 being disposed around the intermediate region 12, and the barrier layer 20 being the dielectric layer 40 disposed within the recess 70.
As shown in fig. 6, the groove 70 is located in the edge region 11 of the substrate 10, and the groove 70 is disposed around the middle region 12 to form an annular groove located at the outer edge of the substrate 10.
As shown in fig. 7, the blocking layer 20 is a dielectric layer 40 disposed in the recess 70, the width and thickness of the dielectric layer 40 are the same as the width and depth of the recess 70, the dielectric layer 40 may be formed by thermal oxidation (Thermal oxidation) or plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition, abbreviated as PECVD), and the dielectric layer 40 can block the device 31 of the edge region 11 from transferring charges to the substrate 10.
In this embodiment, the groove 70 surrounding the middle region 12 is disposed in the edge region 11, and the dielectric layer 40 is correspondingly disposed in the groove 70, so that the device 31 disposed in the edge region 11 is blocked from transferring charges to the substrate 10, thereby preventing arc discharge during subsequent etching of the semiconductor structure, enhancing the protection of the semiconductor structure, and improving the yield of the semiconductor structure.
In some embodiments, as shown in fig. 6, the groove 70 is an annular half-groove that is open at both the top and the outer side.
As shown in fig. 6, the top and the outer sides of the groove 70 are both open, i.e., the groove 70 is an annular half groove with both the top and the outer sides open. The cross-sectional shape of the groove 70 may be rectangular or L-shaped, for example, with a plane passing through the center of the substrate 10 and perpendicular to the substrate 10 as a cross-section.
In this embodiment, the recess 70 is located in the edge region 11, and the recess 70 is configured as an annular half-groove with an open top and an open outer side, which is advantageous for subsequent deposition of the dielectric layer 40 in the recess 70 to form the blocking layer 20 to block the device 31 of the edge region 11 from transferring charges to the substrate 10. In addition, the top and the outer side of the groove 70 are both open, so that the coverage of the dielectric layer 40 in the edge region 11 can be ensured, the charge is prevented from being transferred from the device 31 to the substrate 10 through the top and the outer side of the edge region 11, the protection of the semiconductor structure is further enhanced, and the yield of the semiconductor structure is improved.
In some embodiments, the dielectric layer 40 may be a single layer structure as shown in fig. 7, for example, the dielectric layer 40 is a silicon dioxide layer, a silicon nitride layer, or a silicon oxynitride layer.
In other embodiments, dielectric layer 40 includes multiple layers of dielectric material stacked in sequence. In some embodiments, as shown in fig. 8, the dielectric layer 40 includes three dielectric material layers, and the materials of the dielectric material layers may be the same or different, for example, the material of the dielectric material layer at the bottom layer may be silicon dioxide, the material of the dielectric material layer at the middle layer may be silicon nitride, and the material of the dielectric material layer at the top layer may be silicon oxynitride. That is, in the present embodiment, the dielectric layer 40 includes the silicon oxide layer 41, the silicon nitride layer 42 and the silicon oxynitride layer 43 stacked in this order, wherein the silicon oxide layer 41 is located at the bottommost layer, contacts with the bottom of the groove 70, and the silicon oxynitride layer 43 is located at the topmost layer, and is flush with the upper surface of the substrate 10.
In this embodiment, a plurality of dielectric material layers such as a silicon dioxide layer 41, a silicon nitride layer 42, and a silicon oxynitride layer 43 are sequentially stacked to form a dielectric layer 40 with a laminated structure, so that the dielectric layer 40 is used as a barrier layer 20 to block the device 31 in the edge region 11 from transferring charges to the substrate 10, and arc discharge is prevented from occurring during subsequent etching of the semiconductor structure. In addition, the stacked laminate structure enhances the charge blocking capability of the dielectric layer 40, further enhances the protection of the semiconductor structure and improves the yield of the semiconductor structure.
In other embodiments, as shown in fig. 9, the barrier layer 20 includes a P-type semiconductor layer 52 and an N-type semiconductor layer 51 stacked in the edge region 11, the N-type semiconductor layer 51 is located above the P-type semiconductor layer 52, and an interface between the P-type semiconductor layer 52 and the N-type semiconductor layer 51 forms a PN junction.
The P-type semiconductor layer 52 may be formed by doping trivalent impurities, which may be, for example, boron, aluminum, gallium, or indium elements, from the outer circumferential surface of the substrate 10 to the edge region 11 of the substrate 10. The N-type semiconductor layer 51 may be formed by doping a pentavalent impurity, which may be, for example, an element such as phosphorus, arsenic, antimony, or the like, from the outer peripheral surface of the substrate 10 to the edge region 11 of the substrate 10.
The N-type semiconductor layer 51 is located above the P-type semiconductor layer, and a PN junction is formed at the interface of the P-type semiconductor layer 52 and the N-type semiconductor layer 51, which is turned off in a direction from the device 31 toward the substrate 10, thereby blocking the device 31 of the edge region 11 from transferring charges to the substrate 10.
In this embodiment, the P-type semiconductor layer 52 and the N-type semiconductor layer 51 are stacked in the edge region 11, and the interface between the P-type semiconductor layer 52 and the N-type semiconductor layer 51 forms a PN junction. The PN junction is utilized to realize the cut-off along the direction from the device 31 to the substrate 10, so that the device 31 of the edge region 11 is blocked from transferring charges to the substrate 10, the arc discharge is prevented from happening when the semiconductor structure is etched later, the protection of the semiconductor structure is enhanced, and the yield of the semiconductor structure is improved.
It is appreciated that the formation of the barrier layer 20 may be performed simultaneously with the formation of the active region (ACTIVE AREA, abbreviated as AA) and the shallow trench isolation (Shallow Trench Isolation, abbreviated as STI) in the substrate 10, which may simplify the overall process of the semiconductor structure and reduce the production cost.
In some embodiments, as shown in fig. 7-9, the upper surface of the barrier layer 20 is flush with the upper surface of the substrate 10.
As shown in fig. 7 and 8, when the dielectric layer 40 as the barrier layer 20 has a single layer or a stacked structure, the upper surface thereof is flush with the upper surface of the substrate 10. As shown in fig. 9, the upper surface of the N-type semiconductor layer 51 located above in the barrier layer 20 is flush with the upper surface of the substrate 10, so that the upper surfaces of the different forms of the barrier layer 20 are all flush with the upper surface of the substrate 10.
While the upper surface of the barrier layer 20 is flush with the upper surface of the substrate 10, the peripheral edge of the barrier layer 20 is also flush with the peripheral edge of the substrate 10.
In this embodiment, the upper surface of the barrier layer 20 is flush with the upper surface of the substrate 10, and the outer peripheral surface of the barrier layer 20 is flush with the outer peripheral surface of the substrate 10, so that the barrier layer 20 is disposed on one hand, and the overall volume of the semiconductor structure is not increased, and on the other hand, other structures, such as the device layer 30, are also formed on the upper surface of the barrier layer 20 and the upper surface of the substrate 10.
In some embodiments, as shown in fig. 2, a plurality of pads 32 are also provided in the device layer 30 above the device 31, the plurality of pads 32 being for achieving metal bonding between the plurality of semiconductor structures.
In other embodiments, as shown in fig. 10 and 11, the device layer 30 further includes a top metal layer 33, an insulating layer 34, and a pad layer 35 sequentially stacked on top of each device 31, the pad layer 35 including a plurality of pads 32, and the insulating layer 34 having a via hole 36 formed therein corresponding to each pad 32, each pad 32 being electrically connected to the top metal layer 33 through the via hole 36.
The device layer 30 may further include a top metal layer 33, an insulating layer 34, and a pad layer 35 in addition to the devices 31 located in the edge region 11 and the middle region 12, wherein the top metal layer 33 is disposed on the devices 31, the insulating layer 34 is disposed on the top metal layer 33, and the pad layer 35 is disposed on the insulating layer 34.
The top metal layer 33 is used to form a redistribution layer and the pad layer 35 includes a plurality of pads 32, the plurality of pads 32 being used to effect metal bonding between the plurality of semiconductor structures. A plurality of via holes 36 are formed in the insulating layer 34, and the plurality of pads 32 are electrically connected to the top metal layer 33 or the rewiring layer through the via holes 36, respectively.
In one exemplary embodiment, as shown in fig. 12, the package structure provided by the embodiments of the present disclosure includes at least two semiconductor structures as described above bonded, the package structure having a trimming region 60, the trimming region 60 being located at a circumferential edge of the package structure and a width of the trimming region 60 being smaller than a width of the edge region 11.
The specific structure of the semiconductor structure may be referred to the related description in the above embodiments, and will not be repeated here. In some embodiments, as shown in fig. 12, the package structure includes two semiconductor structures bonded together, and, for example, as shown in fig. 13, the two semiconductor structures may be stacked and packaged by bonding a plurality of pads 32 over a device 31 of the two semiconductor structures one to one after inverting one of the two semiconductor structures.
After bonding the two semiconductor structures, a circle of bonding structures may have a difference in height and/or flatness around the bonding structures, which may result in incomplete bonding of the devices 31 located in the edge region 11, and may also result in the edges of the two semiconductor structures being suspended out of the air due to an error in alignment accuracy during bonding, which may cause edge breakage or damage of the bonding structures in the subsequent process of performing the thinning treatment, as shown in fig. 14.
Based on this, after bonding of the two semiconductor structures, a round of removal of the bond structure is typically required to ensure removal of the defects and alignment of the peripheral edges of the package structure. Illustratively, the peripheral edge of the bonding structure may be removed by cutting with a blade, and as shown in fig. 12 and 15, the bonding structure after removing the peripheral edge forms a package structure, and the package structure has a trimming area 60 at the peripheral edge thereof, where the trimming area 60 corresponds to the peripheral edge area of the bonding structure that needs to be removed. The width of the trimming region 60 is smaller than the width of the edge region 11, i.e. the trimming removes a portion of the device layer 30, the substrate 10 and the barrier layer 20 located in the edge region 11 after bonding of the two semiconductor structures, the device 31 located in the edge region 11 being partially removed.
In this embodiment, in the package structure formed by using the semiconductor structure provided in the above embodiment, because the barrier layer 20 is disposed in the semiconductor structure, arc discharge is prevented from occurring when the semiconductor structure is etched, so that protection of the semiconductor structure is enhanced, yield of the semiconductor structure is improved, and accordingly yield of the package structure is improved, and cost is reduced. In addition, the width of the trimming area 60 is smaller than that of the edge area 11, and the device 31 to be trimmed is basically an ineffective device in the package structure, so that the device 31 located in the edge area 11 is not wasted due to the barrier layer 20, and the waste of the effective area of the chip caused by the barrier layer 20 is avoided.
In some embodiments, as shown in FIG. 12, the width of the trimming region 60 is 1.5-3 mm, the height H1 of the barrier layer 20, the height H2 of the device layer 30, the height H3 of the trimming region 60, and the height H4 of the substrate 10 should satisfy the following relationship that H1. Ltoreq.H2-H4, wherein H3 is 150+ -15 mm.
The width of the trimming region 60 is 1.5-3 mm, the height H3 of the trimming region 60 is 150+ -15 mm, H1 is the height of the barrier layer 20, H2 is the height of the device layer 30, H4 is the height of the substrate 10, and H4 may be 775 μm.
The values of H1, H2, H3, H4 satisfy the relationship H1 < H3-2 < H2-H4, representing the height of the trimming region 60 minus the height of the two device layers 30 stacked after bonding minus the height of the substrate 10 should be greater than the height of the barrier layer 20, i.e., in the bottom semiconductor structure after trimming, the bottom surface of the remaining barrier layer 20 is not lower than the top surface of the substrate 10 below the trimming region 60.
In this embodiment, the width of the trimming area 60 is set to be 1.5-3 mm, and the height of the trimming area 60 is set to be 150±15mm, so that other structural defects caused by poor edge bonding degree can be avoided in other subsequent process procedures on the premise that excessive trimming is not performed to cause waste, and the yield of the packaging structure is improved.
In an exemplary embodiment, as shown in fig. 16, a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure includes:
S100, providing a substrate, wherein the substrate is provided with a middle area and an edge area surrounding the middle area;
S200, forming a barrier layer in the edge region of the substrate, including etching the edge region of the substrate, forming a groove which is positioned in the edge region and surrounds the middle region, and forming a dielectric layer in the groove, or forming a P-type semiconductor layer and an N-type semiconductor layer in the edge region of the substrate through a doping process, wherein the N-type semiconductor layer is positioned above the P-type semiconductor layer, and a PN junction is formed at the interface of the P-type semiconductor layer and the N-type semiconductor layer;
And S300, forming a device layer on the substrate and the barrier layer, wherein the device layer comprises devices positioned in the edge area and devices positioned in the middle area.
In step S100, the substrate 10 shown in fig. 4 is exemplarily provided, and the substrate 10 may be, for example, a silicon substrate, a silicon germanium substrate, a carbon silicon substrate, or the like, and the shape of the substrate 10 may be, for example, a circular shape as shown in fig. 3. The substrate 10 has a middle region 12 and an edge region 11 surrounding the middle region 12, i.e., the middle region 12 is a middle region of the substrate 10, the edge region 11 is a peripheral region of the substrate 10, and the edge region 11 is an annular region circumferentially disposed along the middle region 12.
In step S200, a blocking layer 20 is illustratively formed on the edge of the substrate 10, as shown in fig. 7,8 or 9, the blocking layer 20 is located in the edge region 11 of the substrate 10, the upper surface of the blocking layer 20 is flush with the upper surface of the substrate 10, the peripheral edge of the blocking layer 20 is flush with the peripheral edge of the substrate 10, and the blocking layer 20 is capable of blocking the devices 31 located on the edge region 11 in the subsequently formed device layer 30 from transferring charges to the substrate 10.
In some embodiments, as shown in fig. 17, the step S200 of forming the barrier layer 20 in the edge region 11 of the substrate 10 includes:
S211, etching an edge region of the substrate to form a groove which is positioned in the edge region and surrounds the middle region;
s212, forming a dielectric layer in the groove.
In step S211, the edge region 11 of the substrate 10 may be etched, for example, by a process such as wet etching, dry etching, or the like, to form a groove 70 located at the edge region 11 as shown in fig. 6, the groove 70 being disposed around the intermediate region 12 to form an annular groove located at the outer edge of the substrate 10. The upper and outer sides of the groove 70 are open, i.e. the groove is a half-groove with both the top and the outer sides open. The cross-sectional shape of the groove 70 may be rectangular or L-shaped, for example, with a plane passing through the center of the substrate 10 and perpendicular to the substrate 10 as a cross-section.
In step S212, the dielectric layer 40 as shown in fig. 7 or 8 is illustratively formed in the recess 70, and the width and thickness of the dielectric layer 40 are the same as the width and depth of the recess 70, and the dielectric layer 40 may be formed by thermal oxidation or plasma enhanced chemical vapor deposition, for example. The dielectric layer 40 is capable of blocking the transfer of charge from the device 31 of the edge region 11 to the substrate 10. Dielectric layer 40 includes at least one of a silicon dioxide layer, a silicon nitride layer, and a silicon oxynitride layer.
In this embodiment, the dielectric layer 40 formed in the recess 70 blocks the device 31 in the edge region 11 from transferring charges to the substrate 10, so as to prevent arcing during subsequent etching of the semiconductor structure, thereby enhancing the protection of the semiconductor structure and improving the yield of the semiconductor structure. In addition, the upper surface of the dielectric layer 40 is flush with the upper surface of the substrate 10, and the outer peripheral surface of the dielectric layer 40 is flush with the outer peripheral surface of the substrate 10, so that the dielectric layer 40 is disposed on the one hand, without increasing the overall volume of the semiconductor structure, and on the other hand, other structures, such as the device layer 30, are also formed on the upper surface of the dielectric layer 40 and the upper surface of the substrate 10.
In other embodiments, the step S200 of forming the barrier layer 20 on the edge region 11 of the substrate 10 includes:
S220, forming a P-type semiconductor layer and an N-type semiconductor layer in the edge area of the substrate through a doping process, wherein the N-type semiconductor layer is positioned above the P-type semiconductor layer, and a PN junction is formed at the interface of the P-type semiconductor layer and the N-type semiconductor layer.
In step S220, the P-type semiconductor layer 52 may be exemplarily formed by doping trivalent impurities, which may be, for example, boron, aluminum, gallium or indium elements, from the outer circumferential surface of the substrate 10 toward the edge region 11 of the substrate 10, and the N-type semiconductor layer 51 may be formed by doping pentavalent impurities, which may be, for example, phosphorus, arsenic or antimony elements, from the outer circumferential surface of the substrate 10 toward the edge region 11 of the substrate 10.
As shown in fig. 9, the N-type semiconductor layer 51 is located above the P-type semiconductor layer, the N-type semiconductor layer 51 is in electrical contact with the device 31 located in the edge region 11, and a PN junction is formed at the interface between the P-type semiconductor layer 52 and the N-type semiconductor layer 51, and the PN junction is cut off in a direction from the device 31 toward the substrate 10, so that the device 31 in the edge region 11 can be blocked from transferring charges to the substrate 10.
In this embodiment, the P-type semiconductor layer 52 and the N-type semiconductor layer 51 stacked in the edge region 11 are formed by doping, and a PN junction is formed at the interface between the P-type semiconductor layer 52 and the N-type semiconductor layer 51. The PN junction is utilized to realize the cut-off along the direction from the device 31 to the substrate 10, so that the device 31 of the edge region 11 is blocked from transferring charges to the substrate 10, the arc discharge is prevented from happening when the semiconductor structure is etched later, the protection of the semiconductor structure is enhanced, and the yield of the semiconductor structure is improved. In addition, the upper surface of the N-type semiconductor layer 51 is flush with the upper surface of the substrate 10, and the outer peripheral surfaces of the N-type semiconductor layer 51 and the P-type semiconductor layer 52 are flush with the outer peripheral surface of the substrate 10, so that the barrier layer 20 thus provided does not increase the overall volume of the semiconductor structure, and on the other hand, other structures, such as the device layer 30, are also formed on the upper surface of the barrier layer 20 and the upper surface of the substrate 10.
In step S300, a device layer 30 as shown in fig. 2 or 11 is illustratively formed on the substrate 10 and the barrier layer 20, where the device layer 30 is disposed on the substrate 10, and the device layer 30 includes a device 31 located in the edge region 11 of the substrate 10 and a device 31 located in the middle region 12, where the device 31 may be, for example, a mosfet, a dram, a sram, a mram, or the like, which performs a semiconductor structure function. During formation of device layer 30, the photoresist thickness of edge region 11 is typically greater than the photoresist thickness of intermediate region 12, and thus the photoresist of edge region 11 is typically removed, resulting in exposure of some or all of the metal layer of edge region 11, which may accumulate charge. Also provided in the device layer 30 are a plurality of bond pads 32 located above the device 31 as shown in fig. 2, the plurality of bond pads 32 being for effecting metal bonding between a plurality of semiconductor structures.
In this embodiment, by disposing the barrier layer 20 between the device layer 30 and the substrate 10, the barrier layer 20 is located in the edge region 11 of the substrate 10, and the device 31 in the edge region 11 can be blocked by the barrier layer 20 to transfer charges to the substrate 10, so as to prevent arcing during etching of the semiconductor structure, enhance the protection of the semiconductor structure, and improve the yield of the semiconductor structure.
In some embodiments, the step of forming the device layer 30 on the substrate 10 and the barrier layer 20 includes forming a plurality of devices 31 on the substrate 10 and the barrier layer 20, and forming a plurality of pads 32 over the devices 31 as shown in fig. 2, the plurality of pads 32 being for metal bonding between a plurality of semiconductor structure structures.
In other embodiments, as shown in fig. 18, the step of forming the device layer 30 on the substrate 10 and the barrier layer 20 includes:
S310, forming a plurality of devices on the substrate and the barrier layer;
S320, forming a top metal layer on the top of each device;
s330, forming an insulating layer on the top metal layer, wherein a plurality of through holes are formed in the insulating layer;
And S340, forming a bonding pad layer on the insulating layer, wherein the bonding pad layer comprises a plurality of bonding pads, and each bonding pad is electrically connected with the top metal layer through a corresponding via hole.
In step S310, a plurality of devices 31 may be formed on the substrate 10 and the barrier layer 20 by, for example, deposition, masking, etching, filling, etc., wherein a part of the devices 31 is disposed in the middle region 12 and another part of the devices 31 is disposed in the edge region 11, i.e., the devices 31 are divided into two parts, i.e., the devices 31 disposed in the edge region 11 and the devices disposed in the middle region 12.
In step S320, a top metal layer 33 is illustratively formed on top of each device 31, the top metal layer 33 may be, for example, an aluminum layer, a copper layer, or a copper alloy layer, and the top metal layer 33 is used to form a redistribution layer.
In step S330, an insulating layer 34 may be formed on the top metal layer 33 by a deposition process, for example, the insulating layer 34 may be made of silicon nitride, silicon carbide, silicon oxynitride, or the like, and then the insulating layer 34 is etched by an etching process to form a plurality of via holes 36 in the insulating layer 34, the via holes 36 are typically filled with a metal material to form conductive pillars, or the inner surfaces of the via holes 36 are deposited with a conductive layer, so that electrical connection between the top metal layer 33 and the pads 32 formed later is achieved through the via holes 36.
In step S340, the pad layer 35 illustratively includes a plurality of pads 32 for implementing metal bonding between two semiconductor structures, the pads 32 are formed by deposition, masking, etching, etc., and each pad 32 has a via 36 under it, and each pad 32 is electrically connected to the top metal layer 33 through a respective via 36.
In an exemplary embodiment, as shown in fig. 19, a method for manufacturing a package structure according to an embodiment of the present disclosure includes:
s400 providing at least two semiconductor structures as described above;
s500, bonding the semiconductor structures to form a bonding structure;
And S600, removing part of the edge structure of the bonding structure to form a packaging structure, wherein the packaging structure is provided with a trimming area, the trimming area is positioned at the peripheral edge of the packaging structure, and the width of the trimming area is smaller than that of the edge area.
In step S400, at least the semiconductor structure described above is provided, and the specific structure of the semiconductor structure may be referred to the related description in the above embodiment, which is not repeated here.
In step S500, the semiconductor structures are bonded, for example, as shown in fig. 13, and after one of the semiconductor structures is inverted, the bonding pads 32 above the devices 31 of the two semiconductor structures are bonded in a one-to-one correspondence to form the bonding structure shown in fig. 14.
In step S600, a circle around the bonding structure may cause incomplete bonding of the device 31 located in the edge region 11 due to the difference in height and/or flatness, and may also cause the edges of the two semiconductor structures to deviate and hang due to the error of alignment accuracy during bonding, which may cause damage or breakage of the edges of the bonding structure during the subsequent thinning process.
Based on this, after bonding of the two semiconductor structures, a round of removal of the bond structure is typically required to ensure removal of the defects and alignment of the peripheral edges of the package structure. Illustratively, the removal of the peripheral edge of the bonding structure may be performed by cutting with a blade, and as shown in fig. 12 and 15, the bonding structure after the removal of the peripheral edge forms a package structure, and the package structure has a trimming area 60 at the peripheral edge thereof, where the trimming area 60 corresponds to the peripheral edge area of the bonding structure that needs to be removed. The width of the trimming region 60 is smaller than the width of the edge region 11, i.e. the trimming removes a portion of the device layer 30, the substrate 10 and the barrier layer 20 located in the edge region 11 after bonding of the two semiconductor structures, the device 31 located in the edge region 11 being partially removed.
In this embodiment, in the package structure formed by bonding and trimming the semiconductor structure provided in the above embodiment, because the barrier layer 20 is disposed in the semiconductor structure, arc discharge is prevented from occurring when the semiconductor structure is etched, so that protection of the semiconductor structure is enhanced, yield of the semiconductor structure is improved, and thus yield of the package structure is improved, and cost is reduced. In addition, removing part of the edge structure of the bonding structure makes the package structure have a trimming area 60, the width of the trimming area 60 is smaller than that of the edge area 11, and the trimmed device 31 is basically an ineffective device in the package structure, so that the device 31 located in the edge area 11 is not wasted due to the arrangement of the barrier layer 20, and the waste of the effective area of the chip caused by the arrangement of the barrier layer 20 is avoided.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
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