CN119071102A - A data concurrent processing control system based on 485 bus - Google Patents
A data concurrent processing control system based on 485 bus Download PDFInfo
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- CN119071102A CN119071102A CN202411289692.6A CN202411289692A CN119071102A CN 119071102 A CN119071102 A CN 119071102A CN 202411289692 A CN202411289692 A CN 202411289692A CN 119071102 A CN119071102 A CN 119071102A
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- 238000012545 processing Methods 0.000 title claims abstract description 19
- 230000005540 biological transmission Effects 0.000 claims abstract description 38
- 238000004891 communication Methods 0.000 claims abstract description 6
- 208000033748 Device issues Diseases 0.000 claims abstract 2
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical compound O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 claims description 3
- 238000012544 monitoring process Methods 0.000 claims description 2
- 230000001934 delay Effects 0.000 claims 1
- 230000008859 change Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
- H04L12/16—Arrangements for providing special services to substations
- H04L12/18—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast
- H04L12/1881—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast with schedule organisation, e.g. priority, sequence management
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40045—Details regarding the feeding of energy to the node from the bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40169—Flexible bus arrangements
- H04L12/40176—Flexible bus arrangements involving redundancy
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/04—Protocols for data compression, e.g. ROHC
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/4026—Bus for use in automation systems
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Abstract
本发明公开了一种基于485总线数据并发处理控制系统，包括若干设备和将若干设备连接一起建立通信的485总线，每个设备上均设有控制器、485芯片、传感器，控制器的两个串口分别连接一个485芯片，其中一个485芯片与传感器连接，另一个485芯片与传感器连接；各设备实时监控485总线上的实时数据判断485总线是否处于空闲状态，485总线处于空闲状态时，若有设备发出数据传输请求，则在一个随机延时后往总线上进行数据广播，其他设备在收到这个广播数据，就会暂停进行数据数据发送，直至485总线重新处于空闲状态。此中控制器上的采集模块可对数据进行压缩过滤。通过本发明叙述的系统可以大大提高数据传输效率，并解决数据碰撞等问题。
The invention discloses a data concurrent processing control system based on 485 bus, including several devices and a 485 bus for connecting several devices to establish communication. Each device is provided with a controller, a 485 chip and a sensor. Two serial ports of the controller are respectively connected with a 485 chip, one of which is connected with the sensor, and the other is connected with the sensor. Each device monitors the real-time data on the 485 bus in real time to determine whether the 485 bus is in an idle state. When the 485 bus is in an idle state, if a device issues a data transmission request, data broadcast is performed on the bus after a random delay. When other devices receive the broadcast data, data transmission is suspended until the 485 bus is in an idle state again. The acquisition module on the controller can compress and filter the data. The system described by the invention can greatly improve the data transmission efficiency and solve the problems of data collision.
Description
Technical Field
The invention relates to the field of communication, in particular to a 485 bus data based concurrent processing control system.
Background
With the development of industrial automation and intelligence, the efficiency and stability of data transmission become particularly important. 485 bus is a serial communication interface widely used in industrial fields, and is favored for high reliability, strong anti-interference performance and long-distance transmission capability. However, in the conventional 485 bus data transmission method, a polling solution is generally adopted, as shown in fig. 1, a master station multi-slave station structure is adopted, if the master station needs to collect data of the slave stations, multiple polling needs to be performed, if the number of the slave stations is large, it often takes a long time to read all sensor data, the efficiency is low, the data transmission speed is slow, even the risk of data loss may exist, and the increasing data transmission requirement cannot be met.
Disclosure of Invention
The object of the present invention is to provide a 485 bus data based concurrent processing control system, which solves one or more of the above problems.
The invention provides a 485 bus data concurrent processing control system, which comprises a plurality of devices and a 485 bus for connecting the devices together to establish communication, wherein each device is provided with a controller, 485 chips and a sensor, two serial ports of the controller are respectively connected with one 485 chip, one 485 chip is connected with the sensor, and the other 485 chip is connected with the sensor;
each device monitors real-time data on the 485 bus in real time to judge whether the 485 bus is in an idle state, if the 485 bus is in the idle state, if a device sends a data transmission request, the device broadcasts data on the bus after random delay, and other devices pause data transmission until the 485 bus is in the idle state again after receiving the broadcast data.
In some embodiments of the present invention, in some embodiments,
The devices are connected with terminal matching resistors on the 485 bus in parallel in sequence;
The equipment is also provided with a power supply piece;
the controller is a singlechip.
In some embodiments of the present invention, in some embodiments,
The singlechip is an STM32 singlechip;
The power supply piece is a DCDC power supply.
In some embodiments, the controller is provided with an acquisition module, the acquisition module compresses and filters the data acquired by the 485 chip, if the data generates the change of the preset proportion, the data on the corresponding equipment is normally transmitted, otherwise, the data is not transmitted.
In some embodiments, a rule for judging that the 485 bus is in an idle state is preset in the controller, wherein the rule is that when the 485 bus is monitored in real time, if the time of no data on the 485 bus is longer than the preset idle time, the current 485 bus is judged to be in the idle state, otherwise, the 485 bus is judged to be busy.
In some embodiments, the preset idle duration is 3 bytes of time.
In some embodiments, when the 485 bus is in an idle state and a plurality of devices send data transmission requests, the waiting times of the devices sending the data transmission requests are all 0, the random reference time of each device is screened out in the preset random reference time range of the system, the devices with small random reference time broadcast data to the 485 bus in preference to the devices with large random reference time, when one device on the 485 bus broadcasts data, the waiting times of other devices sending the data transmission requests are increased by 1, when the data transmission of the devices sending the data broadcast on the 485 bus is finished, the other devices sending the data transmission requests set random delay, and the devices with small random delay time broadcast data to the 485 bus in preference to the devices with long random delay time, so the cycle execution is performed until the devices sending the data transmission requests finish.
In some embodiments of the present invention, in some embodiments,
The random delay is X, which is the preset threshold value-waiting times, of the random reference time;
the system random reference time is greater than or equal to 1.5 byte time.
In some embodiments of the present invention, in some embodiments,
The preset threshold value is 4;
the system random reference time is 1.5 bytes to 5 bytes in time.
In some embodiments, the system random reference time range is 2-5ms.
The 485 bus data based concurrent processing control system has the advantages that:
1. The acquisition end has the compression processing capability on data, and the data is transmitted only when the data changes within a certain range, so that the expenditure of a 485 bus is greatly saved;
2. The problem of 485 bus data concurrency is solved by monitoring the bus, sending a transmission command by the phase bus, randomly delaying and the like;
3. 256 devices can be suspended on the 485 bus at maximum, and the traditional acquisition time which needs to be 30s or longer can be shortened to be within 2s through the control system, so that the acquisition efficiency is greatly improved.
Drawings
FIG. 1 is a conventional 485 network bus topology;
FIG. 2 is a 485 bus topology in some embodiments of the invention;
FIG. 3 is a flow chart illustrating the transmission of a 485 bus based data concurrency process control system in some embodiments of the present invention;
FIG. 4 is a flow chart of an acquisition process control system based on 485 bus data concurrency in some embodiments of the present invention;
Fig. 5 is a schematic diagram of a hardware framework of a device in some embodiments of the invention.
Detailed Description
Referring to fig. 2 to 5, a 485 bus data concurrency processing control system is provided in this embodiment, which includes a plurality of devices (such as device 1 to device n shown in fig. 1, n is less than or equal to 256) and a 485 bus for connecting the devices together to establish communication, wherein each device is provided with a controller, a 485 chip and a sensor, two serial ports of the controller are respectively connected with one 485 chip, one 485 chip is connected with the sensor, and the other 485 chip is connected with the sensor;
Each device monitors real-time data on the 485 bus in real time to judge whether the 485 bus is in an idle state, when the 485 bus is in the idle state, the device can send a data transmission request, if the device sends the data transmission request, the device broadcasts data on the bus after random delay, and other devices can pause data transmission until the 485 bus is in the idle state again after receiving the broadcast data. The devices are connected with the terminal matching resistor on the 485 bus in parallel in sequence, the power supply piece can be directly arranged on the devices, the power supply piece can be a DCDC power supply, the controller can be a singlechip, such as an STM32 singlechip, and sensors on the devices can be replaced by other embedded devices.
The controller is provided with an acquisition module, the acquisition module can compress and filter the data acquired through the 485 chip (the compression and filtration process can be directly realized by adopting the prior art, and therefore, the repeated description is omitted here), the data acquired by the 485 chip comprises the data of the sensor, the data of the controller and the like, if the data generate the change in the preset proportion, the data on the corresponding equipment are normally transmitted, otherwise, the data are not transmitted (for example, the preset proportion is less than 2%, the switching value data are overturned from 0 to 1, the analog value is changed by 2%, the data are considered to be changed beyond the preset proportion, and the data are not transmitted). And re-reading the equipment data (namely re-acquiring the data through the 485 chip by the corresponding acquisition module) when the data is not transmitted or the data exceeds a preset time length and is not transmitted.
The controller is preset with a rule for judging that the 485 bus is in an idle state, wherein the rule is that when the 485 bus is monitored in real time, if the time of no data on the 485 bus is longer than the preset idle time, the current 485 bus is judged to be in the idle state, otherwise, the 485 bus is judged to be busy. The preset idle time length can be set according to the requirement, for example, the preset idle time length is set to be one of 1.5 byte time, 2 byte time and 3 byte time, and when the preset idle time length is set to be 3 byte time, the compatibility of the equipment on the 485 bus can be better achieved, and the universality is improved. Taking the preset idle duration set to 3 byte time as an example, if the baud of the current 485 bus is 9600, the single byte time is about 1.05ms, and the 3 byte time is about 3.2ms.
In combination with the content shown in fig. 3, when a 485 bus is in an idle state and a plurality of devices send data transmission requests, the waiting times of the devices sending the data transmission requests are all 0, the random reference time of each device is screened out in the range of the preset system random reference time, the devices with small random reference time broadcast data to the 485 bus in preference to the devices with large random reference time, when one device on the 485 bus broadcasts data, the bus is busy, the other devices sending the data transmission requests enter waiting time and the waiting times are increased by 1, when the data transmission of the devices on the 485 bus for data broadcasting is finished, the other devices sending the data transmission requests set random delay, the devices with small random delay time broadcast data to the 485 bus in preference to the devices with large random delay time, and the cycle execution is performed until the devices sending the data transmission requests are finished, wherein the random delay time is X, the random reference time is the random reference time, the X is the preset threshold value-the waiting times, the preset threshold value can be 4, and the specific preset threshold value can be adjusted according to the number of points of data on the network, the data quantity of the network and the like. For example, in the present stage, the device 2 and the device 3 need to perform data transmission, the random reference time screened by the device 2 is 3ms, the random time screened by the device 3 is 2.5ms, the current waiting times are all 0, because the random delay time of the device 3 is smaller than that of the device 2, the device 3 firstly broadcasts a data to the bus, the device 2 receives the data broadcast, the data can not be sent to the bus, the waiting times are increased by 1 in the system, the waiting times of the device 2 are 1, and after the transmission of the device 3 is completed, the device 2 resets the delay time, and then performs data transmission according to the method.
The system random reference time in the system random reference time range is greater than or equal to 1.5 byte time, the upper limit is not required, but the data transmission efficiency is reduced due to the fact that the upper limit is too high, and therefore the system random reference time range can be set to be 1.5 byte time to 5 byte time, for example, 2-5ms.
The screening of the random reference time of each device can be directly carried out by adopting random screening, and the random reference time is controlled within the random reference time range of the system.
The above-mentioned undisclosed matters can be realized by adopting the prior art, so that the details are not repeated here.
It will be apparent to those skilled in the art that several similar modifications and improvements can be made without departing from the inventive concept, and these should also be considered as being within the scope of the invention.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202411289692.6A CN119071102A (en) | 2024-09-14 | 2024-09-14 | A data concurrent processing control system based on 485 bus |
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| CN202411289692.6A CN119071102A (en) | 2024-09-14 | 2024-09-14 | A data concurrent processing control system based on 485 bus |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6493351B1 (en) * | 1999-04-21 | 2002-12-10 | Nortel Networks Ltd. | Collision detection on a differential bus |
| CN101163075A (en) * | 2006-10-10 | 2008-04-16 | 中兴通讯股份有限公司 | Method of implementing embedded device address installation by RS 485 bus competition |
| CN102546141A (en) * | 2012-02-20 | 2012-07-04 | 杭州海康威视系统技术有限公司 | 485 bus system and asynchronous half-duplex communication method thereof |
| CN113395187A (en) * | 2021-05-27 | 2021-09-14 | 深圳市常工电子计算机有限公司 | 485 bus based communication enhancement method and system |
| CN114301729A (en) * | 2021-12-22 | 2022-04-08 | 北京海林自控科技股份有限公司 | Bus communication address allocation method and system based on NTC |
| CN116582384A (en) * | 2023-04-19 | 2023-08-11 | 青岛海信日立空调系统有限公司 | 485 bus-based communication method and intelligent home system |
-
2024
- 2024-09-14 CN CN202411289692.6A patent/CN119071102A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6493351B1 (en) * | 1999-04-21 | 2002-12-10 | Nortel Networks Ltd. | Collision detection on a differential bus |
| CN101163075A (en) * | 2006-10-10 | 2008-04-16 | 中兴通讯股份有限公司 | Method of implementing embedded device address installation by RS 485 bus competition |
| CN102546141A (en) * | 2012-02-20 | 2012-07-04 | 杭州海康威视系统技术有限公司 | 485 bus system and asynchronous half-duplex communication method thereof |
| CN113395187A (en) * | 2021-05-27 | 2021-09-14 | 深圳市常工电子计算机有限公司 | 485 bus based communication enhancement method and system |
| CN114301729A (en) * | 2021-12-22 | 2022-04-08 | 北京海林自控科技股份有限公司 | Bus communication address allocation method and system based on NTC |
| CN116582384A (en) * | 2023-04-19 | 2023-08-11 | 青岛海信日立空调系统有限公司 | 485 bus-based communication method and intelligent home system |
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