CN119087738B - Layout correction method, storage medium and terminal - Google Patents
Layout correction method, storage medium and terminalInfo
- Publication number
- CN119087738B CN119087738B CN202411137065.0A CN202411137065A CN119087738B CN 119087738 B CN119087738 B CN 119087738B CN 202411137065 A CN202411137065 A CN 202411137065A CN 119087738 B CN119087738 B CN 119087738B
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- layout
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- correction
- pattern
- optical proximity
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/72—Repair or correction of mask defects
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
一种版图的修正方法、存储介质及终端，其中版图的修正方法包括：提供初始版图，初始版图包括若干主图形；采用基于规则的辅助图形生成方法在初始版图中生成若干第一辅助图形；对主图形进行光学邻近修正迭代处理，且在每次光学邻近修正的过程中基于辅助图形进行光刻工艺窗口的优化运算。较基于仅基于规则插入亚分辨率辅助图形的版图修正方式相比，由于在每次光学邻近修正的过程中，增加基于辅助图形进行光刻工艺窗口的优化运算，有效提高版图修正的光刻工艺窗口；较基于反演光刻技术的版图修正方式相比，采用基于规则生成若干第一辅助图形，且在基于辅助图形的光刻工艺窗口优化运算过程中，避免采用像素化的计算方式，有效提升版图修正的计算效率。
A layout correction method, storage medium, and terminal are disclosed. The layout correction method includes: providing an initial layout, the initial layout including several main graphics; generating several first auxiliary graphics in the initial layout using a rule-based auxiliary graphics generation method; performing iterative optical proximity correction on the main graphics, and optimizing the photolithography process window based on the auxiliary graphics during each optical proximity correction. Compared to a layout correction method based solely on rule-based insertion of sub-resolution auxiliary graphics, the photolithography process window of the layout correction is effectively improved by adding the photolithography process window optimization calculation based on the auxiliary graphics during each optical proximity correction. Compared to a layout correction method based on inversion lithography, the rule-based generation of several first auxiliary graphics and the avoidance of pixelation calculation during the photolithography process window optimization calculation based on the auxiliary graphics effectively improve the computational efficiency of the layout correction.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a layout correction method, a storage medium, and a terminal.
Background
Integrated circuit fabrication technology is a complex process and technology is rapidly updated. One critical parameter that characterizes integrated circuit fabrication technology is the minimum feature size, i.e., critical dimension (critical dimension, CD), which, as critical dimensions shrink, even to the nanometer scale, makes it possible to place millions of devices on each chip, just as critical dimensions shrink.
Photolithography is a driving force for the development of integrated circuit fabrication processes and is one of the most complex techniques. The improvement in lithography is of great importance for the development of integrated circuits relative to other single fabrication techniques. Before the photolithography process begins, the pattern is first transferred to the reticle by a specific apparatus, and then the patterned structure on the reticle is transferred to the silicon wafer from which the chip is fabricated by generating light of a specific wavelength through the photolithography apparatus. However, due to the shrinking dimensions of semiconductor devices, distortion may occur during the transfer of the pattern to the silicon wafer, which may result in failure of the overall fabrication technique if not eliminated. Therefore, in order to solve the problem, optical proximity correction (Optical Proximity Correction, OPC) can be performed on the mask, i.e. pre-processing is performed on the photolithography mask, and modification is performed in advance, so that the amount of modification compensation can just compensate the optical proximity effect caused by the exposure system.
However, there are still a number of problems with layout modification in the prior art.
Disclosure of Invention
The invention solves the technical problem of providing a layout correction method, a storage medium and a terminal so as to improve the photoetching process window and the calculation efficiency of layout correction.
In order to solve the problems, the technical scheme of the invention provides a layout correction method, which comprises the steps of providing an initial layout, generating a plurality of first auxiliary graphics in the initial layout by adopting a rule-based auxiliary graphics generation method, forming an intermediate layout on the initial layout, carrying out optical proximity correction iterative processing on the main graphics, and carrying out optimization operation of a photoetching process window based on the auxiliary graphics in the optical proximity correction process each time, so that the intermediate layout forms a corrected layout.
Optionally, the method for performing the optimization operation of the lithography process window based on the auxiliary graph comprises the step of adjusting the shape and the position of the first auxiliary graph.
Optionally, the method of adjusting the shape of the first auxiliary pattern includes adjusting one or both of a length dimension and a width dimension of the first auxiliary pattern.
Optionally, the method for adjusting the position of the first auxiliary graph comprises adjusting the size of the interval between the first auxiliary graph and the main graph or adjusting the size of the interval between the adjacent first auxiliary graphs.
Optionally, the method for carrying out the optimization operation of the photoetching process window based on the auxiliary graph further comprises the step of generating a plurality of second auxiliary graphs in the intermediate layout.
Optionally, the first auxiliary pattern and the second auxiliary pattern are sub-resolution auxiliary patterns.
Optionally, the optical proximity correction comprises a fragmented optical proximity correction.
Optionally, the method for performing the fragmented optical proximity correction on the main graph comprises dividing each side length of the main graph into a plurality of correction line segments, and performing translation processing on each correction line segment along a direction perpendicular to the correction line segment.
Optionally, an evaluation function based on edge placement error directs an iterative correction direction of the fragmented optical proximity correction.
Optionally, the evaluation function based on the bandwidth of the photolithography process variation directs the iterative operation direction of the optimization operation of the photolithography process window.
Correspondingly, the technical scheme of the invention also provides a storage medium, on which computer instructions are stored, wherein the computer instructions execute the steps of the method in any one of the technical schemes when running.
Correspondingly, the technical scheme of the invention also provides a terminal which comprises a memory and a processor, wherein the memory stores computer instructions capable of running on the processor, and the processor executes the steps of the method in any one of the technical schemes when running the computer instructions.
Compared with the prior art, the technical scheme of the invention has the following advantages:
In the layout correction method of the technical scheme of the invention, a rule-based auxiliary pattern generation method is adopted to generate a plurality of first auxiliary patterns in the initial layout, and the optimization operation of the photoetching process window is carried out based on the auxiliary patterns in each optical proximity correction process. Compared with the layout correction mode based on the inversion lithography technology, the layout correction mode based on the rule is adopted to generate a plurality of first auxiliary graphs, and in the optimization operation process of the lithography process window based on the auxiliary graphs, the calculation mode of pixelation is avoided, so that the calculation efficiency of the layout correction can be effectively improved.
Further, the optical proximity correction includes a fragmented optical proximity correction. Compared with a layout correction mode based on inversion lithography, the method avoids adopting a pixelated calculation mode and can further improve the calculation efficiency of layout correction.
Drawings
FIG. 1 is a schematic flow diagram of a layout modification method according to an embodiment of the present invention;
fig. 2 to 6 are schematic structural diagrams of steps of a layout correction method according to an embodiment of the present invention.
Detailed Description
As described in the background, there are still a number of problems with layout modification in the prior art. The following will specifically explain.
In order to increase the contrast of the pattern during the optical proximity correction, a target pattern and a sub-resolution auxiliary pattern (Sub Resolution Assist Feature, SRAF) are usually formed on the mask, wherein the sub-resolution auxiliary pattern is a surrounding pattern that generates an optical proximity effect on the target pattern, and is not formed on the wafer after exposure, and the sub-resolution auxiliary pattern is selected from various stripes, boxes, and the like. The prior art typically collects wafer data by selecting an image plane (IMAGE PLANE) in the middle of the photoresist layer to calibrate an optical proximity correction model (model) of the main pattern (MAIN PATTERN), and then uses the calibrated model to simulate the main pattern under normal conditions and to simulate the sub-resolution auxiliary pattern under overexposure conditions.
There are two general ways of inserting sub-resolution auxiliary patterns in the industry at present, one way is based on a rule insertion way, the process generally obtains a rule of inserting a fixed sub-resolution auxiliary pattern through design experiments, and inserts the sub-resolution auxiliary pattern before optical proximity correction is operated, and the other way is to obtain a rule of freely inserting the sub-resolution auxiliary pattern in the operation process through inversion lithography (Inverse Lithography Technology, ILT). The method comprises the steps of inserting sub-resolution auxiliary patterns based on rules, performing fragmented optical proximity correction iteration processing on a main pattern, and not changing the pattern shape and position of the sub-resolution auxiliary patterns in the fragmented optical proximity correction process, performing pixelation calculation on the main pattern and the sub-resolution auxiliary patterns based on an inversion lithography technology, correcting the main pattern and the sub-resolution auxiliary patterns by using a plurality of evaluation functions (cost functions), and performing pixelation movement on the sub-resolution auxiliary patterns in the correction process.
However, the former layout modification approach has limited ability to raise the photolithography process window, but is run-time fast. The latter layout modification mode can greatly improve the photoetching process window, but the operation time is too long.
On the basis, the invention provides a layout correction method, a storage medium and a terminal, wherein a rule-based auxiliary pattern generation method is adopted to generate a plurality of first auxiliary patterns in the initial layout, and optimization operation of a photoetching process window is carried out based on the auxiliary patterns in each optical proximity correction process. Compared with the layout correction mode based on the inversion lithography technology, the layout correction mode based on the rule is adopted to generate a plurality of first auxiliary graphs, and in the optimization operation process of the lithography process window based on the auxiliary graphs, the calculation mode of pixelation is avoided, so that the calculation efficiency of the layout correction can be effectively improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
FIG. 1 is a schematic flow diagram of a layout modification method according to an embodiment of the present invention, including:
step S101, providing an initial layout, wherein the initial layout comprises a plurality of main graphs;
Step S102, generating a plurality of first auxiliary graphics in the initial layout by adopting a rule-based auxiliary graphics generation method, so that the initial layout forms an intermediate layout;
And step S103, performing optical proximity correction iterative processing on the main pattern, and performing optimization operation of a photoetching process window based on the auxiliary pattern in each optical proximity correction process, so that the middle layout forms a correction layout.
The following describes the steps of the layout correction method in detail with reference to the drawings.
Fig. 2 to 6 are schematic structural diagrams of steps of a layout correction method according to an embodiment of the present invention.
Referring to fig. 2, an initial layout is provided, which includes a number of main patterns 100.
In this embodiment, the main pattern 100 is a pattern that can be exposed and developed on the photoresist in a subsequent process, and a pattern corresponding to an actual functional device is formed on the wafer.
Referring to fig. 3, a rule-based auxiliary graph generating method is adopted to generate a plurality of first auxiliary graphs 101 in the initial layout, so that the initial layout forms an intermediate layout.
It should be noted that, the first auxiliary patterns 101 are inserted between the main patterns 100 by using a rule-based SRAF (rule-based SRAF) generating method, that is, according to an empirically manually preset configuration rule, a plurality of first auxiliary patterns 101 are inserted in the gaps between the main patterns 100 in combination with the gap positions and the shapes between the main patterns 100, and the number and the corresponding positions of the first auxiliary patterns 101 to be inserted. After the first auxiliary pattern 101 is generated, the position between the first auxiliary pattern 101 and the main pattern 100 is detected, and the position and the size of the first auxiliary pattern 101 are adjusted according to the detected condition.
In this embodiment, the first auxiliary pattern 101 is a resolution auxiliary pattern (Sub Resolution Assist Feature, SRAF), and the sub-resolution auxiliary pattern is a more adopted optical proximity correction method. The method has the characteristics that the isolated pattern and the sparse pattern also have dense patterns by adding the isolated pattern and the sparse pattern near the main pattern 100 of the layout, so that the light intensity distribution is improved, and the imaging quality is improved. The sub-resolution assist feature cannot be imaged because the line width of the sub-resolution assist feature is small where the intensity of the diffracted light is less than the photoresist threshold on the substrate (e.g., silicon wafer).
Referring to fig. 4, the main pattern 100 is subjected to iterative processing of optical proximity correction, and optimization operation of a photolithography process window is performed based on an auxiliary pattern in each optical proximity correction process, so that the intermediate pattern forms a corrected pattern.
And generating a plurality of first auxiliary patterns 101 in the initial layout by adopting a rule-based auxiliary pattern generation method, and carrying out optimization operation of a photoetching process window based on the auxiliary patterns in the process of optical proximity correction each time. Compared with the layout correction mode based on the inversion lithography technology, the layout correction mode based on the rule is adopted to generate a plurality of first auxiliary graphs 101, and in the optimization operation process of the lithography process window based on the auxiliary graphs, the calculation mode of pixelation is avoided, so that the calculation efficiency of the layout correction can be effectively improved.
In this embodiment, the method for performing the optimization operation of the photolithography process window based on the auxiliary pattern includes adjusting the shape and position of the first auxiliary pattern 101.
With continued reference to fig. 4, in the present embodiment, the method for adjusting the shape of the first auxiliary pattern 101 includes adjusting one or both of a length dimension and a width dimension of the first auxiliary pattern 101.
With continued reference to fig. 4, in the present embodiment, the method for adjusting the position of the first auxiliary pattern 101 includes adjusting the size of the space between the first auxiliary pattern 101 and the main pattern 100, or adjusting the size of the space between adjacent first auxiliary patterns 101.
With continued reference to fig. 4, in this embodiment, the method for performing the optimization operation of the photolithography process window based on the auxiliary patterns further includes generating a plurality of second auxiliary patterns 102 in the intermediate layout.
In this embodiment, the second auxiliary pattern 102 is also a sub-resolution auxiliary pattern.
In this embodiment, the optical proximity correction uses fragmented optical proximity correction. Compared with a layout correction mode based on inversion lithography, the segmented optical proximity correction is adopted for correction of the main graph 100, so that a pixelation calculation mode is avoided, and the calculation efficiency of layout correction can be further improved.
In this embodiment, the method for performing the fragmented optical proximity correction on the main pattern 100 includes dividing each side length of the main pattern 100 into a plurality of correction line segments (not labeled), and performing a translation process on each correction line segment along a direction perpendicular to the correction line segment.
In this embodiment, the method for dividing each side length of the main graph 100 into a plurality of correction line segments includes setting a plurality of segment points (not shown) on each side length of the main graph 100, and one correction line segment is located between adjacent segment points.
In this embodiment, an evaluation function (EPE cost function) based on an edge placement Error (EDGE PLACEMENT Error, EPE) directs the iterative correction direction of the fragmented optical proximity correction, where the evaluation function of edge placement Error is:
And EPE n is the edge placement error corresponding to each corrected line segment.
Referring to fig. 5, in this embodiment, the method for obtaining the edge placement error of each corrected line segment includes obtaining an exposure pattern 103 corresponding to the main pattern 100 after the fragmented optical proximity correction, and comparing the exposure pattern 103 with the main pattern 100 in the initial layout to obtain the edge placement error. The two measurement points P1 of the edge placement error are the center point of each correction line segment in the main pattern 100 and the point on the exposure pattern 103 corresponding to the direction perpendicular to the correction line segment, and the distance between the two measurement points P1 is the edge placement error.
Since the smaller the value of the edge placement error is, the higher the matching degree between the exposure pattern 103 and the main pattern 100 is, the value of the evaluation function of the edge placement error needs to be gradually reduced after each iterative process of optical proximity correction.
In this embodiment, the iterative operation direction of the optimization operation of the photolithography process window is guided based on an evaluation function (PV band cost function) of the photolithography process variation bandwidth, where the evaluation function of the photolithography process variation bandwidth is:
And PVband n is the photolithographic process variation bandwidth corresponding to each correction line segment.
Referring to fig. 6, in this embodiment, the method for obtaining the bandwidth of the photolithography process variation of each corrected line segment includes obtaining two worst exposure patterns of the main pattern 100 after the optical proximity correction, that is, a first worst exposure pattern 104 under a forward direction deviating from the optimal exposure condition and a second worst exposure pattern 105 under a reverse direction deviating from the optimal exposure condition, and comparing the cores of the first worst exposure pattern 104 and the second worst exposure pattern 105 to obtain the bandwidth of the photolithography process variation. The two measurement points P2 of the photolithography process variation bandwidth are the center point of each correction line segment in the main pattern 100, and the points on the first worst exposure pattern 104 and the second worst exposure pattern 105 corresponding to the direction perpendicular to the correction line segment, and the space size between the two measurement points P2 is the photolithography process variation bandwidth.
Since the smaller the value of the photolithography process variation bandwidth is, the higher the photolithography process window is, the value of the evaluation function of the photolithography process variation bandwidth needs to be gradually reduced after each optimization operation of the photolithography process window.
Accordingly, in an embodiment of the present invention, there is further provided a storage medium having stored thereon computer instructions that when executed perform the steps of the method according to any one of the embodiments described above.
Correspondingly, the embodiment of the invention also provides a terminal which comprises a memory and a processor, wherein the memory stores computer instructions capable of running on the processor, and the processor executes the steps of the method in any one of the embodiments when running the computer instructions.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (12)
1. A layout correction method is characterized by comprising the following steps:
Providing an initial layout, wherein the initial layout comprises a plurality of main graphs;
Generating a plurality of first auxiliary graphics in the initial layout by adopting a rule-based auxiliary graphics generation method, so that the initial layout forms an intermediate layout;
And performing optical proximity correction iterative processing on the main pattern, and performing optimization operation of a photoetching process window based on the auxiliary pattern in the optical proximity correction process each time so that the middle layout forms a correction layout.
2. The method for modifying a layout according to claim 1, wherein the optimizing operation of the photolithography process window based on the auxiliary pattern comprises adjusting the shape and position of the first auxiliary pattern.
3. The method for modifying a layout according to claim 2, wherein the method for adjusting the shape of the first auxiliary pattern comprises adjusting one or both of a length dimension and a width dimension of the first auxiliary pattern.
4. The method for correcting a layout according to claim 2, wherein the method for adjusting the position of the first auxiliary pattern comprises adjusting a pitch size between the first auxiliary pattern and the main pattern or adjusting a pitch size between adjacent first auxiliary patterns.
5. The method for modifying a layout according to claim 2, wherein the method for performing the optimization operation of the lithography process window based on the auxiliary patterns further comprises generating a plurality of second auxiliary patterns in the intermediate layout.
6. The method for modifying a layout according to claim 5, wherein the first auxiliary pattern and the second auxiliary pattern are sub-resolution auxiliary patterns.
7. The method for modifying a layout according to claim 1, wherein the optical proximity correction includes fragmented optical proximity correction.
8. The layout correction method according to claim 7, wherein the method for performing the fragmented optical proximity correction on the main pattern comprises dividing each side length of the main pattern into a plurality of correction line segments, and performing translation processing on each correction line segment along a direction perpendicular to the correction line segment.
9. A method of modifying a layout according to claim 8, wherein the iterative modification direction of the fragmented optical proximity modification is guided based on an evaluation function of edge placement errors.
10. A layout modification method according to claim 1, wherein the iterative operation direction of the optimization operation of the photolithography process window is guided based on an evaluation function of the photolithography process variation bandwidth.
11. A storage medium having stored thereon computer instructions which, when run, perform the steps of the method of any of claims 1 to 10.
12. A terminal comprising a memory and a processor, the memory having stored thereon computer instructions executable on the processor, wherein the processor, when executing the computer instructions, performs the steps of the method of any of claims 1 to 10.
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| CN117631436A (en) * | 2023-12-08 | 2024-03-01 | 深圳晶源信息技术有限公司 | Sub-resolution auxiliary graph optimization method, system and storage medium |
| CN118363250A (en) * | 2023-01-17 | 2024-07-19 | 中芯国际集成电路制造(上海)有限公司 | Layout correction method |
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| US8732625B2 (en) * | 2007-06-04 | 2014-05-20 | Asml Netherlands B.V. | Methods for performing model-based lithography guided layout design |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118363250A (en) * | 2023-01-17 | 2024-07-19 | 中芯国际集成电路制造(上海)有限公司 | Layout correction method |
| CN117631436A (en) * | 2023-12-08 | 2024-03-01 | 深圳晶源信息技术有限公司 | Sub-resolution auxiliary graph optimization method, system and storage medium |
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