CN119088631A - A chip register verification method, device, equipment and medium - Google Patents
A chip register verification method, device, equipment and medium Download PDFInfo
- Publication number
- CN119088631A CN119088631A CN202411570872.1A CN202411570872A CN119088631A CN 119088631 A CN119088631 A CN 119088631A CN 202411570872 A CN202411570872 A CN 202411570872A CN 119088631 A CN119088631 A CN 119088631A
- Authority
- CN
- China
- Prior art keywords
- register
- chip
- script
- module
- verification
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2247—Verification or detection of system hardware configuration
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Debugging And Monitoring (AREA)
Abstract
本发明提供了一种芯片寄存器的验证方法、装置、设备及介质，通过获取待验证芯片中寄存器的参数信息并处理得到设定格式的数据；基于所述设定格式的数据通过脚本生成含不同设定值的寄存器相关文件；通过所述脚本将所述寄存器相关文件集成到验证环境，以根据不同设定值对待验证芯片中寄存器进行自动化验证。利用脚本将设定格式的数据转换成寄存器相关文件，不仅提高了验证的效率，还能够提高验证的复用性，而利用不同的设定值对芯片寄存器进行验证，能够实现对芯片寄存器的充分验证，提高了对寄存器映射问题检测的准确性。
The present invention provides a chip register verification method, device, equipment and medium, which obtains parameter information of registers in a chip to be verified and processes to obtain data in a set format; generates register-related files containing different set values through a script based on the data in the set format; and integrates the register-related files into a verification environment through the script to automatically verify the registers in the chip to be verified according to different set values. Using a script to convert the data in the set format into a register-related file not only improves the efficiency of verification, but also improves the reusability of verification, and using different set values to verify the chip registers can achieve full verification of the chip registers and improve the accuracy of detecting register mapping problems.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a method, an apparatus, a device, and a medium for verifying a chip register.
Background
In digital chips, registers play a very important role, and the circuit can change its behavior according to the register values, thus realizing different modes or functions. The chip verification environment built based on UVM generally uses a register model to configure registers, so as to simplify the configuration process and reduce the verification workload. Because the general register description of the digital chip is in the form of an excel table, although the content of each module register can be presented simply and clearly, the excel table cannot be directly converted into a ralf file or a register model, which forms a certain barrier to the verification of the digital chip.
Currently, in most digital chip verification, after generating a UVM register model, for checking a register, only a sequence of a UVM library, such as UVM _reg_access_seq, is generally used, and the register is checked by a combination of front gate access and back gate access. The method is simple and convenient, but has limitations, and the main problem of the method is that the sequence carried by UVM only uses default values for reading and writing operations on registers, the default values of a plurality of registers are usually fixed values, if only a single fixed value is used for reading and writing inspection, the problem of wrong mapping of the registers in a chip is difficult to find, thus the verification of the registers of the chip is insufficient, and obvious bug carry-over can occur after front-end verification.
Therefore, a method, apparatus, device and medium for verifying a chip register are needed to improve the above-mentioned problems.
Disclosure of Invention
The invention aims to provide a verification method, device, equipment and medium for a chip register, which can improve the verification efficiency and reusability and the accuracy of register mapping problem detection.
In a first aspect, the present invention provides a method for verifying a chip register, including:
Acquiring parameter information of a register in a chip to be verified and processing the parameter information to obtain data in a set format;
Generating a register related file containing different set values through a script based on the data in the set format;
and integrating the register related file into a verification environment through the script so as to automatically verify the register in the chip to be verified according to different set values.
The method has the advantages that parameter information of the register in the chip to be verified is obtained and data in a set format is obtained through processing, the register related files containing different set values are generated through scripts based on the data in the set format, and the register related files are integrated into a verification environment through the scripts so as to automatically verify the register in the chip to be verified according to the different set values. The script is utilized to convert the data with the set format into the relevant register file, so that the verification efficiency is improved, the verification reusability is also improved, the chip registers are verified by utilizing different set values, the chip registers can be fully verified, and the accuracy of detecting the register mapping problem is improved.
Optionally, automatically verifying the register in the chip to be verified according to different set values includes:
And respectively carrying out read-write test on the register in the chip to be verified according to different set values, carrying out read-write operation on the register in the chip to be verified bit by bit, and carrying out automatic verification based on the read-back value and the written value. The method has the advantages that the registers in the chip to be verified are subjected to read-write test by utilizing different set values, then the registers in the chip to be verified are subjected to read-write operation bit by bit, whether verification passes or not is judged based on the read-back value and the written-in value, full verification of the registers of the chip is achieved, and accuracy of register mapping problem detection is improved.
Optionally, processing the data in the set format includes:
And editing the format of the parameter information to obtain data with a set format. The method has the advantages that the data processing efficiency can be improved by editing the parameter information into the data in the set format, so that the verification efficiency is improved.
Optionally, the script is a Python script and/or the verification environment is a UVM verification environment;
And/or the formatted data comprises a module name, a register address, a register name, a location of each field in the register, a register domain name, a register type, a register initial value, a bit width, and a register description. The method has the advantages that the Python script is adopted, the compatibility is strong, the automatic verification is convenient, the verification efficiency can be ensured, the accuracy of detecting the register mapping problem can be improved, bug carry-over is reduced, and the chip quality is improved by adopting data in a specific format to cooperate with a corresponding verification process.
Optionally, the register-related files include a module register model, a module register rtl file, a module register header file, a register test case, and a register description document.
Optionally, integrating the register-related file into the verification environment by the script includes:
Integrating the module register model and the register test case in a verification environment through the script, and integrating rtl files and header files of the module in rtl codes of a chip to be tested. And integrating the module register model and the register test case in the verification environment by utilizing the script, and integrating the rtl file and the header file of the module in rtl codes of the chip to be tested, so that the verification efficiency and the reusability can be ensured.
Optionally, before generating the register related file containing different setting values, the method further includes:
Judging whether the data with the set format has a register definition error or not through the script, and if so, processing the parameter information again to obtain the data with the new set format. The method has the advantages that whether the register definition errors exist in the data in the set format is judged by utilizing the script before the register related files containing different set values are generated, the accuracy of the generated register related files is ensured, and the verification accuracy is improved.
In a second aspect, the invention provides a device for verifying a chip register, the device comprising means/units for performing the method of any one of the possible designs of the first aspect described above. These modules/units may be implemented by hardware, or may be implemented by hardware executing corresponding software.
In a third aspect, the invention provides an electronic device comprising a memory and a processor, the memory having stored thereon a program executable on the processor, which when executed by the processor causes the electronic device to implement a method of performing any one of the possible designs of any of the above aspects.
In a fourth aspect, the present invention provides a readable storage medium having stored therein a program which, when executed, implements a method of any one of the possible designs of the above aspect.
The advantageous effects concerning the above second to fourth aspects can be seen from the description of the above first aspect.
Drawings
FIG. 1 is a schematic flow chart of a method for verifying a chip register according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a verification device for a chip register according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of data with a set format according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a simulation waveform of a register test according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
Aiming at the inconvenience of the current digital chip verification, the verification method of the chip register provided by the invention can improve the high efficiency and reusability of verification and the accuracy of register mapping problem detection. The technical solutions in the embodiments of the present invention are described below with reference to the accompanying drawings in the embodiments of the present invention. In the description of embodiments of the invention, the terminology used in the embodiments below is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions "a", "an", "the" and "the" are intended to include, for example, also "one or more" such expressions, unless the context clearly indicates to the contrary. It should also be understood that in the following embodiments of the present invention, "at least one", "one or more" means one or more than two (including two). The term "and/or" is used to describe an associative relationship of associative objects, and indicates that three relationships may exist, for example, a and/or B may indicate that a exists alone, while a and B exist together, and B exists alone, where A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.
Reference in the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the invention. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment, but mean "one or more, but not all, embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise. The term "coupled" includes both direct and indirect connections, unless stated otherwise. The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
In embodiments of the invention, "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of "exemplary" or "e.g." is intended to present related concepts in a concrete manner.
As shown in fig. 1, the present invention provides a method for verifying a chip register, including:
S101, acquiring parameter information of a register in a chip to be verified and processing the parameter information to obtain data in a set format.
In some embodiments, in order to improve the data processing efficiency and the verification efficiency, processing the data with the set format includes performing format editing on the parameter information to obtain the data with the set format. For example, data in excel format may be employed.
In some embodiments, in order to improve accuracy of detecting the register mapping problem while ensuring verification efficiency, reduce bug carryover, improve chip quality, data in a specific format is set in association with a corresponding verification process, as shown in fig. 4, where the data in the specific format includes a module name (module), a register address (addr), a register name (reg_name), a location (bit) of each domain in a register, a register domain name (field_name), a register type (type), a register initial value (InitVal (HEX)), a bit width (BitWidth), and a register Description (Description).
S102, generating a register related file containing different set values through a script based on the data in the set format.
In some embodiments, the script is a Python script, which has strong compatibility and is convenient for automatic verification.
In some embodiments, the register-related files include a module register model, a module register rtl file, a module register header file, a register test case, and a register description file, where the module register model is used for verifying environmental integration, the module register rtl file is used for program control of a chip register module, the module register header file is used for macro definition of the chip register module, the register test case is used for register verification, and the register description file is used for chip spec description. The register description document preferably employs a PDF document.
In some embodiments, in order to ensure the accuracy of the generated register-related file, the method further comprises judging whether the register definition errors exist in the data in the set format through a script before generating the register-related file containing different set values, and if yes, processing the parameter information again to obtain the data in the new set format.
And S103, integrating the register related file into a verification environment through the script so as to automatically verify the register in the chip to be verified according to different set values.
In some embodiments, the authentication environment is a UVM authentication environment.
In some embodiments, to ensure the efficiency and reusability of verification, integrating the register-related files into the verification environment by the script includes integrating the module register model and register test cases in the verification environment by the script, and integrating rtl files and header files of the module in rtl codes of the chip under test.
In some embodiments, in order to fully verify a chip register and improve the accuracy of detecting a register mapping problem, performing automatic verification on the register in the chip to be verified according to different set values includes performing read-write tests on the register in the chip to be verified according to different set values, performing read-write operations on the register in the chip to be verified bit by bit, and performing automatic verification based on a read-back value and a written value. For example, the different set values may include 0 and 1, and the registers in the chip to be verified are subjected to all-0 read-write test and all-1 read-write test by using 0 and 1, and finally the registers in the chip to be verified are subjected to read-write operation bit by bit, and are automatically verified based on the read-back value and the written-in value, for example, errors are reported when the read-back register value is inconsistent with the written-in value, so that the full verification of the chip registers is realized. In some embodiments, before performing all-0 read-write test and all-1 read-write test on registers in the chip to be verified, the default values of each register may be checked to ensure that the register model is consistent with the register default values of rtl. It should be understood that the set values may be 0 and 1, and a plurality of other values may be selected according to actual needs.
In the prior art, a chip verifier usually adopts a scheme that a register ralf file is used by a VCS-carried ralgen command, however, parameter information of a general register of a digital chip is in an excel table form, so that data in the excel table form is required to be converted into a ralf file, and then the ralf file is utilized to generate the register model, and the process is complex.
In order to facilitate understanding, the specific implementation process of the method is further described in this embodiment in combination with a specific application scenario system, and to solve the above problems in the current chip verification, that is, the problem that the digital chip register cannot quickly generate a model and fully verify, in order to more efficiently verify the register, in the method of the present invention, starting with an excel description document containing parameter information of the register in the chip register, a Python script is used to extract form data in a set format, and using the Python script can conveniently, quickly and accurately generate a module register model and a register test case for configuring and testing the chip register, where the method is easy to maintain and iterate, as shown in fig. 4-5, and detailed steps are described as follows:
Step a, obtaining parameter information of a register in a chip to be verified, and performing format editing on the parameter information to obtain excel format data as shown in fig. 4, wherein main information contained in a table includes a module name (module), a register address (addr), a register name (reg_name), positions (bits) of all domains in the register, a register domain name (field_name), a register type (type), a register initial value (InitVal (HEX)), a bit width (BitWidth), a register Description (Description) and the like.
Step b, after editing the required register table information according to fig. 4, the table can be processed by using Python script to generate a series of required files, mainly including:
(1) The module register model is used for verifying environment integration;
(2) A module register rtl file for program control of the chip register module;
(3) The module register header file is used for macro definition of the chip register module;
(4) The register test case is used for register verification;
(5) The register describes a PDF document for chip spec description.
And c, integrating the register model and the test case generated in the last step in the NVM verification environment, and integrating a register rtl file and a header file of the module in the chip rtl code.
Step d, running the generated register test case, wherein the simulation waveform is shown in fig. 5, the case firstly checks the default value of each register to ensure that the register model is consistent with the default value of rtl, then performing all-0 and all-1 read-write tests on each register, finally performing the read-write test on each register bit by bit, and reporting errors if the read-back register value is inconsistent with the written-in register value, thereby realizing the full verification of the chip registers.
The embodiment of the invention has the advantages that the method for generating the UVM register model and verifying the register can automatically process by using the Python script only by defining the register according to the format of a given excel table, thereby realizing high efficiency and reusability of verification, firstly checking the default value of each register, ensuring that the default values of the register model and rtl are consistent, then performing all-0 and all-1 read-write tests on each register, finally performing bit-by-bit read-write tests on each register, and improving the accuracy of detecting the register mapping problem. In the verification process, if the chip register is modified, the quick iteration of the register model can be realized through the script, and the method is also suitable for the register verification of the chip comprising a plurality of sub-modules, and can be widely applied to chip-level chip verification.
As shown in fig. 2, based on the above-mentioned verification method of a chip register, the present invention provides a verification device of a chip register, which includes an acquisition unit 201 configured to acquire parameter information of a register in a chip to be verified and process data in a set format, a processing unit 202 configured to generate a register-related file containing different set values through a script based on the data in the set format, and a test unit 203 configured to integrate the register-related file into a verification environment through the script, so as to automatically verify the register in the chip to be verified according to the different set values by using the script. The verification device includes an acquisition unit 201, configured to acquire parameter information of a register in a chip to be verified, and perform format editing on the parameter information to obtain data in a set format (such as an excel format), where the table data includes a module name, a register address, a register name, a location of each domain in the register, a register domain name, a register type, a register initial value, a bit width, and a register description; a processing unit 202 for generating a register related file containing different set values through a Python script based on the data of the set format, the register related file including a module register model for verifying environment integration, a module register rtl file for program control of a chip register module, a module register header file for macro definition of the chip register module, a register test case for register verification, and a register description file for chip spec description, a test unit 203 for integrating the module register model and the register test case in a UVM verification environment through the Python script, and integrating rtl files and header files of the module in rtl codes of a chip to be verified to perform read and write tests according to different set values, and performing read and write operations of the register in the chip to be verified on a bit-by-bit basis, and performing automatic verification based on the read-back value and the written value, converting the set data into the register related file by using the Python script, not only improving verification efficiency but also being able to sufficiently verify the register of the chip with the different set values, the accuracy of detecting the register mapping problem is improved.
It should be understood that all relevant contents of each step involved in the above method embodiments may be cited to the functional descriptions of the corresponding functional modules, and are not repeated herein. In addition, the use of suffixes such as "module", "component" or "unit" for representing elements is only for facilitating the description of the present invention, and is not of particular significance itself. Thus, "module," "component," or "unit" may be used in combination. The terminal may be implemented in various forms. For example, the terminals described in the present invention may include mobile terminals such as a mobile phone, a tablet computer, a notebook computer, a palm computer, a Personal digital assistant (Personal DIGITAL ASSISTANT, PDA), a Portable media player (Portable MEDIA PLAYER, PMP), a navigation device, a wearable device, a smart bracelet, a pedometer, and the like, as well as fixed terminals such as a digital TV, a desktop computer, and the like. The following description will be given taking a mobile terminal as an example, and those skilled in the art will understand that the configuration according to the embodiment of the present invention can be applied to a fixed type terminal in addition to elements particularly used for a moving purpose.
In other embodiments of the invention, an electronic device 300 is disclosed, as shown in FIG. 3, that may include one or more processors 301, memory 302, display 303, one or more application programs (not shown), and one or more computer programs 304, the devices being connectable through one or more communication buses 305. Wherein the one or more computer programs 304 are stored in the memory 302 and configured to be executed by the one or more processors 301, the one or more computer programs 304 comprise instructions that may be used to perform the various steps as in the corresponding embodiment of fig. 1.
The processor 301 may be a central processing unit (CentralProcessingUnit, CPU), but may also be other general purpose processors, digital signal processors (DigitalSignalProcessor, DSP), application specific integrated circuits (Application SpecificIntegratedCircuit, ASIC), field programmable gate arrays (Field-ProgrammableGateArray, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 302 may be an internal storage unit of the electronic device 300, such as a hard disk or a memory of the electronic device 300. The memory 302 may also be an external storage device of the electronic device 300, such as a plug-in hard disk provided on the electronic device 300, a smart memory card (SMARTMEDIACARD, SMC), a secure digital (SecureDigital, SD) card, a flash memory card (FLASHCARD), or the like. Further, the memory 302 may also include both internal storage units and external storage devices of the electronic device 300. The memory 302 is used to store computer programs and other programs and data required by the electronic device. The memory 302 may also be used to temporarily store data that has been output or is to be output.
The computer program 304 may be partitioned into one or more modules/units, which may be a series of computer program instruction segments capable of performing particular functions for describing the execution of the computer program 304 in the electronic device 300.
In addition to the foregoing structures, those skilled in the art will appreciate that FIG. 3 is merely an example of an electronic device 300 and is not intended to limit the electronic device 300, and that the electronic device 300 may include more or less components than illustrated, or may combine certain components, or different components, e.g., an electronic device may also include input and output devices, network access devices, buses, etc.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present invention. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
Based on the above embodiments, the present invention also discloses a computer readable storage medium having stored thereon at least one computer program which, when executed by a processor, implements the method for verifying a chip register in the above embodiments.
Those of ordinary skill in the art will appreciate that all or part of the steps in a method implementing the above embodiments may be performed by a program to instruct a processor, where the program may be stored on a computer readable storage medium, such as a non-transitory (non-transitory) medium, for example, random access memory, read only memory, flash memory, hard disk, solid state disk, magnetic tape (MAGNETIC TAPE), floppy disk (floppydisk), optical disk (opticaldisc), and any combination thereof. The storage media may be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Drive (SSD)), or the like.
The descriptions of the processes or structures corresponding to the drawings have emphasis, and the descriptions of other processes or structures may be referred to for the parts of a certain process or structure that are not described in detail.
In summary, the method, the device, the equipment and the medium for verifying the chip register disclosed by the invention convert the data with the set format into the register related file by utilizing the script, so that the verification efficiency is improved, the reusability of the verification is also improved, the register in the chip to be verified is firstly subjected to read-write test by utilizing different set values, then the register in the chip to be verified is subjected to read-write operation bit by bit, and whether the verification passes or not is judged based on the read-back value and the written value, the full verification of the chip register is realized, the accuracy of detecting the register mapping problem is improved, in addition, the Python script is adopted, the compatibility is strong, the automatic verification is facilitated, the accuracy of detecting the register mapping problem is improved by adopting the data with the specific format in cooperation with the corresponding verification process, the legacy is reduced, the chip quality is improved, the module register model and the register test case are integrated in the verification environment by utilizing the script, the rtl file and the head file of the module are integrated in the rtl code of the chip to be verified, the high efficiency of the verification and the accuracy of the register mapping problem can be ensured, and the accuracy of the register related file is ensured to be accurately judged before the register mapping problem is generated by utilizing the set value.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent changes made by the specification and drawings of the present invention, or direct or indirect application in the relevant art, are included in the scope of the present invention.
Claims (8)
1. A method for verifying a chip register, comprising:
Acquiring parameter information of a register in a chip to be verified and processing the parameter information to obtain data in a set format;
Generating a register related file containing different set values through a script based on the data in the set format;
integrating the related files of the register into a verification environment through the script so as to automatically verify the register in the chip to be verified according to different set values;
the register related files comprise a module register model, a module register rtl file, a module register header file, a register test case and a register description file;
integrating the register-related file into a verification environment by the script includes:
Integrating the module register model and the register test case in a verification environment through the script, and integrating rtl files and header files of the module in rtl codes of a chip to be tested.
2. The method of claim 1, wherein automatically verifying registers in the chip to be verified based on different settings comprises:
and respectively carrying out read-write test on the register in the chip to be verified according to different set values, carrying out read-write operation on the register in the chip to be verified bit by bit, and carrying out automatic verification based on the read-back value and the written value.
3. The method of claim 1, wherein processing the formatted data comprises:
And editing the format of the parameter information to obtain data with a set format.
4. The method of claim 1, wherein the script is a Python script and/or the verification environment is a UVM verification environment;
And/or the formatted data comprises a module name, a register address, a register name, a location of each field in the register, a register domain name, a register type, a register initial value, a bit width, and a register description.
5. The method of claim 1, further comprising, prior to generating the register-related file having different settings:
Judging whether the data with the set format has a register definition error or not through the script, and if so, processing the parameter information again to obtain the data with the new set format.
6. A verification device for a chip register, for use in the method of any one of claims 1 to 5, comprising:
The acquisition unit is used for acquiring parameter information of a register in the chip to be verified and processing the parameter information to obtain data in a set format;
The processing unit is used for generating a register related file containing different set values through a script based on the data in the set format;
the test unit is used for integrating the register related file into a verification environment through the script so as to automatically verify the register in the chip to be verified according to different set values by utilizing the script;
the register related files comprise a module register model, a module register rtl file, a module register header file, a register test case and a register description file;
integrating the register-related file into a verification environment by the script includes:
Integrating the module register model and the register test case in a verification environment through the script, and integrating rtl files and header files of the module in rtl codes of a chip to be tested.
7. An electronic device comprising a memory and a processor, the memory having stored thereon a program executable on the processor, which when executed by the processor, causes the electronic device to implement the method of any of claims 1 to 5.
8. A readable storage medium having a program stored therein, characterized in that the program, when executed, implements the method of any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411570872.1A CN119088631A (en) | 2024-11-06 | 2024-11-06 | A chip register verification method, device, equipment and medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411570872.1A CN119088631A (en) | 2024-11-06 | 2024-11-06 | A chip register verification method, device, equipment and medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN119088631A true CN119088631A (en) | 2024-12-06 |
Family
ID=93662337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411570872.1A Pending CN119088631A (en) | 2024-11-06 | 2024-11-06 | A chip register verification method, device, equipment and medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119088631A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119990059A (en) * | 2025-04-15 | 2025-05-13 | 沐曦集成电路(上海)股份有限公司 | Data extraction module verification method, electronic device and medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103838653A (en) * | 2012-11-27 | 2014-06-04 | 上海华虹集成电路有限责任公司 | Automatic register verification method based on VMM RAL |
| CN114912391A (en) * | 2022-05-11 | 2022-08-16 | 杭州云合智网技术有限公司 | Register design and verification model automatic generation method, apparatus, device and medium |
| CN117725881A (en) * | 2023-12-04 | 2024-03-19 | 紫光同芯微电子有限公司 | Method and device for generating register test case and test equipment |
| CN118446142A (en) * | 2024-05-10 | 2024-08-06 | 成都北中网芯科技有限公司 | Verification method, system, terminal and medium of readable and writable register |
-
2024
- 2024-11-06 CN CN202411570872.1A patent/CN119088631A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103838653A (en) * | 2012-11-27 | 2014-06-04 | 上海华虹集成电路有限责任公司 | Automatic register verification method based on VMM RAL |
| CN114912391A (en) * | 2022-05-11 | 2022-08-16 | 杭州云合智网技术有限公司 | Register design and verification model automatic generation method, apparatus, device and medium |
| CN117725881A (en) * | 2023-12-04 | 2024-03-19 | 紫光同芯微电子有限公司 | Method and device for generating register test case and test equipment |
| CN118446142A (en) * | 2024-05-10 | 2024-08-06 | 成都北中网芯科技有限公司 | Verification method, system, terminal and medium of readable and writable register |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119990059A (en) * | 2025-04-15 | 2025-05-13 | 沐曦集成电路(上海)股份有限公司 | Data extraction module verification method, electronic device and medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7707473B2 (en) | Integrated testing apparatus, systems, and methods | |
| US6353904B1 (en) | Method of automatically generating new test programs for mixed-signal integrated circuit based on reusable test-block templates according to user-provided driver file | |
| WO2016026328A1 (en) | Information processing method and device and computer storage medium | |
| CN112560372A (en) | Chip prototype verification method, device, equipment and medium | |
| CN119088631A (en) | A chip register verification method, device, equipment and medium | |
| CN117076337B (en) | Data transmission method and device, electronic equipment and readable storage medium | |
| CN117112447B (en) | Data transmission method and device, electronic equipment and readable storage medium | |
| CN115510804A (en) | Full-chip pin multiplexing automatic verification method, device, equipment and storage medium | |
| CN119476150A (en) | Method, device, equipment and medium for verifying chip functional coverage | |
| CN114818598B (en) | VCD vector compression method and device based on circuit overturning behavior | |
| WO2023202148A1 (en) | Register debugging platform and debugging method | |
| CN118133742B (en) | Bitstream testing method, device, computer equipment, storage medium and program product | |
| JP5551828B2 (en) | Replay architecture execution with probeless trace collection | |
| US7526691B1 (en) | System and method for using TAP controllers | |
| CN115563930A (en) | Automatic verification method and device based on storage model, terminal and storage medium | |
| CN116414762A (en) | PCIe link control method, control device, equipment and medium | |
| CN111639030A (en) | Page testing method, device, equipment and storage medium | |
| CN110704260A (en) | Reusable method for processor IO register test excitation | |
| CN118886379A (en) | A method, device, equipment and medium for simulating and verifying interface signals | |
| CN119003259A (en) | Digital-analog port inspection method, device, equipment and medium | |
| CN120260658B (en) | Memory testing method, device, equipment and medium | |
| CN113065302B (en) | Method for simulating logic system design, simulator and readable storage medium | |
| CN117976023A (en) | Memory capacity testing method, device, storage medium and electronic device | |
| CN110967613A (en) | Chip testing method, device, equipment and system | |
| CN120409373A (en) | Method, device, equipment and medium for verifying address allocation of system on chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20241206 |