CN119110119A

CN119110119A - HDCP receiver and display device

Info

Publication number: CN119110119A
Application number: CN202411209490.6A
Authority: CN
Inventors: 孙妙琴
Original assignee: Haining Yisiwei Computing Technology Co ltd; Beijing Eswin Computing Technology Co Ltd
Current assignee: Haining Yisiwei Computing Technology Co ltd; Beijing Eswin Computing Technology Co Ltd
Priority date: 2024-08-30
Filing date: 2024-08-30
Publication date: 2024-12-10

Abstract

The application discloses an HDCP receiver and display equipment. The algorithm circuit of the HDCP receiver can calculate the receiving end authentication key, and the interface circuit can enable the HDCP transmitter to read the receiving end authentication key so that the HDCP transmitter can authenticate the receiving end authentication key and send the encrypted video stream to the interface circuit after the authentication is passed. The data decryption circuitry in the HDCP receiver is capable of decrypting the video stream using a data decryption cipher. The data decryption password is calculated based on the receiving end authentication key. Because the algorithm circuit in the HDCP receiver can directly calculate the receiving end authentication key, the processor is not required to calculate the key, thereby effectively reducing the load of the processor.

Description

HDCP receiver and display device

Technical Field

The application relates to the technical field of electronics, in particular to an HDCP receiver and display equipment.

Background

The high-bandwidth digital content protection technology (HDCP) is a content protection system based on data encryption and authorization verification, which is widely used in high-definition multimedia interfaces (high-definition multimedia interface, HDMI). HDCP can solve the problem that digital video contents provided by a computer or other digital video content provider are copied and played out a plurality of times without degradation or degradation of source signal quality.

In order to realize the protection of video data, an interactive authentication key is required between the HDCP originating device and the HDCP receiving device to realize the device authentication. After the authentication is passed, the HDCP originating device may send a video stream to the HDCP receiving device.

The above-described scheme typically requires calculation of the authentication key by the processor, resulting in a high load on the processor.

Disclosure of Invention

The application provides an HDCP receiver and display equipment, which can solve the technical problem of high load of a processor caused by calculating an authentication key through the processor. The technical scheme is as follows:

in a first aspect, an HDCP receiver is provided for use in a display device, the HDCP receiver comprising an algorithm circuit, an interface circuit, and a data decryption circuit;

the algorithm circuit is used for calculating a receiving end authentication key;

The interface circuit is used for the HDCP transmitter to read the receiving end authentication key so that the HDCP transmitter authenticates the receiving end authentication key based on the transmitting end authentication key and sends a video stream to the interface circuit after the authentication is passed;

The data decryption circuit is used for calculating a data decryption password based on the receiving end authentication key and decrypting the video stream based on the data decryption password.

Optionally, the display device further comprises a processor;

The interface circuit is further configured to receive first key information sent by the processor, receive second key information sent by the HDCP transmitter, and be configured to enable the HDCP transmitter to read the first key information, so that the HDCP transmitter calculates the originating authentication key based on the first key information;

The algorithm circuit is used for calculating the first key information and the second key information by adopting an encryption algorithm to obtain the receiving end authentication key.

Optionally, the interface circuit includes a high performance expansion bus interface (advanced extensible interface, AXI) circuit, and an inter-INTEGRATED CIRCUIT, I2C) interface circuit;

The AXI circuit is used for being connected with the processor, and the I2C interface circuit is used for being connected with the HDCP transmitter.

Optionally, the HDCP receiver further includes an interrupt circuit;

the interrupt circuit is used for sending an interrupt request to the processor after the interface circuit interacts data with the HDCP transmitter;

The interface circuit is further used for receiving a first calculation instruction sent by the processor, wherein the first calculation instruction is sent by the processor based on the interrupt request;

The algorithm circuit is used for calculating the first key information and the second key information by adopting an encryption algorithm under the instruction of the first calculation instruction to obtain the receiving end authentication key.

Optionally, the HDCP receiver further comprises an instruction register, a key memory and a first channel register;

the instruction register is used for storing the first calculation instruction sent by the processor;

the key memory is used for storing the first key information sent by the processor;

the first channel register is configured to store the second key information and the receiving authentication key.

Optionally, the algorithm circuit comprises a first algorithm sub-circuit and a second algorithm sub-circuit, wherein different versions of the encryption algorithm are configured in the first algorithm sub-circuit and the second algorithm sub-circuit;

The HDCP receiver also comprises a multiplexer, a first channel register, a second channel register, a third channel register, a fourth channel register and a fifth channel register, wherein the multiplexer is respectively connected with the instruction register, the first algorithm sub-circuit and the second algorithm sub-circuit;

The instruction register is further used for storing a second calculation instruction sent by the processor through the interface circuit;

The multiplexer is configured to obtain the second key information stored in the first channel register according to the first calculation instruction, and to transmit the obtained second key information to the first algorithm sub-circuit or the second algorithm sub-circuit according to the second calculation instruction.

Optionally, the HDCP receiver further comprises a second channel register, wherein the multiplexer is further connected with the second channel register;

the instruction register is further used for storing a third calculation instruction sent by the processor through the interface circuit;

the second channel register is used for storing input parameters sent by the processor through the interface circuit;

The multiplexer is further configured to obtain the input parameter stored in the second channel register according to the third calculation instruction, and transmit the input parameter to the algorithm circuit;

The algorithm circuit is further configured to calculate the input parameter by using the encryption algorithm, and write a calculation result into the second channel register for the processor to read.

Optionally, the data decryption circuit comprises an HDCP codon circuit, a signal decoding sub-circuit and a decryption sub-circuit;

The HDCP codon circuit is used for calculating a data decryption password based on the receiving end authentication key;

the signal decoding sub-circuit is used for decoding the video stream;

And the decryption sub-circuit is used for decrypting the decoded video stream by adopting the data decryption password.

In a second aspect, there is provided a display device comprising a processor, and an HDCP receiver as described in the first aspect above;

The processor is used for sending first key information to the HDCP receiver, receiving an interrupt request sent by the HDCP receiver, and sending a first calculation instruction to the HDCP receiver according to the interrupt request, wherein the first calculation instruction is used for indicating the HDCP receiver to calculate a receiving end authentication key based on the first key information.

Optionally, the processor is further configured to send a second calculation instruction to the HDCP receiver, where the second calculation instruction is configured to instruct the HDCP receiver to calculate the receiving authentication key through a first algorithm sub-circuit or a second algorithm sub-circuit.

The technical scheme provided by the application has the beneficial effects that at least:

The application provides an HDCP receiver and a display device. The algorithm circuit of the HDCP receiver can calculate the receiving end authentication key, and the interface circuit can enable the HDCP transmitter to read the receiving end authentication key so that the HDCP transmitter can authenticate the receiving end authentication key and send the encrypted video stream to the interface circuit after the authentication is passed. The data decryption circuitry in the HDCP receiver is capable of decrypting the video stream using a data decryption cipher. The data decryption password is calculated based on the receiving end authentication key. Because the algorithm circuit in the HDCP receiver can directly calculate the receiving end authentication key, the processor is not required to calculate the key, thereby effectively reducing the load of the processor.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an HDCP receiver according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of another HDCP receiver according to an embodiment of the present application;

Fig. 3 is a schematic partial structure diagram of an HDCP receiver according to an embodiment of the present application;

fig. 4 is a schematic diagram of a data decryption circuit according to an embodiment of the present application;

FIG. 5 is a timing diagram of a code valid signal and a code received signal according to an embodiment of the present application;

FIG. 6 is a schematic diagram of TMDS period of a video frame according to an embodiment of the present application;

FIG. 7 is a flow chart of an initialization process provided by an embodiment of the present application;

fig. 8 is a schematic diagram of an authentication procedure of HDCP according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

The embodiment of the application provides an HDCP receiver, which can be applied to display equipment. The display device may be a television, a computer, a display, a projector, or the like. And, the HDCP receiver may be connected to an HDCP transmitter in the video stream transmission device. The video stream transmitting device may be a set-top box, a player, a computer, or the like. The video stream transmitting device and the display device can be connected through HDMI or digital video interface (digital visual interface, DVI). And, the video stream transmission device may transmit the video stream to the display device through HDMI or DVI.

Fig. 1 is a schematic structural diagram of an HDCP receiver according to an embodiment of the present application, and as shown in fig. 1, the HDCP receiver 01 includes an algorithm circuit 10, an interface circuit 20, and a data decryption circuit 30.

The algorithm circuit 10 is used for calculating a receiving end authentication key.

The interface circuit 20 is used for the HDCP transmitter 03 to read the receiving authentication key, so that the HDCP transmitter 03 authenticates the receiving authentication key based on the sending authentication key, and sends the video stream to the interface circuit 20 after the authentication is passed. It will be appreciated that if the HDCP transmitter 03 detects that the receiving authentication key is the same as the originating authentication key, it may be determined that the HDCP receiver 01 is authenticated.

A data decryption circuit 30 for calculating a data decryption password based on the receiving authentication key and decrypting the video stream transmitted by the HDCP transmitter 03 based on the data decryption password.

It can be understood that, after determining that the HDCP receiver 01 passes the authentication, the HDCP transmitter 03 may also calculate a data encryption password using the originating authentication key, encrypt the video stream to be transmitted based on the data encryption password, and transmit the encrypted video stream to the HDCP receiver 01. Based on the authentication mechanism between the HDCP transmitter 03 and the HDCP receiver 01, the data encryption password and the data decryption password can be ensured to be the same, so that the data decryption circuit 30 can be ensured to correctly recover the original video stream after decrypting the encrypted video stream by adopting the data decryption password.

Because the algorithm circuit of the HDCP receiver provided by the embodiment of the application can directly calculate the receiving end authentication key, the processor is not required to calculate the key, thereby effectively reducing the load of the processor.

Optionally, referring to fig. 1, a processor 02 may also be included in the display device.

The interface circuit 20 is connected to the processor 02 in the display device and to the HDCP transmitter 03, respectively. The interface circuit 20 is further configured to receive the first key information sent by the processor 02, receive the second key information and the video stream sent by the HDCP transmitter 03, and be configured to allow the HDCP transmitter 03 to read the first key information, so that the HDCP transmitter 03 calculates an originating authentication key based on the first key information. Wherein the first key information may be preconfigured in the display device and the second key information may be preconfigured in the video stream transmission device.

The algorithm circuit 10 is configured to calculate the first key information and the second key information by using an encryption algorithm, so as to obtain a receiving end authentication key.

The algorithm circuit 10 is preconfigured with an encryption algorithm, and the algorithm circuit 10 can calculate the first key information of the display device and the second key information of the video stream sending device by adopting the encryption algorithm to obtain a receiving end authentication key.

Optionally, with continued reference to fig. 1, hdcp receiver 01 may also include an interrupt circuit 40. The interrupt circuit 40 is configured to send an interrupt request (interrupt request, IRQ) to the processor 02 after the interface circuit 20 has interacted with the HDCP transmitter 03. Also, the interrupt circuit 40 may also send an interrupt request to the processor 02 after the arithmetic circuit 10 performs the calculation operation. That is, the interrupt circuit 40 may send an interrupt request to the processor 02 every time the interface circuit 20 receives data transmitted by the HDCP transmitter 03, every time the HDCP transmitter 03 reads data in the HDCP receiver 01 through the interface circuit 20, and every time the algorithm circuit 10 performs a calculation operation. Thus, it is ensured that the processor 02 accurately knows the authentication progress between the HDCP transmitter 03 and the HDCP receiver 01, and transmits a corresponding instruction.

The interface circuit 20 may also be used to receive a first calculation instruction sent by the processor 02. The algorithm circuit 10 may be configured to calculate the first key information and the second key information by using an encryption algorithm under the instruction of the first calculation instruction, so as to obtain the receiving authentication key.

Wherein, the first calculation instruction may be sent by the processor 02 based on the interrupt request. For example, the processor 02 may send the first calculation instruction to the HDCP receiver 01 after receiving an interrupt request indicating that the interface circuit 20 has received the second key information.

In the embodiment of the application, the interrupt circuit of the HDCP receiver can send an interrupt request to the processor after the interface circuit and the HDCP transmitter interact data each time and after the algorithm circuit executes calculation operation each time, so that the processor determines the authentication progress between the HDCP receiver and the HDCP transmitter and sends a corresponding instruction. Because the HDCP receiver can calculate the receiving end authentication key under the instruction of the processor, namely, the receiving end authentication key can be calculated through a hardware circuit, the processor is not required to calculate the receiving end authentication key, and the load of the processor is effectively reduced.

In addition, according to the scheme provided by the embodiment of the application, the HDCP receiver sends an interrupt to the processor in the authentication process, and performs hardware calculation under the instruction of the processor, so that the authentication flow of the HDCP is realized in a mode of combining software and hardware. In the mode of combining software and hardware, the HDCP receiver only needs to pay attention to hardware calculation, and does not need to consider switching among all processes in the authentication process, so that the complexity of hardware codes can be effectively reduced. In addition, the combination of the software and the hardware can improve the compatibility with different video stream sending devices, and the application flexibility is higher.

Optionally, fig. 2 is a schematic structural diagram of another HDCP receiver according to an embodiment of the present application. As shown in fig. 2, the interface circuit 20 may include an AXI circuit 201, and an I2C interface circuit 202.

The AXI circuit 201 is configured to be connected to the processor 02, and is configured to receive first key information and a first calculation instruction sent by the processor 02. The processor 02 may be a central processing unit (central processing unit, CPU). For example, the processor 02 may be a processor with a security attribute (e.g., a firewall) to ensure the reliability of the sending processor 02 sending the first key information to the AXI circuit 201.

The I2C interface circuit 202 is used to connect to the HDCP transmitter 03 and to interact data with the HDCP transmitter 03. The data may include key information and a video stream.

For example, an HDMI Receiving (RX) circuit may be included in a display device to which the HDCP receiver 01 belongs, and an HDMI Transmitting (TX) circuit may be included in a video stream transmitting device. The HDMI transmitting circuit includes an HDCP transmitter 03, the HDMI receiving circuit includes an HDCP receiver 01, the HDMI transmitting circuit and the HDMI receiving circuit are connected by HDMI, and the I2C interface circuit 202 may be a part of HDMI.

Fig. 3 is a schematic partial structure diagram of an HDCP receiver according to an embodiment of the present application. Optionally, referring to FIGS. 2 and 3, the HDCP receiver 01 may further include an instruction (CMD) register 50, a key memory 60, and a channel register set (CHANNEL REGISTER bank) 70. The channel register set 70 may include a plurality of channel registers, including at least a first channel register 701.

The instruction register 50 is used for storing a first calculation instruction sent by the processor 02. The process by which processor 02 sends instructions may also be understood as processor 02 writing instructions to instruction register 50 via interface circuit 20, such as AXI circuit 201. The instruction register 50, also known as an instruction decoder (CMD decoder), may be used to decode instructions sent by the processor 02.

A key memory 60 for storing the first key information transmitted by the processor 02. The key memory 60 may be a static random-access memory (SRAM).

A first channel register 701 for storing second key information and a recipient authentication key.

It will be appreciated that the interface circuit 20 of the HDCP receiver 01 may include a plurality of I2C interface circuits 202, and that different I2C interface circuits 202 may be connected to different HDCP transmitters 03. That is, the display device to which the HDCP receiver 01 belongs may have a plurality of HDMI interfaces, which may connect different video stream transmission devices. The channel register set 70 may include a plurality of first channel registers 701 corresponding to the plurality of I2C interface circuits 202 one by one, each first channel register 701 storing the second key information written by a corresponding one of the I2C interface circuits 202. The algorithm circuit 10 may be multiplexed by a plurality of first channel registers 701 for authentication with HDCP transmitters 03 in different video streaming devices.

Alternatively, as shown in FIGS. 2 and 3, the algorithm circuit 10 may include a first algorithm sub-circuit 101 and a second algorithm sub-circuit 102. The first algorithm sub-circuit 101 and the second algorithm sub-circuit 102 are configured with different versions of encryption algorithms. For example, the HDCP1.4 algorithm is configured in the first algorithm sub-circuit 101, and the HDCP2.3 algorithm is configured in the second algorithm sub-circuit 102. Referring to fig. 2, the HDCP1.4 algorithm may include km generation (gen) and ks generation algorithms, etc., which are keys required to be calculated in the authentication process. The HDCP2.3 algorithm may include an RSA-OAEP decryption algorithm, a secure hash algorithm (secure hash algorithm, SHA) 256 encryption algorithm, an HMAC-SHA256 encryption algorithm, and an advanced encryption standard (advanced encryption standard, AES) encryption algorithm, among others. Where OAEP refers to optimal asymmetric cryptographic padding (optimal asymmetric encryption padding), HMAC refers to a key-dependent hash operation message authentication code (hash-based message authentication code).

For a scenario where algorithm circuit 20 includes two algorithm sub-circuits, the HDCP receiver 01 may also include a multiplexer MUX, as shown in fig. 2 and 3. The control terminal of the multiplexer MUX may be connected to the instruction register 50, the first terminal of the multiplexer MUX being connected to the first channel register 701, and the second terminal of the multiplexer MUX being connected to the first algorithm sub-circuit 101 and the second algorithm sub-circuit 102, respectively.

The instruction register 50 is further configured to store a second calculation instruction sent by the processor 02 through the interface circuit 20 (for example, the AXI circuit 201). The multiplexer MUX may be configured to obtain the second key information from the first channel register 701 according to the first calculation instruction, and may be configured to transmit the obtained second key information to the first algorithm sub-circuit 101 or the second algorithm sub-circuit 102 according to the second calculation instruction. That is, the multiplexer MUX may transmit the second key information stored in the first channel register 701 to the first algorithm sub-circuit 101 or the second algorithm sub-circuit 102 under the direction of the second calculation instruction. Or it may be understood that the processor 02 can instruct the HDCP receiver 01 to process the first key information and the second key information using different versions of the encryption algorithm through the second calculation instruction to calculate the terminating authentication key.

Alternatively, the processor 02 may determine the version of the encryption algorithm that the HDCP receiver 01 needs to employ based on the interrupt sent by the HDCP transmitter 03, and send a corresponding second calculation instruction.

It will be appreciated that the content of the first key information and the second key information may be different according to the version of the encryption algorithm that the HDCP receiver 01 needs to employ. The first key information may be key information of the HDCP receiver 01 specified in the corresponding version of the encryption algorithm protocol, which includes key information for calculating the receiver authentication key, and key information for reading by the HDCP transmitter 03. The second key information may be key information of the HDCP transmitter 03 specified in the corresponding version of the encryption algorithm protocol, which contains key information for calculating an originating authentication key, and key information for transmitting to the HDCP receiver 01.

For example, if the encryption algorithm adopted by the HDCP transmitter 03 and the HDCP receiver 01 is the HDCP1.4 algorithm, the first key information and the second key information are the key information of the receiving end and the transmitting end specified in the HDCP1.4 algorithm protocol, respectively. If the adopted encryption algorithm is the HDCP2.3 algorithm, the first key information and the second key information are the key information of the receiving end and the transmitting end specified in the HDCP2.3 algorithm protocol respectively.

It will also be appreciated that the key store 60, instruction register 50 and channel register set 70 in HDCP receiver 01 have different base addresses.

Optionally, with continued reference to FIG. 3, the set of channel registers 70 in the HDCP receiver 01 may also include a second channel register 702. The first end of the multiplexer MUX may also be connected to the second channel register 702.

The instruction register 50 may also be used to store third calculation instructions that are sent by the processor 02 via the interface circuit 20. For example, processor 02 may send a third calculation instruction through AXI circuitry 201.

The second channel register 702 may be used to store input parameters that the processor 02 sends through the interface circuit 20.

The multiplexer MUX is further configured to obtain the input parameter stored in the second channel register 70 according to the third calculation instruction, and transmit the input parameter to the algorithm circuit 20.

Accordingly, the algorithm circuit 20 may be further configured to calculate the input parameters using an encryption algorithm, and write the calculation result to the second channel register 702 for the processor 02 to read.

By way of example, the second channel register 702 may be a1 kilobit (kb) spatial register that is used to allocate corresponding space for input parameters of an encryption algorithm. When applied, the processor 02 simply writes the input parameters of the encryption algorithm into the corresponding second channel register 702 and sends a third calculation instruction to instruct the algorithm circuit 20 to perform calculation. After the algorithm circuit 20 has completed its calculation, the calculation result may be written back again to the second channel register 702. The interrupt circuit 30 may send an interrupt request to the processor 02 after completion of calculation by the algorithm circuit 20, and the processor 02 may read the calculation result from the second channel register 702 based on the interrupt request.

It is understood that the input parameter may be other parameters that need to be processed through an encryption algorithm besides the key information, that is, the input parameter is a parameter unrelated to the HDCP authentication flow. That is, the encryption algorithm configured in the algorithm circuit 20 may be multiplexed by other processes as a general algorithm intellectual property (intellectual property, IP) algorithm, in addition to calculating an authentication key in the HDCP authentication process. Thereby, the code utilization of the encryption algorithm in the algorithm circuit 20 is effectively improved. And, the processor 02 can realize the call of the encryption algorithm in the algorithm circuit 20 by writing the input parameters and the third calculation instruction, the call process is simpler, the efficiency is higher, and the load of the processor 02 can be further reduced.

Alternatively, the RSA-OAEP algorithm, SHA256 algorithm, HMAC-SHA256 algorithm, and AES encryption algorithm configured in the second algorithm sub-circuit 102 described above may be multiplexed by other flows as a general algorithm. That is, the multiplexer MUX may send the input parameters stored in the second channel register 702 to the second algorithm subcircuit 102 in the algorithm circuit 20, under the direction of the third calculation instruction.

Fig. 4 is a schematic diagram of a data decryption circuit according to an embodiment of the present application. As shown in fig. 4, the data decryption circuit 30 may include an HDCP codon circuit 301, a signal decoding sub-circuit 302, and a decryption sub-circuit 303.

Wherein, HDCP-code sub-circuit 301 is configured to calculate a data decryption code based on the receiving authentication key. A signal decoding sub-circuit 302 for decoding the received video stream from HDCP transmitter 03. And the decryption sub-circuit 303 is configured to decrypt the decoded video stream by using the data decryption password calculated by the HDCP password sub-circuit 301.

The signal decoding sub-circuit 302 may be, for example, a transition minimized differential signaling TMDS decoding circuit. As shown in fig. 4, the HDCP transmitter 03 may include a data encryption circuit including an HDCP encryption circuit, a TMDS encoder, and an encryption circuit. The HDCP encryption circuit is also called an HDCP encryptor (cipher), and is configured to generate a data encryption password based on an originating authentication key, the encryption circuit is configured to encrypt a video stream to be transmitted by using the data encryption password, and the TMDS encoder is configured to encode the encrypted video stream by using a TMDS algorithm. Accordingly, the signal decoding sub-circuit 302 may decode the received video stream by using the TMDS algorithm, and then the decryption sub-circuit 303 decrypts the decoded video stream.

Referring to fig. 4, it can be seen that the encryption circuit may be an exclusive or (XOR) circuit, and the decryption sub-circuit 303 may also be an exclusive or circuit. The HDCP encryption circuit in the data encryption circuit may generate a 24-bit pseudo-random number (pseudo-random-data) as a data encryption password, and the encryption circuit may perform bitwise exclusive or (bitwise XOR) on 24-bit data in the video stream and the 24-bit data encryption password. The data decryption password generated by the HDCP codon 301 may also be a 24-bit pseudo-random number, and the decryption sub 303 may perform bitwise exclusive or on the 24-bit data in the decoded video stream and the 24-bit data decryption password, thereby recovering the original video stream.

Optionally, the HDCP codon circuit 301 is configured to periodically update a data decryption key based on the receiving authentication key, and is configured to output a password valid signal vld and a password receiving signal acpt. For example, the HDCP encryption sub-circuit 301 may update the data decryption password when the password reset (rekey) enable signal is at the second level. The cipher reset enable signal may be periodically at the second level, and the HDCP codon circuit 301 may periodically update the data decryption cipher under the control of the cipher reset enable signal.

In addition, in the process of updating the data decryption code by the HDCP codon circuit 301, the output code valid signal vld is at the first level, and after the data decryption code is updated, the output code valid signal vld is at the second level. The cipher received signal acpt is at a second level during a data island period (DATA ISLAND period) and a video data period (video data period) of the video stream, and the cipher received signal acpt is at a first level during a control period (control period) of the video stream. Referring to fig. 5, it can be seen that the second level of the code valid signal vld and the code received signal acpt may be high and the first level may be low.

The decryption sub-circuit 303 is further configured to obtain the data decryption password output by the HDCP-codon circuit 301 when the password valid signal vld and the password receiving signal acpt are both at the second level.

Based on the above timing design, it can be ensured that the data decryption password of each 24 bits generated by the HDCP codon circuit 301 corresponds to each 24bit data output by the signal decoding sub circuit 302, and thus the correct decryption of the video stream can be ensured.

It will be appreciated that the first level may also be referred to as an inactive level and the second level may also be referred to as an active level. The second level may be a high level with respect to the first level.

Fig. 6 is a schematic diagram of a TMDS period of a video frame according to an embodiment of the present application. As shown in fig. 6, each video frame may include a control period, a data island period, and a video data period. Also, the display process of each video frame may include a vertical blanking (horizontal blanking) phase, a horizontal blanking (vertical blanking) phase, and an active video (active video) phase. The vertical blanking stage and the horizontal blanking stage both comprise a plurality of data island periods and control periods which are arranged in a staggered manner, and the effective video stage comprises a plurality of video data periods. Since the video stream needs to be decrypted in both the data island period and the video data period, the video stream does not need to be decrypted in the control period, and thus the code receiving signal acpt is at the second level in both the data island period and the video data period, and is at the first level in the control period.

Further, it is understood that VSYNC shown in fig. 6 is a vertical synchronization signal, also called a frame synchronization signal, indicating the start of scanning one frame. HSYNC is a horizontal synchronization signal, also called a line synchronization signal, indicating the start of scanning a line (i.e., a pixel line).

Optionally, in an embodiment of the present application, the authentication procedure between the HDCP receiver 01 and the HDCP transmitter 03 may include an initialization phase and an authentication phase. In this initialization phase, as shown in fig. 7, the processor 02 may first perform operations of reset de-asserted and clock enable. Thereafter, the processor 02 may configure the first key information via the interface circuit 20 (e.g., AXI circuit 201) and select the encryption algorithm via the second calculation instructions. For example, the processor 02 may select the HDCP1.4 algorithm or the HDCP2.3 algorithm.

In this authentication phase, the HDCP receiver 01 and the HDCP transmitter 03 may calculate and interact authentication keys, respectively, to achieve authentication. Thereafter, in the data encryption stage, the HDCP receiver 01 and the HDCP transmitter 03 may calculate a data encryption password and a data decryption password for encrypting and decrypting the video stream, respectively, based on the calculated authentication key. The authentication procedure is described below taking the first authentication phase of the HDCP1.4 algorithm as an example.

As shown in fig. 8, the HDCP transmitter 03 (i.e., HDCP TX) may first read the configuration information Bcaps and Bstatus from the HDCP receiver 01 (i.e., HDCP RX) through the interface circuit 20 (e.g., I2C interface circuit 202). The HDCP transmitter 03 may then write second key information, which may include Ainfo, an and AKSV together 3 keys, to the HDCP receiver 01 via the I2C interface circuit 202. Wherein Ainfo is 1 byte in length, an is a pseudorandom code of 64 bits in length, AKSV is a key select vector (key selection vector, KSV) of HDCP transmitter 03 of 40 bits in length.

After the HDCP receiver 01 receives the second key information, the second key information may be updated to the channel register set 70, and each time one key in the second key information is updated, an interrupt request may be sent to the processor 02 (e.g. CPU) through the interrupt circuit 40. Since the second key information includes 3 keys, the interrupt circuit 40 issues 3 interrupt requests to the processor 02. After receiving the interrupt request 3 times, the processor 02 may send a first calculation instruction to the HDCP receiver 01, which may be written to the instruction register 50 of the HDCP receiver 01, for example.

With continued reference to fig. 8, after writing the second key information, the HDCP transmitter 03 may read the first key information from the HDCP receiver 01 through the interface circuit 20 (e.g., the I2C interface circuit 202). As described above, this first key information is written to the HDCP receiver 01 by the processor 02. And, the first key information may include BKSV and a device private key (DEVICE PRIVATE KEY). Where BKSV is the KSV of HDCP receiver 01, which is a 40bit binary number. The device private key is a collection of 40 56bit keys. In the embodiment of the present application, the HDCP transmitter 03 may read BKSV in the first key information and may also read a relay (repeater) bit in Bcaps. A relay bit, for example, the 6 th bit is a relay bit, which is used to characterize whether HDCP receiver 01 is an HDCP repeater, may be included in Bcaps. As shown in fig. 8, after detecting that the HDCP transmitter 03 reads the relay bit and the BKSV in the first key information, the HDCP receiver 01 may send an interrupt request to the processor 02 through the interrupt circuit 40, and the processor 02 may perform an clear interrupt (clear IRQ) operation.

It will be appreciated that after the interaction of the KSV between the HDCP receiver 01 and the HDCP transmitter 03, it is also necessary to verify a priori whether the KSV of the other party is valid, and if so, to continue with the subsequent steps.

After the HDCP receiver 01 receives the first calculation instruction sent by the processor 02, a receiver authentication key may be calculated based on the first key information and the second key information, where the receiver authentication key may include Ks ', M0', and R0'. For example, HDCP receiver 01 may first generate shared key Km' based on its own device private key (i.e., bkeys) and KSV (i.e., AKSV) of HDCP transmitter 03. And then generating the receiving end authentication keys Ks ', M0' and R0 'based on the shared key Km', the relay bit and the pseudo random code An. In the embodiment of the present application, the HDCP receiver 01 may send R0' in the receiver authentication key to the HDCP transmitter 03 for the HDCP transmitter 03 to authenticate.

Accordingly, HDCP transmitter 03 may also generate shared key Km based on its own device private key (i.e., akeys) and KSV (i.e., BKSV) of HDCP receiver 01. Then, the originating authentication keys Ks, M0, and R0 are generated based on the shared key Km, the relay bit, and the pseudorandom code An. After the HDCP transmitter 03 reads R0 'in the receiving authentication key of the HDCP receiver 01, it can verify whether R0' in the receiving authentication key is identical to R0 in the calculated transmitting authentication key. If R0' in the receiving authentication key is the same as R0 in the transmitting authentication key, the HDCP transmitter 03 may determine that the first authentication phase passes and may continue to perform the subsequent authentication phase.

For example, if HDCP receiver 01 is an HDCP repeater, HDCP transmitter 03 and HDCP receiver 01 may continue to perform the operations of the second authentication phase and the third authentication phase. If HDCP receiver 01 is not an HDCP repeater, HDCP transmitter 03 and HDCP receiver 01 may directly perform the operations of the third authentication phase. In the embodiment of the present application, the HDCP receiver 01 is not typically an HDCP repeater, and thus may directly perform the operation of the third authentication phase.

It will be appreciated that in the first authentication phase described above, as shown in fig. 8, after the HDCP receiver 01 calculates the receiving end authentication keys Ks ', M0' and R0', an interrupt request may be sent to the processor 02 through the interrupt circuit 40, and the processor 02 may perform an operation of clearing the interrupt. After detecting that the HDCP transmitter 03 reads R0' in the receiver authentication key, the HDCP receiver 01 may send an interrupt request to the processor 02 through the interrupt circuit 40, and the processor 02 may perform an operation of clearing the interrupt.

In the third authentication phase (also referred to as the content encryption phase) of the HDCP1.4 algorithm, the HDCP receiver 01 and the HDCP transmitter 03 may calculate new cipher initial values Ki and Mi based on the receiving authentication key calculated in the first authentication phase, and calculate the authentication key Ri, i as a frame number (frame number) of the video stream. Wherein the authentication key Ri may be used for link integrity checking and may be updated once every 128 frames. For example, the HDCP transmitter 03 may periodically read (e.g., read every 2 seconds) the authentication key Ri calculated by the HDCP receiver 01, and verify whether the authentication key Ri read by it is identical to the authentication key Ri calculated by itself. If the two are consistent, the verification can be determined to pass.

In this third authentication phase, the HDCP transmitter 03 may also calculate a 24-bit data encryption password based on Ks in the originating authentication key, the pseudorandom code An, and the password initial values Ki and Mi. Correspondingly, the HDCP receiver 01 may also calculate a 24-bit data decryption password based on Ks' in the receiver authentication key, the pseudorandom code An, and the password initial values Ki and Mi. It will be appreciated that the third authentication phase described above may be performed by the codon circuit 301, which codon circuit 301 is also referred to as an HDCP encryptor (cipher).

For example, referring to fig. 5, the codon circuit 301 may be initialized based on the initialization signal init, for example, after detecting a pulse of the initialization signal init. And, the authentication key Ri may be updated based on the first calculation signal vb_calc, and the data decryption password may be updated based on the second calculation signal hb_calc. For example, the authentication key Ri may be updated after the pulse of the first calculation signal vb_calc is detected, and the data decryption password may be recalculated after the pulse of the second calculation signal hb_calc is detected. In the timing shown in fig. 5, the second level (i.e., the active level) is high. As can be seen from fig. 5, the level of the cryptographically valid signal vld can be pulled low by the codon circuit 301 during the calculation of the data decryption password. After updating the authentication key Ri, the cryptographic sub-circuit 301 may output a Ri update signal ri_upd pulse.

Alternatively, the first calculation signal vb_calc may be generated based on the vertical synchronization signal VSYNC. The second calculation signal hb_calc may be generated based on a password reset (rekey) enable signal, e.g., the second calculation signal hb_calc may be a rekey enable signal. The rekey enable signal is active during the horizontal blanking period.

Alternatively, the HDCP receiver 01 provided in the embodiment of the present application may be implemented using a System On Chip (SOC).

In summary, the embodiments of the present application provide an HDCP receiver, where an interface circuit of the HDCP receiver is capable of receiving first key information and a first calculation instruction sent by a processor, and receiving second key information sent by an HDCP transmitter. The algorithm circuit of the HDCP receiver can calculate the first key information and the second key information by adopting an encryption algorithm based on the first calculation instruction to obtain a receiving end authentication key for authentication of the HDCP transmitter. The interrupt circuit of the HDCP receiver can send an interrupt request to the processor after the interface circuit and the HDCP transmitter interact data each time and after the algorithm circuit executes calculation operation, so that the processor determines the authentication progress between the HDCP receiver and the HDCP transmitter and sends a corresponding instruction. Because the HDCP receiver can calculate the receiving end authentication key under the instruction of the processor, namely, the receiving end authentication key can be calculated through a hardware circuit, the processor is not required to calculate the receiving end authentication key, and the load of the processor is effectively reduced.

Fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present application. As shown in fig. 9, the display device includes a processor 02, and an HDCP receiver 01 as provided in the above-described embodiment.

The processor 02 is configured to send the first key information to the HDCP receiver 01, receive an interrupt request sent by the HDCP receiver 01, and send a first calculation instruction to the HDCP receiver 01 based on the interrupt request. The first calculation instruction is used for instructing the HDCP receiver 01 to calculate a receiving end authentication key based on the first key information.

Alternatively, the processor 02 may be a CPU, for example, a CPU having a security attribute (such as a firewall). The first key information may include BKSV of the display device and a device private key of the display device.

Optionally, the processor 02 may be further configured to send a second calculation instruction to the HDCP receiver 01. The second calculation instruction is used for instructing the HDCP receiver 01 to calculate the receiving end authentication key through the first algorithm sub-circuit or the second algorithm sub-circuit.

Optionally, the processor 02 may be further configured to send the input parameter and the third calculation instruction to the HDCP receiver 01, and obtain a calculation result obtained by encrypting and calculating the input parameter by the HDCP receiver 01.

The third calculation instruction is used for indicating a calculation result obtained by calculating the input parameter by the HDCP receiver 01 through an encryption algorithm. After the HDCP receiver 01 calculates the calculation result, an interrupt request may be sent to the processor 02, and the processor 02 may read the calculation result from the HDCP receiver 01 based on the terminal request.

It will be appreciated that the input parameters may be parameters unrelated to the authentication flow of HDCP, i.e. the processor 02 may instruct the HDCP receiver 01 to perform encryption computation on parameters in other flows by using an encryption algorithm, so as to implement multiplexing of the encryption algorithm in the HDCP receiver 01. Thereby, the code utilization rate of the encryption algorithm in the HDCP receiver 01 is effectively improved.

Based on the above analysis, the first calculation instruction sent by the processor 02 is an instruction for instructing the HDCP receiver 01 to calculate the receiver authentication key. The second calculation instruction sent by the processor 02 is an instruction for selecting a version of the encryption algorithm, that is, the second calculation instruction is used to instruct the HDCP receiver 01 to calculate the receiver authentication key using the first algorithm sub-circuit or the second algorithm sub-circuit. The third calculation instruction sent by the processor 02 is an instruction for instructing the HDCP receiver 01 to perform encryption calculation on the input parameter using the encryption algorithm, that is, the third calculation instruction is an instruction for multiplexing the encryption algorithm in the HDCP receiver 01.

The terms "first," "second," and the like in this disclosure are used for distinguishing between similar elements or items having substantially the same function and function, and it should be understood that there is no logical or chronological dependency between the terms "first," "second," and "n," and that there is no limitation on the amount and order of execution.

The foregoing description of the exemplary embodiments of the application is not intended to limit the application to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the application.

Claims

1. An HDCP receiver, characterized in that it is applied to a display device; the HDCP receiver comprises: an algorithm circuit, an interface circuit and a data decryption circuit;

The algorithm circuit is used to calculate the receiving end authentication key;

The interface circuit is used for the HDCP transmitter to read the receiving end authentication key, so that the HDCP transmitter authenticates the receiving end authentication key based on the transmitting end authentication key, and sends the video stream to the interface circuit after the authentication is passed;

The data decryption circuit is used to calculate a data decryption password based on the receiving end authentication key, and decrypt the video stream based on the data decryption password.

2. The HDCP receiver according to claim 1, wherein the display device further comprises a processor;

The interface circuit is further used to receive the first key information sent by the processor, receive the second key information sent by the HDCP transmitter, and be used for the HDCP transmitter to read the first key information so that the HDCP transmitter calculates the transmitting end authentication key based on the first key information;

The algorithm circuit is used to calculate the first key information and the second key information using an encryption algorithm to obtain the receiving end authentication key.

3. The HDCP receiver according to claim 2, wherein the interface circuit comprises: a high-performance expansion bus interface AXI circuit, and an internal integrated circuit I2C interface circuit;

The AXI circuit is used to connect to the processor, and the I2C interface circuit is used to connect to the HDCP transmitter.

4. The HDCP receiver according to claim 2, characterized in that the HDCP receiver further comprises: an interrupt circuit;

The interrupt circuit is used to send an interrupt request to the processor after the interface circuit interacts with the HDCP transmitter;

The interface circuit is further configured to receive a first calculation instruction sent by the processor, where the first calculation instruction is sent by the processor based on the interrupt request;

The algorithm circuit is used to calculate the first key information and the second key information using an encryption algorithm under the instruction of the first calculation instruction to obtain the receiving end authentication key.

5. The HDCP receiver according to claim 4, characterized in that the HDCP receiver further comprises: an instruction register, a key memory and a first channel register;

The instruction register is used to store the first computing instruction sent by the processor;

The key storage device is used to store the first key information sent by the processor;

The first channel register is used to store the second key information and the receiving end authentication key.

6. The HDCP receiver according to claim 5, characterized in that the algorithm circuit comprises: a first algorithm sub-circuit and a second algorithm sub-circuit, wherein the first algorithm sub-circuit and the second algorithm sub-circuit are configured with different versions of the encryption algorithm;

The HDCP receiver further includes: a multiplexer, the multiplexer being connected to the instruction register, the first channel register, the first algorithm subcircuit and the second algorithm subcircuit respectively;

The instruction register is further used to store a second computing instruction sent by the processor through the interface circuit;

The multiplexer is used to obtain the second secret key information stored in the first channel register according to the first calculation instruction, and is used to transmit the obtained second secret key information to the first algorithm sub-circuit or the second algorithm sub-circuit according to the second calculation instruction.

7. The HDCP receiver according to claim 6, characterized in that the HDCP receiver further comprises: a second channel register, the multiplexer is also connected to the second channel register;

The instruction register is further used to store a third computing instruction sent by the processor through the interface circuit;

The second channel register is used to store input parameters sent by the processor through the interface circuit;

The algorithm circuit is further used to calculate the input parameters using the encryption algorithm and write the calculation results into the second channel register for reading by the processor.

8. The HDCP receiver according to any one of claims 1 to 7, characterized in that the data decryption circuit comprises: an HDCP cipher subcircuit, a signal decoding subcircuit and a decryption subcircuit;

The HDCP cryptographic subcircuit is used to calculate a data decryption cryptogram based on the receiving end authentication key;

The signal decoding subcircuit is used to decode the video stream;

The decryption subcircuit is used to decrypt the decoded video stream using the data decryption password.

9. A display device, characterized in that the display device comprises: a processor, and an HDCP receiver according to any one of claims 1 to 8;

The processor is configured to send first key information to the HDCP receiver, receive an interrupt request sent by the HDCP receiver, and send a first calculation instruction to the HDCP receiver according to the interrupt request;

The first calculation instruction is used to instruct the HDCP receiver to calculate a receiving end authentication key based on the first key information.

10. The display device according to claim 9 is characterized in that the processor is also used to send a second calculation instruction to the HDCP receiver, and the second calculation instruction is used to instruct the HDCP receiver to calculate the receiving end authentication key through the first algorithm subcircuit or the second algorithm subcircuit.