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CN119127751A - DMA controllers, chips, root complexes, and endpoint devices - Google Patents

DMA controllers, chips, root complexes, and endpoint devices Download PDF

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Publication number
CN119127751A
CN119127751A CN202310699192.9A CN202310699192A CN119127751A CN 119127751 A CN119127751 A CN 119127751A CN 202310699192 A CN202310699192 A CN 202310699192A CN 119127751 A CN119127751 A CN 119127751A
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China
Prior art keywords
information
memory
description character
data
dma controller
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CN202310699192.9A
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Chinese (zh)
Inventor
陈坤晗
蒋辉
李磊
王凡
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Lianyun Technology Hangzhou Co ltd
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Lianyun Technology Hangzhou Co ltd
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Priority to CN202310699192.9A priority Critical patent/CN119127751A/en
Publication of CN119127751A publication Critical patent/CN119127751A/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)

Abstract

本申请公开了一种DMA控制器、芯片、根复合体及端点设备，属于通信领域。本申请提供的DMA控制器应用于RC或者EP，DMA控制器包括：获取模块和控制模块；获取模块用于获取来自目标处理器的DMA控制信息，DMA控制信息包括目标存储器的信息，目标存储器的信息用于指示描述字符链表的存放位置；获取模块还用于根据DMA控制信息确定目标存储器，并从目标存储器中获取描述字符链表中的描述字符信息，目标存储器包括RC存储器或者EP存储器；控制模块用于根据描述字符链表中的描述字符信息，在RC存储器与EP存储器之间进行数据传输。本申请的DMA控制器既能够用于RC，也能够用于EP，具有复用性，解决相关技术中DMA控制器的应用场景单一的问题。

The present application discloses a DMA controller, a chip, a root complex and an endpoint device, which belong to the field of communications. The DMA controller provided by the present application is applied to RC or EP, and the DMA controller includes: an acquisition module and a control module; the acquisition module is used to obtain DMA control information from the target processor, and the DMA control information includes information of the target memory, and the information of the target memory is used to indicate the storage location of the description character list; the acquisition module is also used to determine the target memory according to the DMA control information, and obtain the description character information in the description character list from the target memory, and the target memory includes an RC memory or an EP memory; the control module is used to perform data transmission between the RC memory and the EP memory according to the description character information in the description character list. The DMA controller of the present application can be used for both RC and EP, and has reusability, which solves the problem of single application scenario of the DMA controller in the related art.

Description

DMA controller, chip, root complex and endpoint device
Technical Field
The application belongs to the field of communication, and particularly relates to a DMA controller, a chip, a root complex and endpoint equipment.
Background
In the field of communications, communication devices such as 5G, 4G, and the like each support an RC (Root Complex) mode and an EP (End Point, end Point device) mode (slave mode) of a PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, high-speed serial computer expansion bus standard) high-speed interface. In the RC mode, the communication device can be used as a master device to externally connect with the extension device, and in the EP mode, the communication device can be used as a slave device to be connected to the upper computer.
In the related art, in the RC mode, the communication device may be used as a master device to transmit data by using a DMA (Direct Memory Access ) controller, so as to improve the data transmission rate between the communication device and the external expansion device. Or in the EP mode, the communication device may be used as a slave device to transmit data by using another DMA controller, so as to increase the data transmission rate between the communication device and the host computer.
However, since the existing DMA controller cannot be used in a communication device supporting multiple modes (for example, supporting both RC mode and EP mode), there is a problem in the related art that the DMA controller has a single application scenario.
Disclosure of Invention
The embodiment of the application provides a DMA controller, a chip, a root complex and endpoint equipment, which can solve the problem of single application scene of the DMA controller in the related technology.
In a first aspect, an embodiment of the present application provides a DMA controller, where the DMA controller is applied to a root complex RC or an endpoint device EP, and the DMA controller includes an acquisition module and a control module;
the acquisition module is used for acquiring DMA control information from a target processor, wherein the DMA control information comprises information of a target memory, and the information of the target memory is used for indicating the storage position of a description character linked list;
The acquisition module is also used for determining a target memory according to the DMA control information and acquiring description character information in a description character linked list from the target memory, wherein the target memory comprises an RC memory or an EP memory;
and the control module is used for carrying out data transmission between the RC memory and the EP memory according to the description character information in the description character linked list.
In a second aspect, an embodiment of the present application provides a chip, including a processor, a memory, and a DMA controller according to the first aspect, where the processor is connected to the memory and the DMA controller, and the memory is connected to the DMA controller.
In a third aspect, an embodiment of the present application provides a root complex, including an RC processor, an RC memory, a DMA controller according to the first aspect, and a first PCIe controller;
The RC processor is respectively connected with the RC memory and the DMA controller, the RC memory is connected with the DMA controller, and the DMA controller is connected with the first PCIe controller.
In a fourth aspect, an embodiment of the present application provides an endpoint device, including an EP processor, an EP memory, a DMA controller according to the first aspect, and a second PCIe controller;
The EP processor is respectively connected with the EP memory and the DMA controller, the EP memory is connected with the DMA controller, and the DMA controller is connected with the second PCIe controller.
The DMA controller comprises an acquisition module and a control module, wherein the acquisition module is used for acquiring DMA control information from a target processor, the DMA control information comprises information of a target memory, the information of the target memory is used for indicating the storage position of a description character linked list, the acquisition module is also used for determining the target memory according to the DMA control information and acquiring the description character information in the description character linked list from the target memory, the target memory comprises an RC memory or an EP memory, and the control module is used for carrying out data transmission between the RC memory and the EP memory according to the description character information in the description character linked list. Therefore, the DMA controller can determine the storage position of the description character linked list according to the DMA control information from the target processor, and further the DMA controller can acquire the description character information by accessing the local memory or the opposite-end memory according to the storage position of the description character linked list, so that the direction of the DMA controller for reading the description character information can be switched, the DMA controller can be used for RC and EP, and the problem of single application scene of the DMA controller in the related technology is solved.
Drawings
FIG. 1 is a schematic block diagram of a DMA controller provided by an embodiment of the present application;
FIG. 2 is a schematic block diagram of another DMA controller provided by an embodiment of the present application;
FIG. 3 is a schematic block diagram of another DMA controller provided by an embodiment of the present application;
FIG. 4 is a schematic block diagram of another DMA controller provided by an embodiment of the present application;
FIG. 5 is a schematic diagram of a description character linked list stored in a discontinuous storage space of a target memory according to an embodiment of the present application;
FIG. 6 is a schematic block diagram of a chip provided by an embodiment of the present application;
FIG. 7 is a schematic diagram of data transmission by a root complex and endpoint device provided by an embodiment of the present application;
fig. 8 is a schematic diagram of data transmission by another root complex and endpoint device provided by an embodiment of the present application.
Reference numerals illustrate:
100-DMA controller, 110-acquisition module, 120-control module, 1201-analysis module, 1202-data channel control module, 130-status write-back module, 140-interrupt report module.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
The applicant has noted that in the related art, the existing DMA controller cannot be used in a communication device supporting multiple modes (for example, supporting both RC mode and EP mode), and there is a problem that the application scenario of the DMA controller is single.
Based on this, the embodiment of the application provides a DMA controller, which can determine the storage position of a description character linked list according to DMA control information from a target processor, and further the DMA controller can obtain the description character information by accessing a local memory or accessing an opposite-end memory according to the storage position of the description character linked list, so that the direction of the DMA controller for reading the description character information can be switched, the DMA controller can be used for RC as well as EP, and compared with the related art, the DMA controller has reusability, and the problem of single application scene of the DMA controller in the related art is solved.
The DMA controller, the chip, the root complex and the endpoint device provided by the embodiment of the application are described in detail below through specific embodiments and application scenarios thereof with reference to the accompanying drawings.
Fig. 1 is a schematic block diagram of a DMA controller according to an embodiment of the present application.
As shown in fig. 1, the DMA controller 100 according to the embodiment of the present application, applied to RC or EP, may include an acquisition module 110 and a control module 120;
The acquiring module 110 is configured to acquire DMA control information from a target processor, where the DMA control information includes information of a target memory, and the information of the target memory is used to indicate a storage location of a description character linked list;
the obtaining module 110 is further configured to determine a target memory according to the DMA control information, and obtain description character information in a description character linked list from the target memory, where the target memory includes an RC memory or an EP memory;
the control module 120 is configured to perform data transmission between the RC memory and the EP memory according to the description character information in the description character linked list.
In the embodiment of the present application, the target processor may be an RC processor or an EP processor, and the present application is not limited in particular.
For example, in the case where the DMA controller is applied to RC, the target processor may be an RC processor, where the RC processor is a local processor, the RC processor communicates with the DMA controller through an AXI bus, and the acquisition module of the DMA controller may acquire DMA control information from the RC processor through the AXI bus. Or in the case that the DMA controller is applied to RC, the target processor may be an EP processor, where the EP processor is an opposite-end processor, and the EP processor and the DMA controller communicate with each other through a PCIe bus, and the acquiring module of the DMA controller may acquire DMA control information from the EP processor through the PCIe bus.
For another example, in the case where the DMA controller is applied to EP, the target processor may be an RC processor, where the RC processor is a peer processor, and the RC processor and the DMA controller communicate with each other through a PCIe bus, and the acquiring module of the DMA controller may acquire DMA control information from the RC processor through the PCIe bus. Or in the case that the DMA controller is applied to EP, the target processor may be an EP processor, where the EP processor is a local processor, and the EP processor and the DMA controller communicate with each other through an AXI bus, and the acquisition module of the DMA controller may acquire DMA control information from the EP processor through the AXI bus.
In the embodiment of the present application, the DMA control information may be configuration information preset by the target processor to control how the DMA controller works. For example, the DMA control information may include information of a target memory, which is used to indicate a storage location of the description character link table, and the target memory may be an RC memory or an EP memory. The description character linked list comprises at least one piece of description character information, and the description character information can be used for indicating related control parameters of the DMA controller for carrying data.
In practical applications, the DMA control information may further include DMA enable information, doorbell information, etc. for instructing the DMA controller to start working, which is not particularly limited herein.
In the embodiment of the application, when the DMA controller is applied to RC, the target memory may be an RC memory, and at this time, the RC memory is a local memory, and the RC memory and the DMA controller communicate with each other through an AXI bus, and the acquisition module of the DMA controller may acquire the description character information in the description character linked list from the RC memory through the AXI bus. Or in the case that the DMA controller is applied to RC, the target memory may also be an EP memory, where the EP memory is an opposite-end memory, and the EP memory and the DMA controller are in communication through a PCIe bus, and the acquisition module of the DMA controller may acquire, through the PCIe bus, the description character information in the description character linked list from the EP memory.
In the embodiment of the application, when the DMA controller is applied to EP, the target memory may be an RC memory, and in this case, the RC memory is an opposite-end memory, the RC memory and the DMA controller communicate with each other through a PCIe bus, and the acquisition module of the DMA controller may acquire the description character information in the description character linked list from the RC memory through the PCIe bus. Or in the case that the DMA controller is applied to EP, the target memory may also be an EP memory, where the EP memory is a local memory, and the EP memory and the DMA controller may communicate with each other through an AXI bus, and the acquisition module of the DMA controller may acquire, through the AXI bus, the description character information in the description character linked list from the EP memory.
It can be understood that in the embodiment of the application, the DMA control information is configured for the DMA controller in advance by the target processor, so that the DMA controller is informed of the storage position of the description character linked list, and further, the DMA controller can access the local memory through the AXI link or access the opposite-end memory through the PCIe link according to the storage position of the description character linked list, thereby improving the flexibility of the target processor in controlling the DMA controller, being capable of switching the direction of the DMA controller for reading the description character information, widening the application scenario of the DMA controller, and enabling the DMA controller to be used for RC as well as EP.
Particularly for communication equipment compatible with RC mode and EP mode, two different DMA controllers are required to be designed for the communication equipment in the RC mode and the EP mode in the related technology, but the DMA controller provided by the embodiment of the application can be used in the RC mode of the communication equipment and also can be used in the EP mode of the communication equipment, has reusability, widens the application scene of the DMA controller compared with the related technology, simultaneously reduces the cost of the DMA controller in the communication equipment, and solves the problem of single application scene of the DMA controller in the related technology.
The DMA controller comprises an acquisition module and a control module, wherein the acquisition module is used for acquiring DMA control information from a target processor, the DMA control information comprises information of a target memory, the information of the target memory is used for indicating the storage position of a description character linked list, the acquisition module is also used for determining the target memory according to the DMA control information and acquiring description character information in the description character linked list from the target memory, the target memory comprises an RC memory or an EP memory, and the control module is used for carrying out data transmission between the RC memory and the EP memory according to the description character information in the description character linked list. Therefore, the DMA controller can determine the storage position of the description character linked list according to the DMA control information from the target processor, and further the DMA controller can acquire the description character information by accessing the local memory or the opposite-end memory according to the storage position of the description character linked list, so that the direction of the DMA controller for reading the description character information can be switched, the DMA controller can be used for RC and EP, and the problem of single application scene of the DMA controller in the related technology is solved.
Fig. 2 is a schematic block diagram of another DMA controller according to an embodiment of the present application.
In a specific embodiment, as shown in fig. 2, in the DMA controller 100 provided in the embodiment of the present application,
The control module 120 may include a parsing module 1201 and a data channel control module 1202;
The parsing module 1201 is configured to extract the description character information, convert the description character information into data handling information in a target instruction format, and transmit the data handling information to the data channel control module;
the data channel control module 1202 is configured to perform data transmission between the RC memory and the EP memory according to the data handling information.
The data channel control module 1202 may be a data channel controller, and the target instruction format may be an instruction required by the data channel controller. For example, in the case where the information amount of the description character information is relatively large, the parsing module 1201 may decompose the description character information, extract information required by the data channel controller from the description character information, and convert the information into data handling information required by the data channel controller, so that the data channel controller performs data transfer between the RC memory and the EP memory according to the data handling information.
For example, in an embodiment of the present application, the description character information may include at least one of a data description character, a status description character, and a chain connection description character.
Wherein the data description characters may be used to store the source address, destination address, data block length, etc. of the DMA transfer data.
The state description character can be used for storing the DMA execution result, and is physically the same as the corresponding data description character storage position (namely, covers the original data description character), and when the specified processor reads the state description character, the storage space can be recovered.
The chain connection description character can be used for connecting the description characters stored in the discrete storage space, so that the description characters are discontinuously stored in the storage space.
The description character information extracted by the parsing module 1201 is a data description character, and the data description character may include source address information of the data to be carried, destination address information of the data to be carried, and data amount information of the data to be carried;
The analysis module can be used for extracting data description characters in the description character information, converting source address information of data to be carried, destination address information of the data to be carried and data quantity information of the data to be carried in the data description characters into data carrying information in a target instruction format, and transmitting the data carrying information to the data channel control module.
For example, table 1 below is a schematic data structure diagram of data description characters:
TABLE 1
The data description character may include 6 Double Words (DW), each of which has a size of 32 bits.
The "DAR Low" field in the first doubleword and the "DAR High" field in the second doubleword may represent destination address information of data to be handled.
The "SAR Low" field in the third double word and the "SAR High" field in the fourth double word may represent source address information of data to be handled.
The "Transfer Size" field in the fifth doubleword may represent data amount information of the data to be handled.
The sixth double word is divided into 7 fields, wherein the "Stop" field may indicate the order of the data description characters in the description character chain table. For example, the "Stop" field is "0" indicating that this data description character is not the last data description character of the description character linked list. The Stop field is "1", which indicates that the data description character is the last data description character of the description character chain table, and after the data description character is executed, DMA completion interrupt information needs to be reported to the designated processor.
Wherein the "Reserve" field may indicate that this field is a reserved field.
Wherein the "LLP" field may indicate the type of the data description character. For example, a "LLP" field of "1" may indicate that the type of this description character is a chain connection description character, and a "LLP" field of "0" may indicate that the type of this description character is a data description character or a status description character.
Wherein the "LIE" field may indicate the direction of interrupt reporting. For example, a "LIE" field of "1" indicates that interrupt information needs to be reported to the local processor, and a "LIE" field of "0" indicates that interrupt information does not need to be reported to the local processor.
Wherein the "RIE" field may also indicate the direction of interrupt reporting. For example, a "RIE" field of "1" indicates that interrupt information needs to be reported to the opposite processor, and a "RIE" field of "0" indicates that interrupt information does not need to be reported to the opposite processor.
Wherein the "OWN" field may indicate whether this description character has been executed. For example, an "OWN" field of "1" indicates not being executed, and "0" indicates being executed. In general, the "OWN" field in the data description character is "1", and the "OWN" field in the status description character is "0".
Thus, taking the structure of the data description character shown in table 1 as an example, the parsing module may be configured to extract the data description character in the description character information, extract the information in the "SAR Low" field, the "SAR High" field, the "DAR High" field, and the "Transfer Size" field in the data description character, convert the information into the data handling information in the target instruction format, and transmit the data handling information to the data channel control module, so that the data channel control module performs data transmission between the RC memory and the EP memory according to the data handling information.
Fig. 3 is a schematic block diagram of another DMA controller according to an embodiment of the present application.
In a specific embodiment, as shown in fig. 3, in the DMA controller 100 provided in the embodiment of the present application, the data channel control module 1201 is further configured to generate a DMA execution result after performing data transmission between the RC memory and the EP memory, where the DMA execution result includes status information for reflecting the data to be handled transmitted by the DMA controller;
For example, the DMA execution result may indicate that the DMA controller is successful in executing the data to be transferred, or may indicate that the DMA controller is failed in executing the data to be transferred, or may indicate a failure type of the DMA controller that the DMA controller is failed in executing the data to be transferred, etc., which is not limited in the specific content of the DMA execution result.
As shown in fig. 3, the DMA controller 100 according to the embodiment of the present application further includes a status write-back module 130;
The status write-back module 130 is configured to obtain a DMA execution result from the data channel control module, and generate a status description character corresponding to the data description character according to the DMA execution result;
the state write-back module 130 is further configured to transmit the state description character to a target memory, so that the target memory stores the state description character in a manner that the state description character is overlaid.
For example, table 2 below is a schematic data structure diagram of a state description character:
TABLE 2
Wherein, the state description character shown in table 2 is different from the data description character shown in table 1 in that:
2 fields, SEC field and Error Type field, are redefined in the 6-31bit "Reserve" field of the sixth doubleword.
Wherein, the SEC field and the Error Type field are used for indicating the DMA execution result.
The SEC field is used for indicating whether the DMA controller successfully executes the data to be carried in the transmission. For example, "SEC" is "1" indicates execution success, and "SEC" is "0" indicates execution failure.
The "Error Type" field is used to indicate a failure Type of the DMA controller that the DMA controller fails to transfer the data to be handled.
Thus, taking the structure of the status description character shown in table 2 as an example, in the process of the status writing back module 130 generating the status description character corresponding to the data description character, the status writing back module 130 may write the "OWN" field as "0", which indicates that this data description character has been executed, and write corresponding contents in the "SEC" field and the "Error Type" field according to the DMA execution result.
In another specific embodiment, in the case that all the data description characters in the description character linked list have been executed, the DMA controller may further report DMA completion interrupt information to the specified processor, so that the specified processor obtains the status description characters from the target memory, and determines a DMA execution result according to the status description characters. The following is illustrative:
In the embodiment of the application, the description character chain table comprises a target data description character, wherein the target data description character is the last data description character in the description character chain table, and the target data description character comprises configuration information for indicating the interruption reporting direction.
For example, taking the structure of the data description character shown in table 1 as an example, the "Stop" field of the target data description character is "1", which indicates that the target data description character is the last data description character of the description character linked list. Configuration information contained in the target data description character for indicating the direction of interrupt reporting may be stored in the "LIE" field and/or the "RIE" field.
As shown in fig. 4, the DMA controller 100 provided in the embodiment of the present application may further include an interrupt control module 140;
The interrupt control module 140 may be configured to determine the designated processor according to the configuration information in the target data description character for indicating the direction of reporting the interrupt, and report the DMA completion interrupt information to the designated processor, so that the designated processor obtains the state description character from the target memory, and determines the DMA execution result according to the state description character.
The configuration information for indicating the interrupt reporting direction comprises first configuration information and/or second configuration information, wherein the first configuration information is used for indicating that the appointed processor comprises a local processor, and the second configuration information is used for indicating that the appointed processor comprises an opposite-end processor.
Taking the structure of the data description character shown in table 1 as an example, the first configuration information may be stored in the "LIE" field and the second configuration information may be stored in the "RIE" field. For example, a "LIE" field of "1" indicates that DMA completion interrupt information is to be reported to local memory. Or the "RIE" field of "1" indicates that DMA completion interrupt information is reported to the peer memory. Or the "LIE" field and the "RIE" field may both be "1" indicating that DMA completion interrupt information is to be reported to the local memory and the peer memory.
Wherein, in case the DMA controller is applied to RC, the first configuration information is used to indicate that the specified processor comprises an RC processor, and the second configuration information is used to indicate that the specified processor comprises an EP processor;
Wherein, in case the DMA controller is applied to an EP, the first configuration information is used to indicate that the specified processor comprises an EP processor and the second configuration information is used to indicate that the specified processor comprises an RC processor.
In the embodiment of the present application, the specified processor may be an RC processor, an EP processor, or an RC processor and an EP processor, which is not particularly limited in the present application.
The specified processor and the target processor may be the same processor or different processors, and the present application is not limited in particular.
For example, in the case that the DMA controller is applied to RC, the "LIE" field of the data description character is "1", the designated processor may be an RC processor, where the RC processor is a local processor, and the RC processor communicates with the DMA controller through an AXI bus, and the interrupt control module 140 of the DMA controller may report DMA completion interrupt information to the RC processor through the AXI bus, so that the RC processor obtains the state description character from the target memory, and determines the DMA execution result according to the state description character.
Or in the case that the DMA controller is applied to RC, the "RIE" field of the data description character is "1", the designated processor may be an EP processor, and at this time, the EP processor is an opposite-end processor, and the EP processor and the DMA controller communicate with each other through a PCIe bus, and the interrupt control module 140 of the DMA controller may report DMA completion interrupt information to the EP processor through the PCIe bus, so that the EP processor obtains the state description character from the target memory, and determines the DMA execution result according to the state description character.
Or in the case that the DMA controller is applied to RC, the "LIE" field and the "RIE" field of the data description character are both "1", the designated processor may be an RC processor and an EP processor, where the RC processor is a local processor and the EP processor is an opposite-end processor, the RC processor communicates with the DMA controller through an AXI bus, the EP processor communicates with the DMA controller through a PCIe bus, the interrupt control module 140 of the DMA controller may report DMA completion interrupt information to the RC processor through the AXI bus, and the DMA completion interrupt information may be reported to the EP processor through the PCIe bus, so that the RC processor and the EP processor acquire status description characters from the target memory, and determine a DMA execution result according to the status description characters.
For another example, in the case where the DMA controller is applied to EP, the "RIE" field of the data description character is "1", the designated processor may be an RC processor, where the RC processor is an opposite-end processor, and the RC processor communicates with the DMA controller through a PCIe bus, and the interrupt control module 140 of the DMA controller may report DMA completion interrupt information to the RC processor through the PCIe bus, so that the RC processor obtains the state description character from the target memory, and determines the DMA execution result according to the state description character.
Or in the case that the DMA controller is applied to EP, the "LIE" field of the data description character is "1", the designated processor may be an EP processor, and at this time, the EP processor is a local processor, and the EP processor and the DMA controller communicate with each other through an AXI bus, and the interrupt control module 140 of the DMA controller may report DMA completion interrupt information to the EP processor through the AXI bus, so that the EP processor obtains the state description character from the target memory, and determines the DMA execution result according to the state description character.
Or in the case that the DMA controller is applied to EP, the "RIE" field and the "LIE" field of the data description character are both "1", the designated processor may be an RC processor and an EP processor, where the RC processor is an opposite-end processor, the EP processor is a local processor, the RC processor and the DMA controller communicate with each other through a PCIe bus, the EP processor and the DMA controller communicate with each other through an AXI bus, the interrupt control module 140 of the DMA controller may report DMA completion interrupt information to the RC processor through the PCIe bus, and the DMA completion interrupt information may be reported to the EP processor through the AXI bus, so that the RC processor and the EP processor acquire status description characters from the target memory, and determine the DMA execution result according to the status description characters.
In this way, the DMA controller is informed to report the DMA completion interrupt information to the local processor and/or the opposite terminal processor by configuring the DMA completion interrupt information reporting direction for the DMA controller in advance through the first configuration information and/or the second configuration information in the data description character. Furthermore, the DMA controller can report DMA completion interrupt information to the local controller through the AXI link or report DMA completion interrupt information to the opposite-end controller through the PCIe link according to the first configuration information and/or the second configuration information in the data description character, so that flexibility of the DMA controller is improved, and a direction in which the DMA controller reports the DMA completion interrupt information can be switched.
For example, taking the structure of the data description character shown in table 1 as an example, the "RIE" field and the "LIE" field in the data description character acquired by the DMA controller indicate whether DMA completion interrupt information needs to be generated to the opposite processor or the local processor. After analyzing the data description character, the DMA controller can directly report the interrupt information of the completion of the DMA to the opposite terminal processor and/or the local processor. Particularly, when the DMA completion interrupt information needs to be reported to the opposite-end processor, the DMA controller directly reports the DMA interrupt information to the opposite-end processor through the PCIe link, and the local processor is not needed to participate in forwarding during the process.
In addition, for communication equipment compatible with RC mode and EP mode, the DMA controller can dynamically control the direction of interrupt reporting under RC mode and EP mode, so that the DMA controller can be used for both RC mode and EP mode, and the application scene of the DMA controller is widened.
In this way, the DMA controller provided by the embodiment of the application can be applied to communication equipment compatible with an EP mode and an RC mode, and the reporting direction of the DMA completion interrupt information can also be directly controlled through the RIE field and the LIE field in the data description character, so that the DMA controller has higher robustness.
In practical application, the embodiment of the application can discontinuously store the description character linked list in the target memory under the condition that the description character linked list is longer and the continuous space of the target memory is insufficient. When the description character linked list is to be physically stored discontinuously, the description characters can be linked to the physical address of the next data description character. Under the conditions that the storage space of the target memory is discrete and the description character linked list is long, the DMA controller is ensured to work normally. The following is an example.
In a specific embodiment, the description character linked list comprises a plurality of pieces of description character information, and the pieces of description character information are discontinuously stored in a plurality of storage spaces of the target memory;
The plurality of pieces of descriptive character information comprise chain connection descriptive characters stored in a first storage space of the target memory and data descriptive characters stored in a second storage space of the target memory, wherein the second storage space is a storage space discrete from the first storage space.
In an embodiment of the present application, the chain connection description character includes a target pointer for indicating a physical address of the data description character stored in the second storage space of the target memory.
Taking the target memory shown in fig. 5 as an example, a plurality of pieces of descriptive character information in the descriptive character linked list are discontinuously stored in a first storage space, a second storage space and a third storage space, and the first storage space, the second storage space and the third storage space are mutually discrete storage spaces. The link description character 1 is stored in a first storage space of the target memory, the data description character 4 is stored in a second storage space of the target memory, and the link description character 1 contains a target pointer for indicating a physical address of the data description character 4.
Of course, the target memory shown in fig. 5 is only an example, and the present application is not limited to the number of discrete memory spaces of the target memory, the number of data description characters stored in each memory space, and the number of chain connection description characters.
In this way, the embodiment of the application connects the description characters through the chain connection, and the data description characters stored in the discrete storage space are connected, so that the discontinuous storage of the description character information in the storage space is realized, and the discontinuous storage of the description character linked list is realized under the condition that the continuous space of the target memory is insufficient when the description character linked list is longer.
The contents of the chain connection description characters in the description character linked list are described in detail below in conjunction with the data structure of the chain connection description characters. For example, table 3 is a schematic data structure diagram of a chain connection description character:
TABLE 3 Table 3
The chain connection descriptor may include 6 Double Words (DW), each of which has a size of 32 bits.
Wherein the first doubleword, the second doubleword, and the third doubleword are "Reserve" fields, indicating that the fields are reserved fields.
Wherein the "Next TRANSFER LIST Pointer Address Low" field in the fourth doubleword and the "Next TRANSFER LIST Pointer ADDRESS HIGH" field in the fifth doubleword may represent a target Pointer for indicating the physical address of the Next data description character stored in the discrete memory space.
Wherein the sixth double word is divided into three fields, wherein the "LLP" field may indicate the type of the data description character. For example, an "LLP" field of "1" may indicate that this description character is of the type chain connection description character. Two "Reserve" fields may indicate that this field is a reserved field.
Thus, taking the target memory shown in fig. 5 as an example, the "Next TRANSFER LIST Pointer Address Low" field and the "Next TRANSFER LIST Pointer ADDRESS HIGH" field in the chain connection description character 1 are used for indicating the physical address of the data description character 4, and the data description character (for example, the data description character 3) stored in the first storage space is connected with the data description character (for example, the data description character 4) stored in the second storage space, so that discontinuous storage of description character information in the storage space is realized, and discontinuous storage of the description character linked list is realized when the continuous space of the target memory is insufficient when the description character linked list is long.
Furthermore, in the DMA controller 100 provided in the embodiment of the present application, the obtaining module 100 may be specifically configured to obtain, according to information of a target memory in the DMA control information, a chain connection description character from the target memory, and obtain, according to a target pointer included in the chain connection description character, a data description character stored in a second storage space of the target memory.
For example, taking the target memory shown in fig. 5 as an example, the acquiring module 100 may acquire the chain connection description character 1 from the target memory according to the information of the target memory in the DMA control information, and then acquire the data description character 4 stored in the second storage space according to the target pointer included in the chain connection description character 1.
In this way, the embodiment of the application indicates the physical address of the next data description character stored in the discrete storage space through the target pointer contained in the chain connection description character, and further, the DMA controller can acquire the description character information in the discrete storage space according to the target pointer, and the DMA controller is ensured to work normally under the condition that the description character linked list is discontinuously stored in the target memory.
Based on the same conception as the DMA controller provided by the embodiment of the application, the embodiment of the application also provides a chip.
Fig. 6 is a schematic structural diagram of a chip according to an embodiment of the present application.
As shown in fig. 6, an embodiment of the present application further provides a chip, including a processor, a memory, and a DMA controller provided in any one of the foregoing embodiments, where the processor is connected to the memory and the DMA controller, and the memory is connected to the DMA controller.
The chip provided by the embodiment of the application can comprise a 4G chip, a 5G chip and the like, and the application is not particularly limited to the type of the chip.
The chip provided by the embodiment of the application can realize each process realized by the DMA controller and can achieve the same technical effect, and in order to avoid repetition, the description is omitted here.
Based on the same concept as the DMA controller provided by the embodiment of the present application, the embodiment of the present application also provides a root complex.
As shown in FIG. 7, an embodiment of the present application further provides a root complex that may include an RC processor, an RC memory, a DMA controller provided by any of the above embodiments, and a first PCIe controller;
The RC processor is respectively connected with the RC memory and the DMA controller, the RC memory is connected with the DMA controller, and the DMA controller is connected with the first PCIe controller.
In an embodiment of the present application, as shown in fig. 7, the process of DMA data transfer by the root complex may include:
① The RC processor stores the description character linked list into an RC memory;
② The RC processor sends DMA control information to the DMA controller;
③ The acquisition module of the DMA controller acquires description character information in the description character linked list from the RC memory according to the DMA control information;
④ The analysis module of the DMA controller extracts the data description character and converts the data description character into data carrying information in a target instruction format;
⑤ The analysis module of the DMA controller transmits the data carrying information to the data channel control module of the DMA controller;
⑥ The data channel control module of the DMA controller performs data transmission between the RC memory and the EP memory according to the data carrying information and generates a DMA executing result;
⑦ The state write-back module of the DMA controller acquires the DMA execution result, and generates a state description character corresponding to the data description character according to the DMA execution result;
⑧ The interrupt control module of the DMA controller can determine the RC processor according to the configuration information used for indicating the interrupt reporting direction in the data description character, and report the interrupt information of the DMA completion to the RC processor;
⑨ The RC processor acquires the state description character from the RC memory and determines a DMA execution result according to the state description character.
In the embodiment of the present application, in the steps ① and ②, the EP processor may control the DMA controller in addition to the RC processor, which is not limited by the present application.
In the embodiment of the application, the description character linked list can be stored in the EP memory besides the RC memory, and the application is not limited to the description character linked list.
In step ⑥, the data channel control module of the DMA controller may access the RC memory through the AXI bus, access the EP memory through the PCIe bus, complete data handling between the RC memory and the EP memory, and save the DMA execution result in the data handling process.
In step ⑦, after the data channel control module completes data handling of one data description character, the DMA execution result is sent to the status write-back module, which is responsible for writing the DMA execution result back into the storage space corresponding to the original data description character.
In step ⑧, if the data description character being executed is the last data description character in the description character chain table (i.e., stop field=1), the interrupt control module of the DMA controller determines to send the DMA completion interrupt information to the local processor (i.e., RC processor) according to the values of the "RIE" field and the "LIE" field in the data description character (the DMA controller in fig. 7 operates in RC mode, designates the processor as the RC processor, rie=0, lie=1).
Of course, in the embodiment of the present application, in addition to sending the DMA completion interrupt information to the local processor, the DMA completion interrupt information may also be sent to the opposite processor (i.e., the EP processor). For example, by means of the RC processor writing a value to the terminal register of the EP, DMA completion interrupt information is generated and reported to the EP processor. Of course, the present application may also send the DMA completion interrupt information to the peer processor in other manners, and the present application is not limited in this regard.
The root complex provided by the embodiment of the application can realize each process realized by the DMA controller and can achieve the same technical effect, and in order to avoid repetition, the description is omitted here.
Based on the same concept as the DMA controller provided by the embodiment of the present application, the embodiment of the present application also provides an endpoint device.
As shown in fig. 8, an embodiment of the present application further provides an endpoint device, which may include an EP processor, an EP memory, a DMA controller provided in any of the foregoing embodiments, and a second PCIe controller;
The EP processor is respectively connected with the EP memory and the DMA controller, the EP memory is connected with the DMA controller, and the DMA controller is connected with the second PCIe controller.
In an embodiment of the present application, as shown in fig. 8, the process of DMA data transmission by the endpoint device may include:
① The RC processor stores the description character linked list into the EP memory through the PCIe bus;
② The RC processor sends DMA control information to the DMA controller through a PCIe bus;
③ The acquisition module of the DMA controller acquires description character information in the description character linked list from the EP memory according to the DMA control information;
④ The analysis module of the DMA controller extracts the data description character and converts the data description character into data carrying information in a target instruction format;
⑤ The analysis module of the DMA controller transmits the data carrying information to the data channel control module of the DMA controller;
⑥ The data channel control module of the DMA controller performs data transmission between the RC memory and the EP memory according to the data carrying information and generates a DMA executing result;
⑦ The state write-back module of the DMA controller acquires the DMA execution result, and generates a state description character corresponding to the data description character according to the DMA execution result;
⑧ The interrupt control module of the DMA controller can determine the RC processor according to the configuration information used for indicating the interrupt reporting direction in the data description character, and report the interrupt information of the DMA completion to the RC processor through the PCIe bus;
⑨ The RC processor acquires the state description character from the EP memory through the PCIe bus, and determines a DMA execution result according to the state description character.
In the embodiment of the present application, in the steps ① and ②, the EP processor may control the DMA controller in addition to the RC processor, which is not limited by the present application.
In the embodiment of the application, the description character linked list can be stored in the RC memory besides the EP memory, and the application is not limited to the description character linked list.
In step ⑥, the data channel control module of the DMA controller may access the EP memory through the AXI bus, access the RC memory through the PCIe bus, complete data handling between the RC memory and the EP memory, and save the DMA execution result in the data handling process.
In step ⑦, after the data channel control module completes data handling of one data description character, the DMA execution result is sent to the status write-back module, which is responsible for writing the DMA execution result back into the storage space corresponding to the original data description character.
In step ⑧, if the data description character being executed is the last data description character in the description character chain table (i.e. Stop field=1), the interrupt control module of the DMA controller determines to send the DMA completion interrupt information to the opposite processor (i.e. RC processor) according to the values of the "RIE" field and the "LIE" field in the data description character (the DMA controller in fig. 7 works in EP mode, designates the processor as RC processor, rie=1, lie=0), and specifically selects any one of the three interrupt sending modes legacy, MSI, MSI-X defined in the PCIe protocol to send the DMA completion interrupt information.
Of course, in the embodiment of the present application, in addition to sending the DMA completion interrupt information to the peer processor, the DMA completion interrupt information may also be sent to the local processor.
The endpoint device provided by the embodiment of the application can realize each process realized by the DMA controller and can achieve the same technical effect, and in order to avoid repetition, the description is omitted here.
In this way, in the DMA controller provided by the embodiment of the application, in the RC mode and the EP mode, the storage position of the description character linked list can be determined according to the DMA control information from the RC processor, and then the DMA controller can obtain the description character information by accessing the local memory or accessing the opposite terminal memory according to the storage position of the description character linked list, so that the direction of the DMA controller for reading the description character information can be switched, the DMA controller can be used for RC and EP, and compared with the related art, the DMA controller has reusability, the problem of single application scene of the DMA controller in the related art is solved, and the cost of the DMA controller is reduced for the communication equipment compatible with the RC mode and the EP mode.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims (11)

1. A DMA controller, which is applied to a root complex RC or an endpoint device EP, comprising an acquisition module and a control module;
the acquisition module is used for acquiring DMA control information from a target processor, wherein the DMA control information comprises information of a target memory, and the information of the target memory is used for indicating the storage position of a description character linked list;
The acquisition module is also used for determining a target memory according to the DMA control information and acquiring description character information in a description character linked list from the target memory, wherein the target memory comprises an RC memory or an EP memory;
and the control module is used for carrying out data transmission between the RC memory and the EP memory according to the description character information in the description character linked list.
2. The DMA controller of claim 1, wherein the control module comprises a parsing module and a data channel control module;
The analysis module is used for extracting the description character information, converting the description character information into data handling information in a target instruction format, and transmitting the data handling information to the data channel control module;
the data channel control module is used for carrying out data transmission between the RC memory and the EP memory according to the data handling information.
3. The DMA controller according to claim 2, wherein the description character information includes a data description character containing source address information of data to be handled, destination address information of data to be handled, and data amount information of data to be handled;
The analysis module is used for extracting data description characters in the description character information, converting source address information of data to be carried, destination address information of the data to be carried and data quantity information of the data to be carried in the data description characters into data carrying information in a target instruction format, and transmitting the data carrying information to the data channel control module.
4. The DMA controller according to claim 3, wherein,
The data channel control module is also used for generating a DMA execution result after data transmission between the RC memory and the EP memory, wherein the DMA execution result comprises state information for reflecting the data to be carried transmitted by the DMA controller;
the DMA controller also comprises a status write-back module;
The state write-back module is used for acquiring a DMA execution result from the data channel control module and generating a state description character corresponding to the data description character according to the DMA execution result;
the state write-back module is further configured to transmit the state description character to a target memory, so that the target memory stores the state description character in a manner of covering the data description character.
5. The DMA controller of claim 4 wherein the description character linked list includes a target data description character, the target data description character being a last data description character in the description character linked list, the target data description character including configuration information for indicating an interrupt reporting direction;
the DMA controller also comprises an interrupt control module;
The interrupt control module is used for determining a designated processor according to configuration information used for indicating the interrupt reporting direction in the target data description character, reporting the DMA completion interrupt information to the designated processor, so that the designated processor obtains the state description character from the target memory, and determining a DMA execution result according to the state description character.
6. The DMA controller according to claim 5, wherein the configuration information for indicating the interrupt reporting direction includes first configuration information for indicating that the specified processor includes a local processor and/or second configuration information for indicating that the specified processor includes a peer processor;
In the case where the DMA controller is applied to an RC, the first configuration information is used to indicate that the specified processor includes an RC processor, and the second configuration information is used to indicate that the specified processor includes an EP processor;
in case the DMA controller is applied to an EP, the first configuration information is used to indicate that the specified processor comprises an EP processor and the second configuration information is used to indicate that the specified processor comprises an RC processor.
7. The DMA controller according to any of the claims 1-6, characterized in that,
The description character linked list comprises a plurality of pieces of description character information which are discontinuously stored in a plurality of storage spaces of the target memory;
The plurality of pieces of descriptive character information comprise chain connection descriptive characters stored in a first storage space of the target memory and data descriptive characters stored in a second storage space of the target memory, wherein the second storage space is a storage space discrete from the first storage space;
The chain connection description character includes a target pointer for indicating a physical address of a data description character stored in a second storage space of the target memory.
8. The DMA controller according to claim 7, wherein the obtaining module is specifically configured to obtain a chain connection description character from a target memory according to information of the target memory in the DMA control information, and obtain a data description character stored in a second storage space of the target memory according to a target pointer included in the chain connection description character.
9. A chip comprising a processor, a memory and a DMA controller according to any of claims 1-8, wherein the processor is connected to the memory and the DMA controller, respectively, and wherein the memory is connected to the DMA controller.
10. A root complex comprising an RC processor, an RC memory, the DMA controller of any of claims 1-8, and a first PCIe controller;
The RC processor is respectively connected with the RC memory and the DMA controller, the RC memory is connected with the DMA controller, and the DMA controller is connected with the first PCIe controller.
11. An endpoint device comprising an EP processor, an EP memory, a DMA controller according to any of claims 1-8, and a second PCIe controller;
The EP processor is respectively connected with the EP memory and the DMA controller, the EP memory is connected with the DMA controller, and the DMA controller is connected with the second PCIe controller.
CN202310699192.9A 2023-06-13 2023-06-13 DMA controllers, chips, root complexes, and endpoint devices Pending CN119127751A (en)

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CN106547709A (en) * 2016-11-24 2017-03-29 盛科网络（苏州）有限公司 The method and device of flexible configuration multi-channel DMA controller
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