CN119153400A - Interconnection structure based on back power supply and preparation method thereof - Google Patents
Interconnection structure based on back power supply and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本申请提供一种基于背面供电的互连结构及其制备方法，涉及集成电路技术领域，通过利用金属化的纳米埋入式电源轨对金属化的背面接触孔实现在外延层背面形成电源布线层，即实现背面供电，这样不仅能够有效缓解传统电源线和信号线同侧布置所导致的高压降，提高功率传输性能，减少布线的拥塞，而且更重要的是能够利用金属化的纳米埋入式电源轨进一步的降低电阻，提高设计兼容性。
The present application provides an interconnect structure based on back-side power supply and a preparation method thereof, which relates to the field of integrated circuit technology. By using a metallized nano-embedded power rail to metallized back contact holes, a power wiring layer is formed on the back side of an epitaxial layer, that is, back-side power supply is realized. This can not only effectively alleviate the high voltage drop caused by the arrangement of traditional power lines and signal lines on the same side, improve power transmission performance, and reduce wiring congestion, but more importantly, the metallized nano-embedded power rail can be used to further reduce resistance and improve design compatibility.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to an interconnection structure based on back power supply and a preparation method thereof.
Background
Chip fabrication begins with the smallest component transistor and then gradually builds up smaller and smaller wiring layers for connecting the transistor to the various parts of the chip and for powering the chip, so the wiring layers typically include power and signal lines on the same side of the chip. However, as the transistors become smaller and higher in density, the circuit layer where the signal lines and the power lines coexist becomes an increasingly chaotic network, which becomes an obstacle to improving the overall performance of the chip.
In order to optimize the layout structure of the circuit layer and improve the overall performance of the chip, the concept of back power supply is proposed, and the back power supply is used for searching to move the power line to the back of the chip, so that the front of the chip is only focused on signal interconnection, and the voltage drop caused by high resistance of the power line can be effectively relieved, and the power transmission performance is improved. But the back power supply structure in the current industry has higher resistance and poorer design compatibility.
Disclosure of Invention
The application aims to overcome the defects in the prior art and provide an interconnection structure based on back side power supply and a preparation method thereof.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the application is as follows:
in one aspect of the embodiment of the application, a method for preparing an interconnection structure based on back side power supply is provided, which comprises the following steps:
A wafer substrate with an epitaxial layer of a certain thickness is chosen (the thickness of the epitaxial layer will affect the final thickness of the substrate after thinning, preferably a 2um to 6um epitaxial layer).
The method comprises the steps of forming metal power supply rails and device structures which are distributed at intervals on the front surface of an epitaxial layer, wherein the metal power supply rails comprise nano embedded power supply rails extending from the front surface of the epitaxial layer to the inside of the epitaxial layer and front metal filled in the nano embedded power supply rails, in other words, a silicon substrate wafer (wafer substrate) with a certain thickness of the epitaxial layer is formed on the surface and inside of the epitaxial layer, the metal power supply rails are formed on the surface of the epitaxial layer, the silicon substrate wafer is firstly formed, then the epitaxial layer is grown on the surface of the silicon substrate wafer, and then the device structures are formed on the surface of the epitaxial layer.
Forming a signal wiring layer covering the metal power rail and the device structure on the front surface of the epitaxial layer, wherein the signal wiring layer is respectively connected with the metal power rail and the device structure in a metal manner;
bonding a carrier wafer on the front surface of the signal wiring layer;
thinning at least the wafer substrate to expose the epitaxial layer from the back surface;
Forming a back contact hole correspondingly communicated with the nano embedded power rail on the back of the epitaxial layer;
filling back metal in contact with the front metal in the back contact hole;
And forming a power wiring layer on the back surface of the epitaxial layer, wherein the power wiring layer is connected with the back metal.
Optionally, the nano-embedded power rail is any one of an elongated groove, an annular groove, and a circular groove.
Optionally, the number of the back contact holes is multiple, and the multiple back contact holes are correspondingly communicated with the same nano embedded power rail.
Optionally, forming the metal power rails and the device structure in the front surface of the epitaxial layer in a spaced apart manner includes:
forming a nano embedded power rail extending into the epitaxial layer on the front surface of the epitaxial layer;
filling front metal in the nano embedded power rail;
And a device structure positioned beside the nano-embedded power rail is formed on the front surface of the epitaxial layer.
Optionally, forming a nano-buried power rail on the front side of the epitaxial layer that extends into the epitaxial layer includes:
Forming a first dielectric layer on the front surface of the epitaxial layer;
Forming a first window exposing the epitaxial layer on the first dielectric layer through photoetching;
and etching the epitaxial layer in the first window by using the first dielectric layer as a mask layer to form the nano embedded power rail.
Optionally, filling the nano-buried power rail with the front metal includes:
Forming a first isolation buffer layer on the bottom wall and the side wall of the nano embedded power rail;
Forming a first metal barrier layer on the surface of the first isolation buffer layer;
and forming a front metal positioned in the nano-buried power rail on the surface of the first metal barrier layer.
Optionally, forming a device structure on the front side of the epitaxial layer beside the nano-buried power rail includes:
Depositing a first insulating layer covering front metal on the front side of the first dielectric layer;
Sequentially etching the first insulating layer and the first dielectric layer to form a second window exposing the epitaxial layer, wherein the second window is positioned at the side of the nano embedded power rail;
and forming a device structure on the epitaxial layer in the second window.
Optionally, thinning at least the wafer substrate to expose the epitaxial layer from the back side includes:
coarsely thinning the wafer substrate from the back surface of the wafer substrate to form a thinned wafer;
and after the wafer is thinned, continuously carrying out the fine thinning of the preset depth on the epitaxial layer so as to expose the first isolation buffer layer in the nano embedded power rail on the back surface of the epitaxial layer.
Optionally, forming a back contact hole on the back surface of the epitaxial layer in corresponding communication with the nano-buried power rail includes:
Forming a composite dielectric layer on the back of the epitaxial layer;
etching the back of the composite dielectric layer to form a first contact hole, wherein the first contact hole is terminated in an intermediate layer in the composite dielectric layer;
Etching the back surface of the composite dielectric layer to form a wiring groove overlapped with the first contact hole in the composite dielectric layer;
And etching the composite dielectric layer and the first isolation buffer layer in the first contact hole in sequence to form a second contact hole in the composite dielectric layer and the first isolation buffer layer, wherein the front metal is exposed in the second contact hole, and the first contact hole and the second contact hole are used as back contact holes.
Optionally, filling the back contact hole with the back metal in contact with the front metal includes:
And forming a second metal barrier layer and a back metal in the wiring groove and the back contact hole through a Damascus process.
In another aspect of the embodiments of the present application, a backside-powered interconnect structure is provided, and the backside-powered interconnect structure is prepared by any one of the methods for preparing a backside-powered interconnect structure described above.
The beneficial effects of the application include:
The application provides an interconnection structure based on back power supply and a preparation method thereof, wherein a power wiring layer is formed on the back of an epitaxial layer by utilizing a metallized nano embedded power rail to a metallized back contact hole, namely back power supply is realized, so that high voltage drop caused by arrangement of a traditional power line and a signal line on the same side can be effectively relieved, the power transmission performance is improved, wiring congestion is reduced, and more importantly, resistance can be further reduced by utilizing the metallized nano embedded power rail, and design compatibility is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic state diagram of a method for manufacturing an interconnection structure based on back side power supply according to an embodiment of the present application;
FIG. 2 is a second schematic state diagram of a method for fabricating a backside-powered interconnect structure according to an embodiment of the present application;
FIG. 3 is a third schematic state diagram of a method for fabricating a backside-powered interconnect structure according to an embodiment of the present application;
FIG. 4 is a schematic diagram showing a state of a back side power supply-based interconnection structure manufacturing method according to an embodiment of the present application;
FIG. 5 is a schematic diagram showing a method for fabricating a backside-powered interconnect structure according to an embodiment of the present application;
FIG. 6 is a schematic diagram showing a method for fabricating an interconnection structure based on back side power supply according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a back side power supply-based interconnect structure fabrication method according to an embodiment of the present application;
FIG. 8 is a schematic diagram illustrating a back side power supply-based interconnect structure fabrication method according to an embodiment of the present application;
FIG. 9 is a schematic diagram illustrating a state of a back side power supply-based interconnect structure fabrication method according to an embodiment of the present application;
FIG. 10 is a schematic diagram showing a method for fabricating a backside-powered interconnect structure according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a back side power supply-based interconnect structure according to an embodiment of the present application;
FIG. 12 is a schematic diagram showing a back side power supply-based interconnect structure fabrication method according to an embodiment of the present application;
FIG. 13 is a schematic diagram showing thirteenth status of a method for fabricating a backside-powered interconnect structure according to an embodiment of the present application;
FIG. 14 is a schematic diagram showing fourteen states of a method for fabricating a backside-powered interconnect structure according to an embodiment of the present application;
FIG. 15 is a schematic diagram showing fifteen states of a method for fabricating a backside-powered interconnect structure according to an embodiment of the present application;
FIG. 16 is a schematic illustration of a state diagram of a backside-powered interconnect structure fabrication method according to an embodiment of the present application;
FIG. 17 is a schematic diagram showing seventeen states of a method for fabricating a backside-powered interconnect structure according to an embodiment of the present application;
FIG. 18 is a schematic diagram showing an eighteenth embodiment of a method for fabricating a backside-powered interconnect structure;
FIG. 19 is a schematic diagram of a nano-buried power rail according to an embodiment of the present application;
FIG. 20 is a second schematic diagram of a nano-buried power rail according to an embodiment of the present application;
FIG. 21 is a third schematic illustration of a shape of a nano-buried power rail according to an embodiment of the present application;
Fig. 22 is a schematic diagram of a correspondence relationship between a nano embedded power rail and a back contact hole according to an embodiment of the present application.
The icons are 110-wafer substrate, 111-thinned wafer, 120-epitaxial layer, 130-first dielectric layer, 140-alignment mark, 150-first window, 160-nano buried power rail, 170-first isolation buffer layer, 180-metal power rail, 181-front metal, 190-first insulating layer, 210-second window, 220-device structure, 230-second insulating layer, 240-first contact via, 250-signal wiring layer, 260-carrier wafer, 310-back metal, 320-power wiring layer, 330-wiring trench, 350-metal block, 360-fourth insulating layer, 371-first silicon oxide layer, 372-first silicon nitride layer, 373-second silicon oxide layer, 380-back contact hole, 381-first contact hole, 382-second contact hole.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. It should be noted that, under the condition of no conflict, the features of the embodiments of the present application may be combined with each other, and the combined embodiments still fall within the protection scope of the present application.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present application, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are directions or positional relationships based on those shown in the drawings, or those that are conventionally put in use of the product of the application, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific direction, be configured and operated in a specific direction, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected through an intermediary, or in communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In one aspect of the embodiment of the application, a method for preparing an interconnection structure based on back side power supply is provided, which comprises the following steps:
And S10, selecting a wafer substrate with an epitaxial layer with a certain thickness.
As shown in fig. 1, a wafer substrate 110 having an epitaxial layer 120 of a certain thickness is selected. Wherein the epitaxial layer 120 may be doped during deposition to achieve a different doping concentration control than the wafer substrate 110. It will be appreciated that 2 to 6 microns thick epitaxial layer 120 may be selected, as epitaxial layer 120 may affect the final thickness of the substrate after subsequent S50 thinning (such as the remaining epitaxial layer 120 thickness shown in fig. 18, which is less than the epitaxial layer 120 thickness prior to thinning). The front surface and the back surface of the epitaxial layer 120 are two opposite side surfaces of the epitaxial layer 120 in the thickness direction, for example, in fig. 1, a side indicated by an arrow a is the front surface (the same applies to the following figures), that is, the upper surface of the epitaxial layer 120 is the front surface, and the lower surface of the epitaxial layer 120 is the back surface.
And S20, forming metal power rails 180 and device structures 220 which are distributed at intervals on the front surface of the epitaxial layer 120, wherein the metal power rails 180 comprise nano-buried power rails 160 extending from the front surface of the epitaxial layer 120 into the epitaxial layer 120 and front surface metal 181 filled in the nano-buried power rails 160.
As shown in fig. 2 to 8, the metal power rail 180 and the device structure 220 are formed on the front surface of the epitaxial layer 120 through a series of processes (such as etching, deposition, ion implantation, etc.), and the metal power rail 180 and the device structure 220 are spaced apart from each other, in other words, the front surface of the epitaxial layer 120 may be divided into a first area and a second area that do not intersect, where the metal power rail 180 is located in the first area and the device structure 220 is located in the second area.
The metal power rail 180 is buried in the epitaxial layer 120, as shown in fig. 2 to 4, the metal power rail 180 includes a nano-buried power rail 160 and a front metal 181, and specifically, the nano-buried power rail 160 is a groove that is perforated from the front surface of the epitaxial layer 120 and extends to a certain depth (not penetrating through the epitaxial layer 120) inside the epitaxial layer 120 toward the back surface of the epitaxial layer 120, and then the front metal 181 is filled in the groove by metallizing the groove.
As shown in fig. 5-8, a device structure 220 is fabricated in a second region of the front side of the epitaxial layer 120, and the device structure 220 may be a transistor, a chip, or the like. It should be appreciated that the present application is not limited to the number of metal power rails 180 and device structures 220 that are disposed on the front side of epitaxial layer 120. In addition, it should be further understood that the nano-buried power rail 160 is different from the nano-silicon through hole, wherein the nano-buried power rail 160 has a larger structural cross section than the nano-silicon through hole and a lower resistance, and the nano-buried power rail 160 can be designed in different shapes and sizes according to requirements, so that the nano-buried power rail is compatible with various designs, has better performance, and therefore, has different structures and application scenes.
And S30, forming a signal wiring layer 250 covering the metal power rail 180 and the device structure 220 on the front surface of the epitaxial layer 120, wherein the signal wiring layer 250 is respectively connected with the metal power rail 180 and the device structure 220 in a metal manner.
As shown in fig. 9 and 10, after the metal power supply rail 180 and the device structure 220 are fabricated on the front surface of the epitaxial layer 120 through S20, the signal wiring layer 250 is continuously fabricated on the front surface of the epitaxial layer 120. For convenience of interconnection, the signal wiring layer 250 may be made to cover the metal power rail 180 and the device structure 220, and the signal wiring layer 250 may be made to be respectively metal-connected with the metal power rail 180 and the device structure 220, so that the signal of the device structure 220 can be conveniently led out through the signal wiring layer 250.
And S40, bonding a carrier wafer 260 on the front surface of the signal wiring layer 250.
As shown in fig. 11, in order to facilitate the power wiring layer 320 on the back surface of the epitaxial layer 120, a carrier wafer 260 is bonded to the front surface of the signal wiring layer 250, and the entire device is carried by the carrier wafer 260. As shown in fig. 11, the side indicated by the arrow b is the back side (the same applies to the subsequent drawings).
At least the wafer substrate 110 is thinned to expose the epitaxial layer 120 from the back surface S50.
As shown in fig. 12, after S40, the device is flipped so that the carrier wafer 260 is down and the wafer substrate 110 is up, facilitating the processing of the wafer substrate 110. It should be appreciated that the front and back sides of the epitaxial layer 120 remain consistent with the definition set forth above, i.e., as shown in fig. 12, the upper surface of the epitaxial layer 120 is the back side and the lower surface is the front side, as it is flipped over.
At least the wafer substrate 110 is then thinned, eventually exposing the epitaxial layer 120 from the back side. Specifically, as shown in fig. 11 and 12, the wafer substrate 110 is thinned in the thinning process, and in this process, the epitaxial layer 120 may be used as an etching stop layer, so that the thinning is stopped at the back surface of the epitaxial layer, thereby improving the thinning consistency.
After the wafer substrate is thinned, the epitaxial layer 120 can be thinned continuously from the back surface of the epitaxial layer 120 by a certain thickness, and the thinning can be performed by wet etching, so that the exposed surface of the thinned epitaxial layer 120 is used as the back surface, and the epitaxial layer 120 can be exposed from the back surface of the whole device, and meanwhile, the consistency of the silicon thickness in the thinning process is improved by utilizing the epitaxial layer 120.
And S60, forming a back contact hole 380 correspondingly communicated with the nano-embedded power rail 160 on the back surface of the epitaxial layer 120.
And S70, filling the back surface contact hole 380 with the back surface metal 310 contacted with the front surface metal 181.
And S80, forming a power wiring layer 320 on the back surface of the epitaxial layer 120, wherein the power wiring layer 320 is in metal connection with the back surface metal 310.
As shown in fig. 13 to 18, after the epitaxial layer 120 is exposed from the entire device back surface, a back surface contact hole 380 may be formed at the back surface side of the epitaxial layer 120. It should be understood that the back contact hole 380 may be formed by one or more steps, such as one etching, or may be formed by multiple etching, according to the requirement. The number of the back contact holes 380 and the nano-embedded power supply rails 160 is not limited, and at least one is used, but it is required that a plurality of back contact holes 380 are correspondingly communicated with the same nano-embedded power supply rail 160, and the back contact holes 380 are filled with the back metal 310 in contact with the front metal 181, so that the power supply wiring layer 320 for back power supply is conveniently led out from the back of the whole device by utilizing the back contact holes 380 and the metal columns in the nano-embedded power supply rails 160.
A power wiring layer 320 is then formed on the back side of the epitaxial layer 120, wherein the power wiring layer 320 is metal-connected to the back side metal 310.
In summary, the power supply wiring layer 320 is formed on the back surface of the epitaxial layer 120 by using the metallized nano embedded power supply rail 160 to form the metallized back surface contact hole 380, that is, back surface power supply is realized, so that high voltage drop caused by the arrangement of the conventional power supply line and the signal line on the same side can be effectively relieved, power transmission performance is improved, wiring congestion is reduced, and more importantly, resistance can be further reduced by using the metallized nano embedded power supply rail 160, and design compatibility is improved. In addition, metallized nano-buried power rails 160 may be used to enclose the devices within some cells with sensitive devices to provide physical isolation.
Optionally, forming a metal power rail 180 and a device structure 220 on the front surface of the epitaxial layer 120 at intervals, wherein the metal power rail 180 includes a nano-buried power rail 160 extending from the front surface of the epitaxial layer 120 into the epitaxial layer 120, and the front surface metal 181 filled in the nano-buried power rail 160 includes:
and S21, forming a nano embedded power rail 160 extending into the epitaxial layer 120 on the front surface of the epitaxial layer 120.
And S22, filling the front metal 181 in the nano embedded power rail 160.
As shown in fig. 2 to 4, the nano-buried power rail 160 extending into the epitaxial layer 120 is formed on the front surface of the epitaxial layer 120 by etching, and the bottom wall of the nano-buried power rail 160 is spaced apart from the back surface of the epitaxial layer 120. The nano-buried power rail 160 may be formed by one or more steps, for example, one etching, or multiple etching.
As shown in fig. 5, the nano-buried power rail 160 is filled with a front metal 181.
A device structure 220 is formed on the front surface of the epitaxial layer 120 beside the nano-buried power rail 160.
As shown in fig. 6 to 8, a device structure 220 is formed on the front surface of the epitaxial layer 120, and the device structure 220 is located beside the nano-buried power rail 160 so that the two are spaced apart on the front surface of the epitaxial layer 120. Because the sequence of steps for fabricating the metal power rail 180 is earlier than that of the device structure 220, the method can be used for preferentially forming the embedded metal power rail 180 before the device structure 220 is formed, thereby being beneficial to improving the design flexibility and being compatible with the traditional and advanced processes.
Optionally, forming a nano-buried power rail 160 on the front side of the epitaxial layer 120 extending into the epitaxial layer 120 includes:
S211, forming a first dielectric layer 130 on the front surface of the epitaxial layer 120.
S212, forming a first window 150 exposing the epitaxial layer 120 on the first dielectric layer 130 by photolithography.
S213, etching the epitaxial layer 120 in the first window 150 to form the nano-buried power rail 160 by using the first dielectric layer 130 as a mask layer.
As shown in fig. 2 to 3, a first dielectric layer 130 is deposited on the front surface of the epitaxial layer 120, then a photoresist is coated on the front surface of the first dielectric layer 130, a first window 150 is formed on the first dielectric layer 130 through a photolithography process, and the epitaxial layer 120 under the first dielectric layer 130 is exposed in the first window 150. The number of first windows 150 corresponds one-to-one with the number of nano-buried power rails 160. The epitaxial layer 120 is then etched within the first window 150 using the first dielectric layer 130 having the first window 150 as a mask layer to form the nano-buried power rail 160. The size and depth of the opening of the nano-buried power rail 160 can be set as desired.
It should be understood that when the nano-buried power rail 160 extending into the epitaxial layer 120 is formed on the front surface of the epitaxial layer 120, one or more steps of forming may be selected according to circumstances, the photoresist is preferably used as a barrier etch to form a dielectric hard mask layer on the surface of the silicon substrate, and then the dielectric is used as a hard mask to etch silicon on the substrate portion, so as to form a nano-BPR (nano-buried power rail 160), where the dielectric layer is preferably made of a common semiconductor material such as silicon nitride, silicon oxide, etc.
The first dielectric layer 130 may be a conventional semiconductor material such as a silicon nitride layer, a silicon oxide layer, or a composite film.
Optionally, S22, filling the front metal 181 in the nano-buried power rail 160 includes:
s221, forming a first isolation buffer layer 170 on the bottom wall and the side wall of the nano-buried power rail 160.
A first isolation buffer layer 170 is deposited on the bottom and side walls of the nano-buried power rail 160. As shown in fig. 4, when the first dielectric layer 130 is formed on the front surface of the epitaxial layer 120, the first isolation buffer layer 170 may be located on the bottom and side walls of the nano-buried power rail 160 and the side walls and front surface of the first dielectric layer 130. It will be appreciated that the first dielectric layer 130 is preferably grown using thermal oxygen or atomic layer deposition ALD in view of the step coverage of thin film deposition.
S222, forming a first metal barrier layer on the surface of the first isolation buffer layer 170.
And S223, forming a front metal 181 positioned in the nano-buried power rail 160 on the surface of the first metal barrier layer.
As shown in fig. 5, the nano-buried power rail 160 may be metallized, specifically, a first metal barrier layer is formed on the surface of the first isolation buffer layer 170, where the first metal barrier layer is located in the nano-buried power rail 160, and preferably an ALD metal nitride such as tungsten nitride, titanium nitride, etc. Then, a front metal 181 located in the nano-buried power rail 160 is formed on the surface of the first metal barrier layer, and the front metal 181 must have high temperature stability (600 ℃ to 1000 ℃), preferably using atomic layer deposition ALD or chemical vapor deposition of metal tungsten, ruthenium, etc., so that the diffusion of the front metal 181 can be avoided by using the first metal barrier layer, which is helpful for improving the device performance.
The metal formed outside the nano-buried power rail 160 (e.g., the entire device surface) during the fabrication of the first metal barrier layer and the front metal 181 is then removed, and only the first metal barrier layer and the front metal 181 within the nano-buried power rail 160 remain, preferably using a chemical mechanical mask or dry etching.
Optionally, S23, forming a device structure 220 on the front side of the epitaxial layer 120 beside the nano-buried power rail 160 includes:
and S231, depositing a first insulating layer 190 covering the front metal 181 on the front surface of the first dielectric layer 130.
As shown in fig. 6, a first insulating layer 190 covering the front side metal 181 is deposited on the front side of the first dielectric layer 130, so that the metal power rail 180 can be covered by the first insulating layer 190, thereby avoiding the influence on the process of preparing the device structure 220 later. Typically, the first insulating layer 190 is a nitride film, such as silicon nitride. Here, the thickness of the first insulating layer 190 needs to be determined together in consideration of the subsequent process requirements, and is typically about 1 μm.
And S232, sequentially etching the first insulating layer 190 and the first dielectric layer 130 to form a second window 210 exposing the epitaxial layer 120, wherein the second window 210 is positioned beside the nano-buried power rail 160.
As shown in fig. 7, the first insulating layer 190 and the first dielectric layer 130 are sequentially etched, so that the second window 210 is formed in a region without the metal power rail 180, for example, the second window 210 is located beside the nano-buried power rail 160 (or the metal power rail 180), and a portion of the front surface of the epitaxial layer 120 is exposed through the second window 210. Here, dry or wet etching with a high etching selectivity can be selected.
And S233, forming a device structure 220 on the epitaxial layer 120 in the second window 210.
As shown in fig. 8, a device structure 220 is fabricated on the front side of the epitaxial layer 120 exposed within the second window 210.
Optionally, in S30, forming a signal wiring layer 250 covering the metal power rail 180 and the device structure 220 on the front surface of the epitaxial layer 120, where the signal wiring layer 250 is respectively connected with the metal power rail 180 and the device structure 220 in a metal manner, as shown in fig. 9, forming a second insulating layer 230 on the front surface of the epitaxial layer 120, and then forming a plurality of first contact through holes 240 penetrating through the second insulating layer 230 by etching, where the number of the first contact through holes 240 is plural, and it is possible to reasonably set according to requirements, and connect the metal power rail 180 while connecting the device structure 220 through the metallized first contact through holes 240. Next, as shown in fig. 10, a signal wiring layer 250 is further formed over the second insulating layer 230, and metal lines in the signal wiring layer 250 are connected with the metallized first contact via 240 through metal, so that metal lines in the signal wiring layer 250 can be connected with the metal power rail 180 and the device structure 220 through different first contact vias 240, respectively.
It should be understood that the signal wiring layer 250 may include a plurality of stacked metal wiring layers, and adjacent two metal wiring layers may be separated by a third insulating layer, so that desired wiring can be smoothly achieved.
Optionally, at S40, before the carrier wafer 260 is bonded to the front surface of the signal wiring layer 250, the front surface of the signal wiring layer 250 may be subjected to planarization and edge removal before bonding, and then the carrier wafer 260 is bonded to the front surface of the signal wiring layer 250.
In addition, as shown in fig. 2 to 18, an alignment mark 140 may be formed on the epitaxial layer 120 for alignment of the nano-buried power rail 160, the back contact hole 380, and the 2D process.
In the process of thinning at least the wafer substrate 110 to expose the epitaxial layer 120 from the back surface, the thinning process may be divided into two sections, i.e., rough thinning and fine thinning, specifically including:
S51, rough thinning is performed on the wafer substrate 110 from the back surface of the wafer substrate 110 to form a thinned wafer 111.
As shown in fig. 12, wafer substrate 110 is thinned coarsely using carrier wafer 260 as a support, so that the remaining wafer substrate 110 forms thinned wafer 111. For example, the back surface of the wafer substrate 110 is thinned, and the wafer substrate 110 needs to be thinned from a thickness of about 775um to a thickness of 7-50 um.
After the wafer 111 is thinned, the epitaxial layer 120 is further thinned to a predetermined depth, so that the first isolation buffer layer 170 in the nano-buried power rail 160 is exposed on the back surface of the epitaxial layer 120.
As shown in fig. 13, after the wafer 111 is thinned, the epitaxial layer 120 is thinned continuously to a preset depth, and the implementation manner includes a process of chemical mechanical polishing thinning, wet etching, dry etching, or the like, or a combination of these processes may be implemented. For example, the process of thinning the epitaxial layer 120 is divided into two steps, namely, a first step of primarily thinning the epitaxial layer 120 by combining wet etching with chemical mechanical polishing with a high selectivity, and a second step of thinning is performed when the depth of the first step of thinning reaches a preset depth, namely, the process of thinning the back surface of the epitaxial layer 120 is continuously performed by dry etching with a high selectivity until the first isolation buffer layer 170 in the nano-buried power rail 160 is exposed from the back surface of the epitaxial layer 120.
S60, forming a back contact hole 380 corresponding to the nano-buried power rail 160 on the back surface of the epitaxial layer 120 includes:
and S64, forming a composite dielectric layer on the back surface of the epitaxial layer 120.
As shown in fig. 14, a composite dielectric layer is deposited on the back surface of the thinned epitaxial layer 120, and then the back surface of the composite dielectric layer is planarized, so as to repair the height difference caused by exposing the first isolation buffer layer 170 in the thinning process. As shown in fig. 14, the composite dielectric layer may include a first silicon oxide layer 371, a first silicon nitride layer 372, and a second silicon oxide layer 373 sequentially deposited on the back surface of the epitaxial layer 120.
S65, etching the back surface of the composite dielectric layer to form a first contact hole 381, wherein the first contact hole 381 is terminated in the middle layer in the composite dielectric layer.
As shown in fig. 15, the composite dielectric layer is etched from the back side thereof to form first contact holes 381 extending toward the inside of the composite dielectric layer, and the first contact holes 381 terminate in an intermediate layer in the composite dielectric layer, which is a level other than the outermost side of the composite dielectric layer. For example, as shown in fig. 15, when the composite dielectric layer includes a first silicon oxide layer 371, a first silicon nitride layer 372, and a second silicon oxide layer 373 deposited in this order on the back side of the epitaxial layer 120, the first contact hole 381 terminates in the first silicon nitride layer 372, typically with an etch rate ratio of >5:1 for the second silicon oxide to the first silicon nitride.
And S66, etching the back surface of the composite dielectric layer to form a wiring groove 330 overlapped with the first contact hole 381 in the composite dielectric layer.
And S67, etching the composite dielectric layer and the first isolation buffer layer 170 in the first contact hole 381 in sequence to form a second contact hole 382 in the composite dielectric layer and the first isolation buffer layer 170, wherein the front metal 181 is exposed in the second contact hole 382, and the first contact hole 381 and the second contact hole 382 serve as back contact holes 380.
As shown in fig. 16, the composite dielectric layer is etched from the back side thereof, thereby forming a wiring trench 330 in the composite dielectric layer, the wiring trench 330 overlapping the first contact hole 381. And then continuing to etch the first silicon nitride layer 372 and the first silicon oxide layer 371 in the composite dielectric layer and the first isolation buffer layer 170, so as to form a second contact hole 382 in the first silicon nitride layer 372, the first silicon oxide layer 371 and the first isolation buffer layer 170, so that the front metal 181 is conveniently exposed in the second contact hole 382, and the first contact hole 381 and the second contact hole 382 are communicated as a back contact hole 380 positioned on the back side of the epitaxial layer 120.
Filling the back contact hole 380 with the back metal 310 in contact with the front metal 181 includes forming a second metal barrier layer and the back metal 310 by a damascene process in the wiring trench 330 and the back contact hole 380 as shown in fig. 17. The metallization process is divided into a second metal barrier layer deposition filling the backside metal 310. The metallization process includes electroplating, chemical mechanical polishing and other processes. The back metal 310 includes a metal block 350 located within the wiring trench 330.
A fourth insulating layer 360 is then formed on the back of the composite dielectric layer. As shown in fig. 18, the power supply wiring layer 320 is continuously formed on the fourth insulating layer 360, the nano-buried power supply rail 160 is connected to the back surface of the epitaxial layer 120 by using the back surface contact hole 380, the back surface power supply wiring layer 320 is continuously formed, and then the power supply wiring layer 320 is metal-connected to the back surface metal 310. The power wiring layer 320 may include a plurality of metal lines which may be separated from each other by a third insulating layer, thereby enabling desired wiring to be smoothly achieved.
Alternatively, as shown in fig. 19, the nano-buried power rail 160 is a circular groove, as shown in fig. 20, the nano-buried power rail 160 is a long-strip groove (or plate-like shape), as shown in fig. 21, and the nano-buried power rail 160 is a circular groove. When the number of nano-buried power rails 160 is plural, the plurality of nano-buried power rails 160 may be one or a combination of several of a circular groove, an elongated groove, and an annular groove. Alternatively, the nano-embedded power rail 160 may be formed by splicing at least two elongated grooves at an included angle.
Alternatively, as shown in fig. 22, the number of the back contact holes 380 is plural, and portions of the back contact holes 380 are correspondingly connected to the same nano-buried power rail 160.
In another aspect of the embodiments of the present application, a backside-powered interconnect structure is provided, and the backside-powered interconnect structure is prepared by any one of the methods for preparing a backside-powered interconnect structure described above. The back side power based interconnect structure may be the structure shown in fig. 18.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (11)
1. A method for preparing an interconnect structure based on backside power supply, the method comprising:
selecting a wafer substrate with an epitaxial layer with a certain thickness;
Forming metal power supply rails and device structures which are distributed at intervals on the front surface of the epitaxial layer, wherein the metal power supply rails comprise nano embedded power supply rails which extend from the front surface of the epitaxial layer to the inside of the epitaxial layer and front surface metal filled in the nano embedded power supply rails;
Forming a signal wiring layer covering the metal power rail and the device structure on the front surface of the epitaxial layer, wherein the signal wiring layer is respectively connected with the metal power rail and the device structure in a metal manner;
bonding a carrier wafer on the front surface of the signal wiring layer;
Thinning at least the wafer substrate to expose the epitaxial layer from the back surface;
Forming a back contact hole correspondingly communicated with the nano embedded power rail on the back of the epitaxial layer;
filling back metal in contact with the front metal in the back contact hole;
and forming a power wiring layer on the back surface of the epitaxial layer, wherein the power wiring layer is connected with the back surface metal.
2. The method of claim 1, wherein the nano-embedded power rail is any one of an elongated groove, an annular groove, and a circular groove.
3. The method of claim 1, wherein the number of back contact holes is a plurality, and at least two back contact holes in the plurality of back contact holes are in corresponding communication with the same nano-buried power rail.
4. The method of claim 1, wherein forming the spaced apart metal power rails and device structures on the front side of the epitaxial layer comprises:
Forming a nano embedded power rail extending into the epitaxial layer on the front surface of the epitaxial layer;
Filling front metal in the nano embedded power rail;
and a device structure positioned beside the nano-embedded power supply rail is formed on the front surface of the epitaxial layer.
5. The method of claim 4, wherein forming a nano-buried power rail on the front side of the epitaxial layer that extends into the epitaxial layer comprises:
forming a first dielectric layer on the front surface of the epitaxial layer;
forming a first window exposing the epitaxial layer on the first dielectric layer through photoetching;
and etching the epitaxial layer in the first window by using the first dielectric layer as a mask layer to form the nano embedded power rail.
6. The method of claim 4, wherein the filling the nano-buried power rail with a front metal comprises:
forming a first isolation buffer layer on the bottom wall and the side wall of the nano embedded power rail;
forming a first metal barrier layer on the surface of the first isolation buffer layer;
And forming the front metal positioned in the nano embedded power rail on the surface of the first metal barrier layer.
7. The method of claim 5, wherein forming a device structure on the front side of the epitaxial layer that is beside the nano-buried power rail comprises:
depositing a first insulating layer covering the front metal on the front side of the first dielectric layer;
Sequentially etching the first insulating layer and the first dielectric layer to form a second window exposing the epitaxial layer, wherein the second window is positioned at the side of the nano embedded power rail;
and forming the device structure on the epitaxial layer in the second window.
8. The method of claim 6, wherein thinning at least the wafer substrate to expose the epitaxial layer from the back side comprises:
coarsely thinning the wafer substrate from the back surface of the wafer substrate to form a thinned wafer;
and after the thinning wafer is thinned, continuing to carry out the thinning of the preset depth on the epitaxial layer so as to expose the first isolation buffer layer in the nano embedded power rail on the back surface of the epitaxial layer.
9. The method of claim 8, wherein forming a back contact hole on the back surface of the epitaxial layer in corresponding communication with the nano-buried power rail comprises:
Forming a composite dielectric layer on the back of the epitaxial layer;
Etching the back surface of the composite dielectric layer to form a first contact hole, wherein the first contact hole is terminated at an intermediate layer in the composite dielectric layer;
etching the back surface of the composite dielectric layer to form a wiring groove overlapped with the first contact hole in the composite dielectric layer;
And etching the composite dielectric layer and the first isolation buffer layer in the first contact hole in sequence to form a second contact hole in the composite dielectric layer and the first isolation buffer layer, wherein the front gold is exposed in the second contact hole, and the first contact hole and the second contact hole are used as back contact holes.
10. The method of claim 9, wherein filling the backside contact hole with backside metal in contact with the front side metal comprises:
and forming a second metal barrier layer and the back metal in the wiring groove and the back contact hole through a Damascus process.
11. Backside-powered interconnect structure, characterized in that it is manufactured using the backside-powered interconnect structure manufacturing method according to any of claims 1 to 10.
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