CN119207526A

CN119207526A - On-chip verification circuit, memory and storage device

Info

Publication number: CN119207526A
Application number: CN202310717517.1A
Authority: CN
Inventors: 韩钰璋; 李亮; 史丹丹
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-06-15
Filing date: 2023-06-15
Publication date: 2024-12-27

Abstract

The application provides an on-chip check circuit, a memory and a storage device, wherein the on-chip check circuit comprises an encoder and a first error correction circuit, the encoder generates a first check code according to written data and bit groups represented by an error correction matrix in a writing stage, the first check code is written into a storage array, generates a second check code according to read data and bit groups represented by the error correction matrix in a reading stage, and generates an error correction code based on the read first check code and the generated second check code, the first error correction circuit receives the read data and performs single-bit error correction on the read data according to the error correction code output by the encoder, and then outputs the first error correction data, wherein the error correction matrix comprises error correction codes corresponding to each bit in each beat, and the error correction matrix meets the condition that the exclusive or result of error correction codes corresponding to any plurality of bits is not identical to error correction codes corresponding to any bit in the same beat. The scheme can realize data verification.

Description

On-chip verification circuit, memory and storage device

Technical Field

The present application relates to memory technologies, and in particular, to an on-chip verification circuit, a memory, and a storage device.

Background

With the development of memory technology, memories are widely used in various fields, such as dynamic random access memories (Dynamic Random Access Memory, abbreviated as DRAMs).

In practical applications, on-chip error checking and correction (On-Die ECC) is introduced to ensure data reliability. In particular, on-chip error checking and correction may support correction of single-bit errors, but may be miscorrected based on-chip error checking and correction for multi-bit errors. The error-corrected data is transmitted to the outside for further verification, for example, error checking and correction (Rank-level ECC) at the memory bank level, resulting in further aggravation of the bit error condition.

Disclosure of Invention

The embodiment of the application provides an on-chip checking circuit, a memory and a storage device.

According to some embodiments, the first aspect of the application provides an on-chip check circuit, which is applied to a memory, and comprises an encoder, a first error correction circuit and a first error correction circuit, wherein the encoder is connected with a storage array of the memory and is used for generating a first check code according to a bit packet represented by write data and an error correction matrix in a writing stage and writing the first check code into the storage array, the second check code is generated according to a bit packet represented by read data and the error correction matrix in a reading stage and is used for generating an error correction code based on the read first check code and the second check code, the first error correction circuit is connected with the encoder and is used for receiving the read data and outputting the first error correction data after single-bit error correction is performed on the read data according to the error correction code output by the encoder, and the error correction matrix comprises error correction codes corresponding to each bit in each beat, and the error correction matrix meets the condition that the exclusive OR result of the error correction codes corresponding to any plurality of bits is not identical to the error correction codes corresponding to any bit in the same beat.

In some embodiments, the error correction matrix has an exclusive or result of an error correction code corresponding to any of a plurality of bits belonging to a same beat that is not the same as an error correction code corresponding to any of the plurality of bits in the error correction matrix, and an exclusive or result of an error correction code corresponding to any of a plurality of bits belonging to a different beat that is not the same as an error correction code corresponding to any of the plurality of bits in the same beat.

In some embodiments, the on-chip verification circuitry further comprises a data selector, a first input of the data selector receiving the write data, a second input of the data selector receiving the read data, an output of the data selector coupled to the input of the encoder and the memory array, the data selector being configured to output the write data during the write phase and to output the read data during the read phase.

In some embodiments, the first error correction circuit comprises a first decoder and a first correction circuit, wherein the input end of the first decoder is connected with the encoder, the first decoder is used for receiving an error correction code output by the encoder, determining a first target position to be flipped based on the error correction code and the error correction matrix, and outputting a first error correction instruction pointing to the first target position, the first correction circuit is connected with the output end of the first decoder, and is used for receiving read data and carrying out data flipping on bits under the first target position according to the first error correction instruction to obtain first error correction data.

In some embodiments, the on-chip verification circuitry further comprises a plurality of buffer circuits including a first buffer circuit having an input for receiving the write data, an output of the first buffer circuit being coupled to a first input of the data selector for buffering the received write data, a second buffer circuit having an input coupled to an output of the data selector, an output of the second buffer circuit being coupled to the memory array for buffering the write data output by the data selector during a write phase, a third buffer circuit having an input coupled to the encoder, an output of the third buffer circuit being coupled to the memory array for buffering the first check code output by the encoder during a write phase, a fourth buffer circuit having an output coupled to the encoder for buffering the first check code read from the memory array during a read phase, a fifth buffer circuit having an input coupled to the memory array for buffering the write data output by the data selector, an output of the fifth buffer circuit being coupled to the output of the first buffer circuit during a read phase, and an output of the error correction circuit from the sixth buffer circuit, and an output of the error correction circuit being coupled to the output of the first buffer circuit during a read phase.

In some embodiments, the buffer circuit includes an even number of inverters in series.

In some embodiments, the exclusive OR result of the error correction code corresponding to any plurality of bits is not the same as the error correction code corresponding to any one of the plurality of bits in the same beat, including that the exclusive OR result of the error correction code corresponding to any two bits in the same beat is not the same as the error correction code corresponding to any one of the two bits in the same beat.

In some embodiments, the error correction matrix has different exclusive or results for error correction codes corresponding to different bits belonging to the same beat.

In some embodiments, the on-chip verification circuit further comprises a second error correction circuit, wherein the second error correction circuit is connected with the encoder, receives a multi-bit error correction instruction, reads data or first error correction data, and is used for responding to the multi-bit error correction instruction pointing to a target beat number, performing multi-bit error correction on the received data according to an error correction code output by the encoder, and outputting the second error correction data, wherein the multi-bit error correction instruction pointing to the target beat number indicates that the read data generates multi-bit errors in the same beat number, and the multi-bit errors occur in the target beat number.

In some embodiments, the second error correction circuit comprises a second decoder and a second correction circuit, wherein the input end of the second decoder is connected with the encoder, the second decoder receives error correction codes and multi-bit error correction instructions and is used for responding to the multi-bit error correction instructions pointing to target beats, determining a second target position to be flipped based on the target beats pointed by the multi-bit error correction instructions, the error correction codes and the error correction matrix and outputting the second error correction instructions pointing to the second target position, the second correction circuit is connected with the output end of the second decoder and is used for receiving read data or first error correction data and carrying out data error correction on bits in the second target position according to the second error correction instructions to obtain second error correction data.

In some embodiments, the second correction circuit is connected to a data input of the first error correction circuit for receiving the read data, or the second correction circuit is connected to an output of the first error correction circuit.

According to some embodiments, a second aspect of the application provides a memory comprising a memory array, and an on-chip verification circuit as in any preceding claim.

According to some embodiments, a third aspect of the present application provides a memory device comprising an off-chip verification circuit and at least one memory as in any one of the preceding claims, the off-chip verification circuit being connected to the at least one memory for verifying each beat of data in the first error correction data output by the at least one memory during a read phase, the verification comprising single bit error correction and multi-bit detection.

In some embodiments, the off-chip verification circuit comprises an indication circuit and an indication circuit, wherein the indication circuit is used for sending a multi-bit error correction instruction pointing to a target beat number to all memories if multi-bit errors exist under the same beat of data.

In some embodiments, the off-chip verification circuit further comprises a processing circuit, wherein the processing circuit is used for performing first data integration on first error correction data output by different memories and performing data verification on integrated data, outputting off-chip verified data if no data errors exist or correction can be performed, performing error data replacement on the integrated data based on the second error correction data and performing data verification again after the second error correction data is received if the second error correction data is required, and outputting off-chip verified data if no data errors exist or correction can be performed.

The on-chip checking circuit, the memory and the storage device provided by the embodiment of the application comprise an encoder and a first error correction circuit, wherein the encoder is responsible for generating check codes of writing and reading stages and obtaining error correction codes according to the check codes of the two stages, and the first error correction circuit performs single-bit error correction on data read in the reading stage according to the error correction codes. The check code in the scheme is generated by the encoder based on the bit grouping represented by the error correction matrix, the error correction matrix comprises error correction codes corresponding to each bit in each beat, and the condition that the bits corresponding to the exclusive OR result of any plurality of error correction codes are not located in the same beat with any bit of the plurality of bits is satisfied, so even if error correction codes which are incorrectly corrected are generated due to the existence of multi-bit errors, the error correction codes which are incorrectly corrected are not located in the same beat with the bit which is incorrectly corrected, and new multi-bit errors in the same beat are not caused, thereby avoiding further expansion of data errors, realizing data verification, and effectively improving the reliability of verification.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the embodiments of the application.

FIG. 1 is a diagram showing an example architecture of a memory according to an embodiment;

FIG. 2 is a diagram showing an example of the structure of a memory cell according to an embodiment;

FIG. 3 is a schematic diagram of an exemplary on-chip verification flow;

FIG. 4 is a schematic diagram of an exemplary architecture;

FIG. 5 is a data structure diagram of an example;

FIG. 6 is a schematic diagram of an exemplary on-chip verification circuit;

FIG. 7 is an exemplary single bit error scenario;

FIG. 8 is an exemplary double bit error scenario;

FIG. 9 is a data structure diagram of an example;

FIG. 10 is a schematic diagram of an exemplary on-chip verification circuit;

FIG. 11 is a schematic diagram of an exemplary on-chip verification circuit;

FIG. 12 is a schematic diagram of an exemplary on-chip verification circuit;

FIG. 13 is a schematic diagram of an exemplary buffer circuit;

FIG. 14 is a schematic diagram of an exemplary on-chip verification circuit;

FIG. 15 is a schematic diagram of an exemplary on-chip verification circuit;

FIG. 16 is a diagram showing an example of the structure of a memory;

fig. 17 is a diagram showing a structural example of an exemplary memory device.

Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application.

The terms "comprising" and "having" in the present application are used in an open-ended fashion, and mean that additional elements/components/etc. may be present in addition to the listed elements/components/etc., and the terms "first" and "second" etc. are used merely as labels or differences, and are not intended to limit the order or quantity of their objects. Furthermore, the various elements and regions in the figures are only schematically illustrated and are therefore not limited to the dimensions or distances illustrated in the figures.

The technical scheme is described in detail below with specific examples. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

The technical scheme is described in detail below with specific examples. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present disclosure will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing an example of a memory architecture according to an embodiment, and as shown in FIG. 1, a DRAM is taken as an example, and includes a data input/output buffer, a row decoder, a column decoder, a sense amplifier, and a memory array. Wherein the data input/output buffers belong to a peripheral area circuit, and the sense amplifier, the row decoder, the column decoder, and the memory array belong to an array area circuit. The memory array is mainly composed of word lines, bit lines and memory cells. Word lines in the memory array extend in a row direction, bit lines in the memory array extend in a column direction, and intersections of the word lines and the bit lines are memory cells of the memory array.

Wherein each memory cell is for storing one bit (bit) of data. As shown in fig. 2, fig. 2 is a schematic diagram showing a structure example of a memory cell according to an embodiment, and the memory cell mainly includes a transistor switch M and a capacitor C. The capacitor is used for storing data, and the transistor switch is used for being turned off or turned on according to the selected state.

A certain memory cell may be activated by controlling the word line and the bit line to enable access to the memory cell. In combination with the reading scenario, when the data in the memory cell needs to be read, the word line of the row where the memory cell is located can be selected through the row decoder, correspondingly, the transistor M in the illustration is turned on, and the state on the capacitor C at the moment can be perceived through the sense amplification of the bit line signal. For example, if the bit data stored in the memory cell is 1, then transistor M will read 1 from the bit line of the memory cell after being turned on, and vice versa. In addition, a write scenario is taken as an example when bit data needs to be written to a certain memory location, such as writing 1. The word line of the row in which the memory cell is located can be selected by a row decoder, and the transistor M in the corresponding figure is turned on, and the capacitor C is charged, i.e. a 1 is written to the memory cell, by setting the logic level of the bit line to 1. Conversely, if a 0 is to be written, then the logic level of the bit line is set to 0, causing the capacitor C to discharge, i.e., write a 0 to the memory cell.

In practical applications, considering the influence of various factors, such as process deviation, ionizing radiation, temperature, data loss, etc., there may be cases where the actually read data is inconsistent with the data at the time of writing, resulting in data errors. Therefore, in order to ensure the accuracy of the data, on-chip error checking and correcting (On-Die ECC) is introduced, and based On the On-chip error checking and correcting, the memory can check the data of the memory to realize the correction of single-bit errors. Taking DDR5 as an example, a double rate synchronous dynamic random access memory (DDR) corresponds to generating 8-bit check bits per 128-bit data. As an example, fig. 3 is a schematic diagram of an exemplary on-chip verification flow, and as shown in fig. 3, the on-chip verification flow generally includes that when data is written, a bit verifier generates 128-bit data (write data) to be written into a memory according to need, and stores the write data and the verification data together in the memory, when data is read, 128-bit data (read data) and 8-bit first verification data are read from the memory, an error correction code generator generates 8-bit second verification data based on the read 128-bit data, and compares the generated second verification data with the first verification data read from the memory to generate an error correction code. The error correction code can determine whether the read data has data errors, for example, if the error correction code is all 0 s, the error is not generated, if the error correction code is not 0 s, the error correction code decoder can decode the error correction code to locate the data error position, the error corrector can execute inversion correction on the bit at the data error position, for example, 0 s is inverted to 1 s or 1 s is inverted to 0 s, and after the data error correction is realized, the 128-bit data after the error correction is output.

In an example technique, an on-chip checksum off-chip check is provided for checking of data, e.g., bank-level error checking and correction (Rank-level ECC). In connection with practical applications, the whole DRAM system may be divided into the following layers, namely, channels (channels), dual in-line memory modules (dual in-line memory modules, abbreviated as DIMMs), banks (RANK), chips (chips), memory blocks (banks), sub-arrays (Sub-arrays), partial Sub-arrays (MATs), rows (rows), and cells (cells). The banks refer to chips that receive the same chip select (CHIP SELECT, abbreviated as CS) signal and can be accessed through the same memory channel, and all chips in one bank share the address lines, control lines and data lines provided by the same memory channel. The memory controller can perform read-write operation on all chips under the same library. Specifically, the on-chip verification object is data in a storage array of each chip, and is output by taking each beat as a unit when outputting the data, and the off-chip verification object is data of each beat output by all chips under a library. As an example, fig. 4 is a schematic diagram of an architecture of an example, fig. 5 is a data structure diagram of an example, as shown in fig. 4, a bank and a chip (a chip not filled with hatching in the figure) for storing check data are disposed on a certain dual in-line memory module, the bank includes eight memory chips (a chip filled with hatching in fig. 4), and assuming that each memory chip outputs 8 bits per beat and outputs 16 beats in total, the bank includes DRAMs 0 to 7, and the data stored in each memory chip is d0 to d127, and 128 bits in total, and each memory chip has 8 data ports, DQ0 to DQ7, as shown in fig. 5. The 128 bits of data are output in 16 beats, each beat outputting 8 bits of data through the data ports DQ 0-DQ 7, for example, for any memory chip, the memory chip outputs 8 bits through the data ports DQ 0-DQ 7 at beat 1, d 0-d 7, outputs 8 bits through the data ports DQ 0-DQ 7 at beat 2, d 8-d 15, and so on, until beat 16 outputs d 120-d 127. In combination with the above explanation, the on-chip verification is that each memory chip performs verification on 128 bits stored by itself, and the off-chip verification is that the eight memory chips perform verification on RANK level on data output by each beat, for example, each memory chip outputs 8 bits per beat, then each memory chip outputs 64 bits per beat, and the off-chip verification performs verification on 64 bits per beat. The current on-chip checking technology can realize the correction of single-bit errors, and the off-chip checking technology can realize the correction of single-bit errors and the detection of multi-bit (such as double-bit) errors.

In practical application, a multi-bit error may occur in a certain memory chip, and for multi-bit error on-chip verification, error correction may occur, and data after error correction is transmitted to the outside of the memory chip for off-chip verification, and when the newly generated error correction bit performs off-chip verification, more error correction may further occur, so that the error condition is aggravated. To avoid the consequences of the above-described data errors being amplified, aspects of embodiments of the present application relate to the above-described considerations. The following describes an example of a solution in connection with some embodiments.

Example 1

FIG. 6 is a schematic diagram of an exemplary on-chip verification circuit, and as shown in FIG. 6, the on-chip verification circuit 31 includes an encoder 11 and a first error correction circuit 12;

An encoder 11 connected to the memory array 13 of the memory for generating a first check code from the Data1 written and the bit packets characterized by the error correction matrix and writing the first check code into the memory array 13 during a write phase, and for generating a second check code from the Data2 read and the bit packets characterized by the error correction matrix during a read phase and generating an error correction code Syn based on the first check code read and the second check code read;

The first error correction circuit 12 is connected to the encoder 11, receives the readout Data2, performs single-bit error correction on the readout Data2 according to the error correction code output from the encoder 11, and outputs the first error correction Data Correct Data1.

The error correction matrix comprises error correction codes corresponding to each bit in each beat, and the error correction matrix meets the condition that the exclusive OR result of the error correction codes corresponding to any plurality of bits is not identical to the error correction codes corresponding to any bit in the same beat with one of the plurality of bits. In practical applications, the circuit provided in this embodiment may be applied to various memories, and as an example, may be applied to a double rate synchronous dynamic random access memory (DDR) or the like.

It should be noted that, in the present application, it is required to understand that the writing of the first check bit into the memory array is performed according to the actual design of the chip, in some embodiments, the target memory areas of the writing data and the check code are not different, that is, each area of the single DRAM can be used to store the writing data and the check code, and in other embodiments, the target memory areas of the writing data and the check code are different and are stored in different positions of the DRAM. The writing area of the check code is not limited in any way, and the final storage locations of the written data and the check code are collectively referred to as a storage array.

Specifically, a single-bit error refers to an error occurring in data having one bit in the data to be verified. If the data is in error, the data written originally and the data read out are inconsistent, for example, a certain bit in the data written originally is 1 or 0, but in the memory array of the memory, the stored bit is turned over to 0 or 1 due to the influence of some factors, and then the bit read out later will be in error. Fig. 7 is an exemplary single-bit error situation, as shown in fig. 7, taking the data to be checked as a check object of on-chip check, for example, 128 bits stored in a certain memory, and assuming that the bits filled with shadows are the bits with errors, as shown in the drawing, there is one bit d 0in the 128 bits stored in the memory, that is, a single-bit error occurs. In practical application, on-chip check and off-chip check can realize single-bit error correction, namely, aiming at the situation of single-bit error, the bit with the error can be accurately positioned and the data of the bit can be turned over, so that the accurate error correction is realized. For the example shown in fig. 7, the error of bit d0 can be corrected by on-chip verification, resulting in accurate 128 bits.

In practice, multi-bit errors may occur in addition to the single-bit error scenario described above. Specifically, a multi-bit error is an error occurring in data having at least two bits. Still referring to the drawings, fig. 8 is an exemplary double-bit error situation, and as shown in fig. 8, on-chip verification is still taken as an example, where two bits, namely, bit d0 and bit d17, out of the 128 bits shown in the drawing have errors, that is, double-bit errors occur. For multi-bit errors, the current on-chip checksum off-chip verification can realize multi-bit error detection, but cannot realize multi-bit error correction, because although whether a plurality of bits in data to be verified are in error or not can be detected through verification, the current verification cannot determine which specific positions of the bits are in error, so that effective error correction cannot be performed. In contrast, taking on-chip verification as an example, still referring to the example of fig. 8, assuming that data error correction is performed based on-chip verification, if the error correction code generated based on multi-bit error is the same as the error correction code corresponding to a certain bit, a new bit may be caused to be in error instead, as shown in fig. 8, because the error correction code generated by multi-bit error is the same as the error correction code corresponding to d6, a new bit error is generated after on-chip verification is performed, that is, d6 is miscorrected. It can be found that the new error bit d6 caused by the error correction is located in the same beat as the original error bit d 0. In connection with the above-described check flow regarding on-chip check and off-chip check, it is known that each beat of data of all memories under one bank will be subjected to off-chip check, and in connection with this example, the first beat of data output from this memory shown in fig. 8 will have multi-bit errors (d 6 and d 0), along with the first beat of data (not shown in the figure) output from other memories in the same bank, are transferred to an off-chip check circuit for off-chip check. It is known that, in the first beat of data output from each memory, at least two bits of the check object of the off-chip check shown in fig. 8 are in error, i.e. there are multiple bit errors. In combination with the foregoing, the existing off-chip verification technology cannot effectively correct the multi-bit error, and on the contrary, due to the multi-bit error, new bit errors may be further generated in the data obtained after the off-chip verification is performed, so that the data errors are amplified layer by layer in each level of on-chip and off-chip verification.

In order to avoid the above situation, the present embodiment designs a grouping manner of bit grouping, where the grouping manner is defined by an error correction matrix, and further, by adding constraint to the error correction matrix, constraint adjustment is performed on the error correction position that may be caused during data verification, so as to avoid the situation that the error may be further amplified in the following process. The data verification principle is exemplified in combination with the data verification principle, wherein data to be verified is grouped, each data to be verified is divided into one or more groups, each group comprises and only comprises one verification bit, the grouping rules of different data to be verified are different, and therefore error correction codes which are different from each other and correspond to the grouping rules are obtained, namely whether each bit of the error correction code represents the error correction code is divided into the corresponding group or not. In essence, the error correction bits of the error correction code and the check bits of the check code are corresponding, i.e. each error correction bit is xored with the corresponding check bit in the written and read check code. Therefore, the check code corresponds to the bit packet being completed. Specifically, after a certain bit of data is divided into a group corresponding to a certain check bit, whether the bit is in error affects the value of the check bit, and further affects the value of an error correction code generated based on the check code, for example, if the generated bit is in error, the value of the check bit changes compared with the value of the check bit when writing, and then based on the check code and the check code generated when writing, the corresponding bit of the error correction code is obtained to be 1. This is because the error correction code is typically obtained by exclusive-or processing of a check code generated at the time of writing and a check code generated at the time of reading. Based on the defined grouping mode, check codes are respectively generated for the data during writing and reading, the check codes during writing and the check codes during reading are obtained, and then, according to the exclusive or result of the two check codes, namely the error correction code, which bit is in error is determined, so that single-bit error correction is realized.

The error correction matrix of this embodiment defines an error correction code corresponding to each bit per beat, i.e. the design of the bit packet is substantially completed. By way of example, table 1 is an exemplary error correction matrix, as shown in Table 1, DQ 0-DQ 7 represent eight data ports of a memory, 0-15 in the second row represent 16 beats, and pc 0-pc 7 represent 8 bits of the error correction code, respectively. It should be noted that, here, the memory is exemplified by having eight data ports, i.e., outputting 8 bits of data per beat, outputting 16 beats in total, and the data length of the error correction code is 8 bits, and it is understood that the practical application is not limited to the case shown in the table.

TABLE 1

In connection with the data structure shown in the foregoing, for example, the 0 th column under DQ0 indicates that a bit outputted from a certain memory through the data port DQ0 at 1 st beat, that is, d0 in the whole 128 bits, the corresponding error correction code corresponding to d0 is pc 0-pc 7 under the column, that is, 00000101, and so on, see the 1 st column under DQ0, the error correction code corresponding to d8 is 11110101, and the error correction code corresponding to d3 is 01100101, see the 0 th column under DQ 3. Specifically, the error correction matrix of this embodiment includes an error correction code corresponding to each bit in each beat, and reflects a check code affected when a single bit error occurs in a certain bit. For example, referring to table 1, it is known that the error correction code corresponding to d0 is 00000101, that is, the grouping condition is that d0 is divided into the groups corresponding to the check codes p5 and p 7. That is, the error correction matrix actually defines the bit grouping situation in the data check. It should be noted that, in practical application, in order to ensure that the data is accurately verified based on the check code, the check code is verified in addition to the data to be verified, that is, the error correction code of the check code is obtained, so as to avoid inaccurate data verification based on the check code due to errors of the check code, that is, table 1 shows at least 128bit data+8 bit check code, and 136bit corresponding error correction codes.

For example, in connection with the case of a single bit error, assuming that the encoder 11 generates a first check code based on the written data and the bit packet characterized by the above-described error correction matrix, and obtains a second check code based on the read data and the above-described error correction matrix, when a single bit error occurs, such as d0 being an error bit, the error correction code Syn generated by the encoder 11 from the first check code and the second check code will be 00000101, and accordingly, the first error correction circuit 12 can determine the position d0 based on the above-described error correction matrix from the error correction code output by the encoder 11, thereby performing data inversion on the data under d 0.

The above described principle of error correction matrix is exemplified in the case of single bit errors. In combination with the above, in order to avoid the problem that the error amplification may be caused when the multiple bits are wrong, the error correction matrix in the present solution satisfies the condition that the exclusive or result of the error correction code corresponding to any of the multiple bits is not the same as the error correction code corresponding to any bit in the same beat as one of the multiple bits. In practical use, error correction occurs because the error correction bits of the error correction code are affected by a plurality of bits of the error, and an error correction code corresponding to a certain bit is generated. For example, when an error occurs in both the bit corresponding to column 2 (data output by the memory through DQ0 in the third beat, i.e., d 16) and the bit corresponding to column 3 (data output by the memory through DQ0 in the fourth beat, i.e., d 24) at DQ0 in combination with the foregoing table 1 example, the error correction bits pc3 and pc7 are affected twice, resulting in an erroneous error correction code. Specifically, the check code in this embodiment refers to data that is generated based on the data to be checked, and the type corresponding to the data to be checked is the check code, and there are various situations as to whether the check code itself is accurate. For example, when a multi-bit error occurs, the generated check code may be erroneous, and thus the subsequently generated error correction code may also be erroneous, i.e., the error correction code does not point to the bit where the error actually occurred, which may result in erroneous correction.

In this embodiment, the error correction matrix satisfies the exclusive-or result of the error correction code corresponding to any of the plurality of bits, and is not identical to the error correction code corresponding to any of the plurality of bits located in the same beat. By this design, it is possible to make the generated error correction code not point to the bit located in the same beat as the multi-bit where the error occurs when the multi-bit error occurs, so as to avoid the error being amplified. For ease of understanding, fig. 9 is a data structure diagram of an example, as shown in fig. 9, and still in combination with the foregoing case where 128 bits are output in 16 beats from a single memory, it is assumed that a multi-bit error occurs, as shown in the figure, and still taking an error occurring in a bit d0 and a bit d17 as an example, based on an error correction matrix satisfying the conditions set in this embodiment, the bits corresponding to the obtained error correction code will not be the same beat data of d0 and d 17. Based on this, it is only required to satisfy that the generated error correction code does not point to any bit of 128 bits, that is, error correction bits are not generated, or as shown in fig. 9, based on the bit packet represented by the error correction matrix, the exclusive or result of the error correction code corresponding to d0 and d17 is designed to be an error correction code corresponding to d15 which is not in the same beat as d0 or d17, that is, the generated error correction code is satisfied, even if the generated error correction code points to one bit of 128 bits, but as long as the pointed error correction bit and multiple bits in which errors originally occur are not in the same beat, when the off-chip verification is performed, since the error in the beat of data in which the error correction bit is located is a single-bit error, the error correction of the error correction bits can be realized through the off-chip verification. The number of "multi-bit" may be various, such as a double-bit error, a three-bit error, a four-bit error, or even an eight-bit full error. Accordingly, in one example, the exclusive OR result of the error correction code corresponding to any plurality of bits is not the same as the error correction code corresponding to any one of the plurality of bits located in the same beat, including the exclusive OR result of the error correction code corresponding to any two of the plurality of bits in the same beat is not the same as the error correction code corresponding to any one of the plurality of bits located in the same beat.

In practical applications, there are various specific ways in which the error correction matrix satisfies the above conditions. In one example, the error correction matrix has an exclusive OR result of an error correction code corresponding to any of a plurality of bits belonging to the same beat that is not the same as an error correction code corresponding to any of the plurality of bits in the error correction matrix, and an exclusive OR result of an error correction code corresponding to any of a plurality of bits belonging to a different beat that is not the same as an error correction code corresponding to any of the plurality of bits in the same beat. For example, it is understood that the value of each error correction bit of the 8-bit error correction code may be 0 or 1, so that the value of the 8-bit error correction code is 8 times 2, i.e., 256 cases. In combination with the foregoing example, assuming that the amount of data to be checked in the memory is 128 bits, only 128 error correction codes corresponding to each bit in each beat of the error correction matrix need to be selected in 256 cases, and in practical application, error correction codes of the check code may also be considered, so that 8 error correction codes used for designing the check code need to be selected, that is, the error correction matrix needs to be designed in 136 cases in total. Based on this example, it is known that 120 cases remain unused, so as an example, an exclusive or result of an error correction code corresponding to an arbitrary plurality of bits in an error correction matrix may be designed as a value case among the 120 cases. Accordingly, when a multi-bit error occurs, the error correction code generated by the encoder 11 will not be the error correction code corresponding to any single bit in the error correction matrix, and the first error correction circuit 12 will not perform data inversion on the data in 128 bits based on the error correction code, thereby avoiding erroneous correction bits. By the scheme, new check bits are not required to be added, and data errors can be prevented from being amplified when multi-bit errors occur.

Specifically, the encoder 11 receives written data at the time of writing and read data at the time of reading, obtains a check code at the writing stage and a check code at the reading stage in a grouping manner characterized by combining an error correction matrix, and obtains an error correction code based on both. The data received at the different stages is different for the encoder 11. Therefore, in order to ensure reliable operation of the encoder, in one example, FIG. 10 is a schematic diagram of an exemplary on-chip verification circuit, as shown in FIG. 10, the on-chip verification circuit 31 further includes a data selector 14;

A first input terminal of the Data selector 14 receives the write Data1, a second input terminal of the Data selector 14 receives the read Data2, and an output terminal of the Data selector 14 is connected to an input terminal of the encoder 11 and the memory array 13;

the Data selector 14 is configured to output the write Data1 in the write phase and output the read Data2 in the read phase.

Specifically, the data selector 14 provides the corresponding data to the encoder according to the current stage. For example, during a write phase, the data selector 14 may select to output data received at the first input in response to a select signal, and during a read phase, the data selector 14 may select to output data received at the second input in response to a select signal. The selection signal may be generated by an associated circuit or component in the memory, and the data selector may be instructed to output data at the first input terminal or the second input terminal by designing the selection signal to be in different level states. In practice, the specific implementation of the data selector 14 is not limited, and may include, for example, a Multiplexer (MUX), or may be implemented based on circuit design of some transmission circuits (e.g., transmission gates, controllable switches, etc.), which is not limited herein.

Through the data selector of this example, can provide the write-in data that generates first check code to the encoder in the write-in phase, and provide the read-out data that generates the second check code to the encoder in the reading phase, thereby guarantee the normal work of encoder, avoid leading to data check error because of data reception error, improve data check's accuracy and reliability, and select the output through data selector, need not to design special data transmission circuit to the encoder, thereby effectively simplify circuit structure, reduce cost.

Based on the error correction code Syn output by the encoder 11, the first error correction circuit 12 performs single-bit error correction on the readout Data2 according to the error correction code Syn, resulting in first error correction Data Correct Data1. The specific configuration of the first error correction circuit 12 is not limited herein. In one example, FIG. 11 is a schematic diagram of an example on-chip verification circuit, and as shown in FIG. 11, the first error correction circuit 12 includes a first decoder 121 and a first correction circuit 122;

The input end of the first decoder 121 is connected to the encoder 11, the first decoder 121 is configured to receive the error correction code Syn output by the encoder 11, determine a first target position to be flipped based on the error correction code Syn and the error correction matrix, and output a first error correction instruction SBC pointing to the first target position;

The first correction circuit 122 is connected to an output terminal of the first decoder 121, and the first correction circuit 122 is configured to receive the readout Data2, and perform Data inversion on the bits at the first target position according to the first error correction command SBC, to obtain first error correction Data Correct Data1.

Specifically, the encoder 11 generates the error correction code Syn based on the first check code generated during writing and the second check code generated during reading, and in combination with the foregoing, the first check code and the second check code are generated by the encoder 11 based on the packet mode characterized by the error correction matrix according to the written data and the read data, respectively, so the encoder 11 matches the conditions satisfied by the foregoing error correction matrix according to the error correction code generated by the first check code and the second check code. It is known that the error correction matrix satisfies the bits corresponding to the exclusive or result of any of the plurality of error correction codes and is not located in the same beat as any of the plurality of bits. By defining the above conditions, a single-bit error can be accurately determined based on the error correction matrix, thereby performing single-bit error correction, and error amplification is avoided when a multi-bit error occurs. Specifically, for single-bit errors, the error correction code Syn generated by the encoder 11 is accurately directed to the error bit position, and accordingly, the first decoder 121 can accurately determine the error bit position corresponding to the error correction code Syn based on the error correction matrix according to the error correction code Syn output by the encoder 11, that is, the first target position obtained by the first decoder 121 is accurate and points to the actual error bit, and the corresponding first decoder 121 outputs the first error correction instruction SBC pointing to the first target position. The first correction circuit 122 receives the readout Data2, and the first error correction command SBC output by the first decoder 121 and directed to the first target position, and performs Data inversion on the bit in the first target position in the readout Data2 according to the first error correction command SBC, for example, if the bit in the first target position in the readout Data is 1, it is modified to 0, and if it is 0, it is modified to 1. It will be appreciated that since the error correction code Syn provided by the encoder 11 is accurate in the single bit error situation, the first decoder is also accurate according to the first error correction instruction SBC output by the error correction code Syn, so that the data inversion performed by the first correction circuit 122 can achieve accurate error correction.

For the case of multi-bit errors, the error correction code Syn generated by the encoder 11 is inaccurate, i.e. does not point to the actual erroneous bits accurately, based on the conditions that the error correction matrix fulfils. Specifically, the error correction code Syn at this time may not be the error correction code corresponding to any single bit in the error correction matrix, or may be the error correction code corresponding to a single bit in the error correction matrix, but the single bit is not in the same beat as the actual error bit. Accordingly, the first decoder 121 may not recognize the first target location based on the error correction matrix according to the error correction code Syn output by the encoder 11 at this time, and may not output the recognizable first error correction instruction SBC. For example, the first decoder 121 may not output the first error correction instruction, or output a pre-default invalid instruction, such as an all-zero instruction, indicating that no data flip is performed on any bit of the read data. Accordingly, the first correction circuit 122 does not perform data inversion on any bit of the read data, thereby ensuring that the data error is limited to the original error bit range, and no new bit error is generated. Or the first decoder 121 can obtain the first target position according to the error correction code Syn output by the encoder 11 at this time, but the first target position at this time does not point to the actual error bit accurately, but points to a certain bit of other beats, and correspondingly, the first error correction instruction SBC output by the first decoder 121 is also inaccurate, and the first correction circuit 122 performs data inversion on the bit under the first target position pointed by the first error correction instruction SBC at this time, but the data inversion at this time does not implement effective data error correction, but generates error correction. The error correction bit is not located in the same beat as any bit with actual error, so that the subsequent correction can be carried out through off-chip verification, the final data error is limited to the original error bit range, new uncorrectable bit errors cannot be caused, and the data error is prevented from being amplified.

In practical applications, the error correction matrix may be pre-stored in the encoder 11 and the first decoder 121, so that the first decoder 121 determines the first target position based on the error correction matrix, and outputs the first error correction instruction SBC. In this example, the first error correction circuit includes a first decoder and a first correction circuit, where the first decoder may determine a position to be flipped based on the error correction matrix according to the error correction code output by the encoder, output a first error correction instruction pointing to the position to be flipped, and the corresponding first correction circuit performs data flipping on bits under the position to be flipped, to obtain first error correction data. In this example, since the signals generated by the circuits are all obtained based on the error correction matrix satisfying the specific conditions, error correction can be avoided or generated error correction can be corrected through off-chip verification, so that single-bit error correction can be accurately and effectively performed, and meanwhile, data errors can be effectively prevented from being amplified for multi-bit error situations.

In practical application, in order to ensure accurate and reliable data transmission, a circuit for improving the accuracy of data transmission is also arranged. In one example, FIG. 12 is a schematic diagram of an exemplary on-chip verification circuit, and as shown in FIG. 12, the on-chip verification circuit 31 further includes a plurality of buffer circuits including:

a first buffer circuit 21, an input terminal of the first buffer circuit 21 receives the write Data1, and an output terminal of the first buffer circuit 21 is connected to a first input terminal of the Data selector 14 for buffering the received write Data 1;

the input end of the second buffer circuit 22 is connected with the output end of the Data selector 14, and the output end of the second buffer circuit 22 is connected to the storage array 13 and is used for buffering and outputting the write Data1 output by the Data selector 14 in the write-in stage;

The input end of the third buffer circuit 23 is connected with the encoder 11, and the output end of the third buffer circuit 23 is connected to the storage array 13 and is used for buffering and outputting the first check code output by the encoder 11 in the writing stage;

A fourth buffer circuit 24, an input end of the fourth buffer circuit 24 is connected to the memory array 13, and an output end of the fourth buffer circuit 24 is connected to the encoder 11, for buffering and outputting the first check code read out from the memory array 13 in a reading phase;

A fifth buffer circuit 25, an input terminal of the fifth buffer circuit 25 is connected to the memory array 13, and an output terminal of the fifth buffer circuit 25 is connected to the second input terminal of the Data selector 14 and the first error correction circuit 12, for buffering and outputting readout Data2 read out from the memory array 13 in a read phase;

The input end of the sixth buffer circuit 26 is connected to the output end of the first error correction circuit 12, and the output end of the sixth buffer circuit 26 is used for buffering and outputting the first error correction Data Correct Data1 output by the first error correction circuit 12.

The specific structure of the buffer circuit is not limited. As an example, the buffer circuit may include an even number of inverters in series. For example, taking the first buffer circuit 21 as an example, fig. 13 is a schematic diagram of a buffer circuit of an example, and as shown in fig. 13, the first buffer circuit 21 may include an even number of inverters 211 connected in series. It should be noted that other buffer circuits may also have the illustrated structure. In practical applications, the delay on each path can be considered when designing the number of inverters in the buffer circuit, so as to optimize the signal synchronization and match the signal timing.

The signal transmission conditions under each stage will be described by way of example with reference to the drawings, in which, during the writing stage, externally entered writing Data1 is transmitted to the first input terminal of the Data selector 14, and at this time, due to the writing stage, the Data selector 14 selects and outputs the writing Data received by the first input terminal, and accordingly, the writing Data output by the Data selector 14 is transmitted to the storage array 13 on the one hand, so as to realize storage of the writing Data, and is transmitted to the encoder 11 on the other hand. In this stage, the encoder 11 generates a first check code ECC code according to the received write data and the packet pattern represented by the error correction matrix, and outputs the first check code ECC code to the storage array 13 to store the check code at the time of writing. The above is the relevant signaling case for the write phase.

Next, when it is necessary to read the Data stored in the memory array 13, the read Data2 read out from the memory array 13 is transmitted to the second input terminal of the Data selector 14 and the Data input terminal of the first error correction circuit 12, while the first check code ECC code read out from the memory array 13 is transmitted to the encoder 11. At this time, the data selector 14 selects and outputs the read data received at the second input terminal to the encoder 11, since the read phase is in progress. Correspondingly, the encoder 11 generates a second check code according to the read data provided by the data selector 14 at this time and the grouping mode represented by the error correction matrix, and obtains an error correction code Syn according to the second check code and the first check code read from the memory array and outputs the error correction code Syn to the first error correction circuit 12. The second error correction circuit 12 performs single-bit error correction on the read Data according to the error correction code supplied from the encoder 11, and outputs the first error correction Data Correct Data1 to the outside of the chip.

The buffer circuit is arranged in the example, so that signal buffer transmission can be realized, accuracy and reliability of signal transmission are guaranteed, and signal synchronization can be further optimized and signal time sequence is matched by adjusting the delay characteristic of the buffer circuit.

Further, it is desirable to achieve efficient correction of multi-bit errors while avoiding data error amplification. In one example, in combination with the above error correction matrix, setting an error correction code corresponding to the multi-bit error is also considered to achieve effective error correction of the multi-bit error. To implement the multi-bit error correction described above, as an example, the exclusive or result of error correction codes corresponding to different bits belonging to the same beat in the error correction matrix is different. It will be appreciated that based on the verification principle, the exclusive or result of the error correction code corresponding to a plurality of bits can reflect the error correction code generated when the plurality of bits are in error. Meanwhile, considering that single-bit errors in each beat can be corrected through off-chip verification, in order to improve verification efficiency, multi-bit error correction is realized, and in this example, the exclusive or result of error correction codes corresponding to different bits belonging to the same beat in the error correction matrix is further limited to be different specifically for the data in the same beat. The term "different bits" refers to different combinations, and, in combination with the data structure of the foregoing example, taking each memory having eight data ports DQ0 to DQ7 as an example, it can be understood that the memory outputs 8 bits per beat, for example, d0 to d7 is output from DQ0 to DQ7 in the first beat, and d8 to d15 is output from DQ0 to DQ7 in the second beat. Accordingly, there are a number of combinations of 8 bits per beat to form a multi-bit combination. For example, with a certain beat of two bits, the bits output by DQ0 and DQ1 are one combination, the data output by DQ2 and DQ3 are one combination, and the data output by DQ0 and DQ2 are another combination, so long as the bits in the combination are not identical, they are considered to be different multiple bits. Further, the present invention is exemplified by two bits only, and it is understood that the multi-bits herein are not limited to the case of two bits, and may be three bits, four bits, or the like, for example. Based on the error correction matrix satisfying the above characteristics, an error correction matrix for a multi-bit case may be established, i.e. the error correction matrix comprises error correction codes corresponding to each group of multi-bits located at the same beat. The error correction code may be derived from an exclusive or result of the error correction code corresponding to each bit in the set of multiple bits. Subsequently, based on the error correction matrix for the multi-bit situation, when it is determined that the multi-bit error in the same beat occurs, multiple bits in which the error occurs can be determined based on the current error correction code combined with the error correction matrix containing the error correction code corresponding to each group of multi-bits in the same beat, so as to implement multi-bit error correction.

In combination with the above, as an example, fig. 14 is a schematic diagram of an exemplary on-chip verification circuit, and as shown in fig. 14, the on-chip verification circuit 31 further includes a second error correction circuit 15;

the second error correction circuit 15 is connected to the encoder 11, receives the multi-bit error correction instruction DUE, and reads the Data2 or the first error correction Data1, and is configured to respond to the multi-bit error correction instruction DUE pointing to the target beat number, perform multi-bit error correction on the received Data according to the error correction code Syn output by the encoder 11, and output the second error correction Data Correct Data2.

Wherein the multi-bit error correction instruction DUE directed to the target beat indicates that the readout Data2 is subjected to multi-bit errors located in the same beat, and the multi-bit errors occur in the target beat. As an example, the multi-bit error correction instruction may have an off-chip parity generation. Specifically, in combination with the foregoing, the off-chip verification is used for performing data verification on each beat of data output by all memories in the same library, and the off-chip verification can implement single-bit error correction and multi-bit detection. Therefore, for single-bit errors in each beat, correction can be effectively performed through off-chip verification, and for multi-bit errors in each beat, when the off-chip verification detects that the multi-bit errors exist in the beat of the current verification, a multi-bit error correction instruction DUE can be sent to the on-chip verification circuit, and the multi-bit error correction instruction points to the beat of the current verification, namely, the target beat number. In one example, the second error correction circuit 15 of the on-chip verification circuit may perform a subsequent operation based on the error correction code if it receives a multi-bit error correction instruction returned by the off-chip verification circuit. It should be noted that, the second error correction circuit 15 receives the multi-bit error correction instruction DUE, which is only used to represent the signal connection relationship of the second error correction circuit, and the receiving also includes receiving but not receiving, for example, the multi-bit error correction instruction is received only when the memory of the second error correction circuit determines that the memory needs to respond to the multi-bit error correction instruction based on the current error correction code, so as to reduce the power consumption. This is because, although the off-chip check can realize multi-bit detection, the off-chip check cannot locate errors which occur in particular to the multi-bits, that is, cannot determine which memory the multi-bit that occurs the error is output by under the present beat, so the off-chip check will send a multi-bit error correction instruction to all memories under the library after detecting that the multi-bit error exists in the present beat. Accordingly, the second error correction circuit of the on-chip check circuit of each memory performs the subsequent multi-bit error correction process only after determining that the currently received multi-bit error correction instruction is valid.

As an example, whether the multi-bit error correction instruction is responsive to the memory in which the on-chip verification circuitry is located may be determined based on the error correction code currently output by encoder 11. For example, if the encoder 11 in the on-chip checking circuit of a certain memory does not output an error correction code or the output error correction code is a default invalid code, that is, the on-chip checking result indicates that no data error occurs, the multi-bit error detected by the on-chip checking circuit may occur in the data output by other memories, so that even if the second error correction circuit of the on-chip checking circuit receives the multi-bit error correction instruction sent by the off-chip checking circuit, no data error correction is required, and the multi-bit error correction instruction sent to the present memory is not required to be responded. For another example, if the error correction code currently output by the encoder 11 in the on-chip checking circuit of a certain memory is not null or not a default invalid code, but the error correction code is not an error correction code corresponding to any multi-bit combination in the error correction matrix, that is, the error correction code cannot be identified, the response is not required depending on the multi-bit error correction instruction, and the data error correction is not performed as well. If the multi-bit error correction command needs to be responded, for example, the error correction code output by the current encoder 11 falls in any error correction code corresponding to different multi-bits defined in the error correction command, which indicates that multi-bit errors occur in the memory, correspondingly, the second error correction circuit 15 can determine the multi-bit error with error according to the multi-bit combination corresponding to the error correction code, and further perform data error correction. The specific error correction target may be read data, and the corresponding second error correction data after error correction may be transmitted to an off-chip verification circuit to perform off-chip verification again. Or the error correction object may be first error correction data, and the second error correction data obtained after error correction may be transmitted to an off-chip verification circuit, where the off-chip verification circuit performs off-chip verification again after integrating the first error correction data and the second error correction data. That is, in some embodiments, the second error correction circuit 15 may determine whether to respond to the multi-bit error correction instruction DUE based on the error correction code Syn.

In practical applications, the specific structure of the second error correction circuit is not limited, in one example, fig. 15 is a schematic diagram of an on-chip verification circuit of an example, and as shown in fig. 15, the second error correction circuit 15 includes a second decoder 151 and a second correction circuit 152;

An input end of the second decoder 151 is connected with the encoder 11, the second decoder 151 receives an error correction code Syn and a multi-bit error correction instruction DUE, and is used for responding to the multi-bit error correction instruction DUE pointing to the target beat number, determining a second target position to be flipped based on the target beat number pointed by the multi-bit error correction instruction DUE, the error correction code Syn and an error correction matrix, and outputting a second error correction instruction DBC pointing to the second target position;

The second correction circuit 152 is connected to an output terminal of the second decoder 151, and the second correction circuit 152 is configured to receive the readout Data2 or the first error correction Data Correct Data1, and perform Data error correction on the bits at the second target position according to the second error correction instruction, to obtain second error correction Data Correct Data2.

Specifically, the encoder 11 generates the error correction code Syn based on the first check code generated during writing and the second check code generated during reading, and in combination with the foregoing, the first check code and the second check code are generated by the encoder 11 based on the packet mode characterized by the error correction matrix according to the written data and the read data, respectively, so the encoder 11 matches the conditions satisfied by the foregoing error correction matrix according to the error correction code generated by the first check code and the second check code. It is known that the error correction matrix also satisfies that the exclusive or result of error correction codes corresponding to different bits belonging to the same beat is different. As an example, a further error correction matrix, also referred to hereinafter as a multi-bit error correction matrix, may be created comprising error correction codes corresponding to different combinations of bits of the same beat, each combination corresponding to an error correction code being derived based on the exclusive or result of the error correction code corresponding to each bit in the combination.

For the case of multi-bit errors, the off-chip checking circuit sends a multi-bit error correction command DUE to the on-chip checking circuits of all memories under the library, and taking the on-chip checking circuit of a certain memory as an example, the second decoder 151 of the on-chip checking circuit detects whether the error correction code is any error correction code defined in the multi-bit error correction matrix according to the error correction code Syn output by the current encoder 11, and if not, does not perform error correction. Otherwise, if the error correction code is a certain error correction code defined in the multi-bit error correction matrix, each bit under the combination is determined according to the multi-bit combination corresponding to the error correction code in the multi-bit error correction matrix, for example, it is determined that the bit combination corresponding to the error correction code includes the bits output by the data ports DQ0 and DQ 1. Further, in combination with the target beat number pointed to by the multi-bit error correction instruction DUE, for example, pointing to the second beat, it may be determined that the multi-bit error occurred is the data output by the memory at the second beat DQ0 and DQ1, and the data structures of the foregoing examples, namely d8 and d9, are combined. After determining the second target position where the multi-bit error occurs, the second decoder 151 outputs a second error correction instruction directed to the second target position to the second correction circuit 152. Correspondingly, the second correction circuit 152 performs Data inversion on the bits in the second target position in the read Data, for example, in combination with the above examples, i.e. d8 and d9, or the second correction circuit 152 may also perform Data inversion on the bits in the second target position in the first error correction Data Correct Data1 output by the first error correction circuit 12, so as to implement multi-bit error correction. The correction objects of the second correction circuit can be various, the multi-bit error correction can be carried out on the read data, the extra processing can be carried out without an off-chip verification circuit, the off-chip verification efficiency is improved, the multi-bit error correction is carried out on the first error correction data, a buffer structure for buffering the read data is not needed to be arranged on the second error correction circuit, and the structure of the on-chip verification circuit is simplified. Accordingly, in one example, the second correction circuit 152 is connected to a Data input of the first error correction circuit 12 for receiving the readout Data2, or the second correction circuit 152 is connected to an output of the first error correction circuit 12. Specifically, fig. 15 illustrates multi-bit error correction for the first error correction data.

The second error correction circuit in this example includes a second decoder and a second correction circuit, where the second decoder determines a multi-bit error position based on an error correction code corresponding to a multi-bit combination in the error correction matrix according to the error correction code and a target beat pointed by the multi-bit instruction, and the second correction circuit corrects the corresponding bit according to the second error correction instruction pointed to the multi-bit error position, thereby avoiding data error amplification, and being capable of implementing multi-bit error correction, and improving accuracy and reliability of data verification.

In practical application, in order to ensure accurate and reliable data transmission, a circuit for improving the accuracy of data transmission is also arranged. In one example, as also shown in fig. 15, the on-chip verification circuitry 31 further includes:

A seventh buffer circuit 27, an input end of the seventh buffer circuit 27 receives the multi-bit error correction instruction DUE, and an output end of the seventh buffer circuit 27 is connected to the second decoder 151, for buffering and outputting the multi-bit error correction instruction DUE;

The input end of the eighth buffer circuit 28 is connected to the output end of the second error correction circuit 15, and the output end of the eighth buffer circuit 28 is used for buffering and outputting the second error correction Data Correct Data2 output by the second error correction circuit 15.

The specific structure of the buffer circuit is not limited. As an example, the buffer circuit may include an even number of inverters in series. The signal transmission conditions under each stage are described by way of example in connection with the illustration, when the off-chip checking circuit detects that the multi-bit error exists in the current beat, the multi-bit error correction instruction DUE pointing to the current beat is sent to the seventh buffering circuit 27 of the on-chip checking circuit of all memories, taking a certain memory as an example, the seventh buffering circuit 27 of the on-chip checking circuit of the memory buffers the received multi-bit error correction instruction DUE to the second decoder 151, the second decoder 151 outputs a second error correction instruction DBC pointing to the position where the multi-bit error occurs in connection with the error correction matrix according to the target beat number pointed to by the multi-bit error correction instruction provided by the seventh buffering circuit 27, the second buffering circuit 28 outputs the second error correction Data coret 2 to the eighth buffering circuit 28, and the second correcting circuit 152 performs Data error correction on the corresponding bit in the read Data or the first error correction instruction according to the second error correction instruction DBC, so as to obtain the second error correction Data coret 2, and the output end of the second correcting circuit 152 serves as the output end of the second error correction circuit 15, and the eighth buffering circuit 28 outputs the second error correction Data coret 2 to the off-chip.

The on-chip checking circuit provided by the embodiment of the application comprises an encoder and a first error correction circuit, wherein the encoder is responsible for generating check codes of writing and reading stages, and obtaining error correction codes according to the check codes of the two stages, and the further first error correction circuit performs single-bit error correction on data read in the reading stage according to the error correction codes. The check code in the scheme is generated by the encoder based on the bit grouping represented by the error correction matrix, the error correction matrix comprises error correction codes corresponding to each bit in each beat, and the condition that the bits corresponding to the exclusive OR result of any plurality of error correction codes are not located in the same beat as any bit of the plurality of bits is satisfied, so even if error correction codes which are incorrectly corrected are generated due to the existence of multi-bit errors, the error correction codes which are incorrectly corrected are not located in the same beat as the bit which is incorrectly corrected, and new multi-bit errors in the same beat are not caused, thereby avoiding further expansion of data errors and improving the reliability of the check.

Example two

Fig. 16 is a diagram showing a structural example of an exemplary memory, as shown in fig. 16, which includes a memory array 13, and an on-chip verification circuit 31 as in any of the foregoing examples.

Taking a DRAM as an example in combination with the scheme of the foregoing embodiment, in a writing stage, the on-chip verification circuit 31 transmits the write Data1 to the storage array 13 while generating a first verification code ECC code based on the bit packet characterized by the write Data1 and the error correction matrix and storing the first verification code ECC code to the storage array 13, and in a reading stage, the on-chip verification circuit 31 reads the first verification code ECC code and the read Data2 from the storage array, generates a second verification code based on the read Data2 and the bit packet characterized by the error correction matrix, obtains an error correction code based on the first verification code and the second verification code, performs single-bit error correction on the read Data2 based on the error correction code, and outputs first error correction Data Correct Data1. The error correction matrix comprises error correction codes corresponding to each bit in each beat, and the error correction matrix meets the condition that the bits corresponding to the exclusive OR result of any plurality of error correction codes are not located in the same beat with any bit of the plurality of bits, so that the data errors are prevented from being amplified when multi-bit errors occur.

In the memory provided in this embodiment, the on-chip calibration circuit includes an encoder and a first error correction circuit, where the encoder is responsible for generating calibration codes of writing and reading phases, and obtaining an error correction code according to the calibration codes of the two phases, and the further first error correction circuit performs single-bit error correction on data read out in the reading phase according to the error correction code. The check code in the scheme is generated by the encoder based on the bit grouping represented by the error correction matrix, the error correction matrix comprises error correction codes corresponding to each bit in each beat, and the condition that the bits corresponding to the exclusive OR result of any plurality of error correction codes are not located in the same beat as any bit of the plurality of bits is satisfied, so even if error correction codes which are incorrectly corrected are generated due to the existence of multi-bit errors, the error correction codes which are incorrectly corrected are not located in the same beat as the bit which is incorrectly corrected, and new multi-bit errors in the same beat are not caused, thereby avoiding further expansion of data errors and improving the reliability of the check.

Example III

FIG. 17 is a diagram showing an example of the structure of a memory device including an off-chip verification circuit 41 and at least one memory 42 as in example two, as shown in FIG. 17;

the off-chip verification circuit 41 is connected to the at least one memory 42 for verifying each beat of Data in the first error correction Data Correct Data1 output by the at least one memory 42 during the read phase, the verification comprising single bit error correction and multi bit detection.

In connection with the scheme example of the foregoing embodiment, in the reading stage, each memory 42 obtains the first error correction Data Correct Data1 based on the foregoing verification process, and outputs each beat of Data of the first error correction Data Correct Data1 beat by beat. The off-chip verification circuit 41 receives the first error correction Data Correct Data1 output from all the memories 42 currently being photographed, and performs off-chip Data verification. In combination with the foregoing, since the error correction matrix used in the on-chip calibration meets a specific condition, the on-chip calibration does not generate error correction for multi-bit errors or even if error correction occurs, the position of the error correction bit does not cause the off-chip calibration to generate new same-beat multi-bit errors, thereby avoiding the amplification of data errors.

Further, if the current beat of data has a single-bit error, the off-chip check circuit 41 performs single-bit error correction on the current beat of data, and if the current beat of data has a multi-bit error, the off-chip check circuit 41 sends a multi-bit error correction instruction to all the memories 42. In one example, the off-chip verification circuit 41 includes an indication circuit 411, and the indication circuit 411 is configured to send a multi-bit error correction instruction DUE to the target beat number to all the memories 42 if there is a multi-bit error under the same beat data. Specifically, each memory 42 confirms whether the multi-bit error correction instruction is valid for itself, and if so, performs multi-bit error correction, outputting the second error correction Data Correct Data2. The memory may perform multi-bit error correction based on the read data or may perform multi-bit error correction based on the first error correction data.

Correspondingly, in order to obtain final accurate data, the off-chip verification circuit 41 further comprises a processing circuit 412, which is used for performing first data integration on the first error correction data output by different memories and performing data verification on the integrated data, outputting off-chip verified data if no data error exists or correction can be performed, performing error data replacement on the integrated data based on the second error correction data after receiving the second error correction data if the second error correction data is required, performing data verification again, and outputting off-chip verified data if no data error exists or correction can be performed. Specifically, the processing circuit 412 performs the first integration according to the first error correction result obtained by the single-bit error correction for each memory to obtain the check object of the off-chip check, that is, integrates the data belonging to the current beat in the first error correction result of each memory. And (3) performing data verification on the data, and outputting the data subjected to off-chip verification if the currently shot data has no data error or only single-bit error (namely, can be corrected). If the integrated data, i.e. the data currently shot from each memory has a multi-bit error, is found to be returned to the memory for secondary correction, and accordingly, the instruction circuit 411 sends a multi-bit error correction instruction to all the memories, and in combination with the above scheme, the memory that needs to respond to the instruction performs multi-bit error correction on its own data and then outputs a second error correction result, and after receiving the second error correction result after the second error correction result, the processing circuit 412 replaces the error bit in the data obtained by the first integration, performs data verification again, and if the verification passes, outputs the final accurate data.

In the memory device provided by this embodiment, the on-chip check circuit of the memory includes an encoder and a first error correction circuit, where the encoder is responsible for generating check codes of writing and reading phases, and obtaining error correction codes according to the check codes of the two phases, and the further first error correction circuit performs single-bit error correction on data read out in the reading phase according to the error correction codes. The check code in the scheme is generated by the encoder based on the bit grouping represented by the error correction matrix, the error correction matrix comprises error correction codes corresponding to each bit in each beat, and the condition that the bits corresponding to the exclusive OR result of any plurality of error correction codes are not located in the same beat as any bit of the plurality of bits is satisfied, so even if error correction codes which are incorrectly corrected are generated due to the existence of multi-bit errors, the error correction codes which are incorrectly corrected are not located in the same beat as the bit which is incorrectly corrected, and new multi-bit errors in the same beat are not caused, thereby avoiding further expansion of data errors and improving the reliability of the check.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. The specification and examples are to be regarded in an illustrative manner only.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof.

Claims

1. An on-chip verification circuit, characterized in that it is applied to a memory, and the on-chip verification circuit comprises:

An encoder connected to the storage array of the memory, and configured to generate a first check code according to the write data and the bit grouping represented by the error correction matrix in a write phase, and write the first check code into the storage array; and to generate a second check code according to the read data and the bit grouping represented by the error correction matrix in a read phase, and generate an error correction code based on the read first check code and the second check code;

a first error correction circuit connected to the encoder, configured to receive the read data, and perform single-bit error correction on the read data according to the error correction code output by the encoder, and then output first error-corrected data;

The error correction matrix includes an error correction code corresponding to each bit in each beat, and the error correction matrix satisfies: an XOR result of the error correction codes corresponding to any multiple bits is not the same as an error correction code corresponding to any bit in the same beat as one of the multiple bits.

2. The on-chip verification circuit according to claim 1, characterized in that:

In the error correction matrix, an XOR result of the error correction codes corresponding to any multiple bits belonging to the same beat is not the same as the error correction code corresponding to any bit in the error correction matrix;

The XOR result of the error correction codes corresponding to any multiple bits belonging to different beats is not the same as the error correction code corresponding to any bit located in the same beat as one of the multiple bits.

3. The on-chip verification circuit according to claim 1, characterized in that the on-chip verification circuit further comprises: a data selector;

The first input end of the data selector receives the write data, the second input end of the data selector receives the read data, and the output end of the data selector is connected to the input end of the encoder and the storage array;

The data selector is used to output the write data in the write phase and output the read data in the read phase.

4. The on-chip check circuit according to claim 3, characterized in that the first error correction circuit comprises: a first decoder and a first correction circuit;

The input end of the first decoder is connected to the encoder, and the first decoder is used to receive the error correction code output by the encoder, determine a first target position to be flipped based on the error correction code and the error correction matrix, and output a first error correction instruction pointing to the first target position;

The first correction circuit is connected to the output end of the first decoder, and is used for receiving the read data and performing data flipping on the bits at the first target position according to the first error correction instruction to obtain the first error correction data.

5. The on-chip verification circuit according to claim 4, characterized in that the on-chip verification circuit further comprises: a plurality of buffer circuits, including:

a first buffer circuit, wherein an input end of the first buffer circuit receives the write data, and an output end of the first buffer circuit is connected to a first input end of the data selector, and is used for buffering and outputting the received write data;

a second buffer circuit, wherein an input end of the second buffer circuit is connected to an output end of the data selector, and an output end of the second buffer circuit is connected to the storage array, and is used for buffering and outputting the write data output by the data selector during the write phase;

a third buffer circuit, wherein an input end of the third buffer circuit is connected to the encoder, and an output end of the third buffer circuit is connected to the storage array, and is used for buffering and outputting the first check code output by the encoder during the writing phase;

a fourth buffer circuit, wherein an input end of the fourth buffer circuit is connected to the storage array, an output end of the fourth buffer circuit is connected to the encoder, and is used for buffering and outputting the first check code read from the storage array during the reading phase;

a fifth buffer circuit, wherein an input end of the fifth buffer circuit is connected to the memory array, an output end of the fifth buffer circuit is connected to the second input end of the data selector and the first error correction circuit, and is used for buffering and outputting the read data read from the memory array in the read phase;

A sixth buffer circuit, wherein an input end of the sixth buffer circuit is connected to an output end of the first error correction circuit, and an output end of the sixth buffer circuit is used for buffering and outputting the first error correction data output by the first error correction circuit.

6 . The on-chip verification circuit according to claim 5 , wherein the buffer circuit comprises: an even number of inverters connected in series.

7. The on-chip check circuit according to claim 1, wherein the XOR result of the error correction codes corresponding to the arbitrary multiple bits is not the same as the error correction code corresponding to any bit in the same beat as one of the multiple bits, comprising:

The XOR result of the error correction codes corresponding to any two bits in the same beat is not the same as the error correction code corresponding to any bit in the same beat as one of the two bits.

8. The on-chip check circuit according to any one of claims 1 to 7, characterized in that, in the error correction matrix, the XOR results of the error correction codes corresponding to different multiple bits belonging to the same beat are different.

9. The on-chip verification circuit according to claim 8, characterized in that the on-chip verification circuit further comprises: a second error correction circuit;

The second error correction circuit is connected to the encoder, receives a multi-bit error correction instruction, and the read data or the first error correction data, and is used to respond to the multi-bit error correction instruction pointing to the target beat number, perform multi-bit error correction on the received data according to the error correction code output by the encoder, and then output second error correction data;

The multi-bit error correction instruction pointing to the target beat number indicates that a multi-bit error occurs in the read data in the same beat, and the multi-bit error occurs in the target beat number.

10. The on-chip check circuit according to claim 9, characterized in that the second error correction circuit comprises: a second decoder and a second correction circuit;

The input end of the second decoder is connected to the encoder, and the second decoder receives the error correction code and the multi-bit error correction instruction, and is used to respond to the multi-bit error correction instruction pointing to the target beat number, determine the second target position to be flipped based on the target beat number pointed to by the multi-bit error correction instruction, the error correction code and the error correction matrix, and output a second error correction instruction pointing to the second target position;

The second correction circuit is connected to the output end of the second decoder, and is used to receive the read data or the first error correction data, and perform data error correction on the bits under the second target position according to the second error correction instruction to obtain the second error correction data.

11. The on-chip verification circuit according to claim 10, characterized in that the second correction circuit is connected to a data input terminal of the first error correction circuit for receiving the read data, or the second correction circuit is connected to an output terminal of the first error correction circuit.

12. A memory, comprising: a memory array and an on-chip verification circuit according to any one of claims 1 to 11.

13. A storage device, comprising: an off-chip verification circuit and at least one memory as claimed in claim 12;

The off-chip verification circuit is connected to the at least one memory and is used to verify each beat of the first error correction data output by the at least one memory during a reading phase, wherein the verification includes single-bit error correction and multi-bit detection.

14. The storage device according to claim 13, wherein the off-chip verification circuit comprises: an indication circuit;

The indication circuit is used to send a multi-bit error correction instruction pointing to the target beat number to all the memories if there are multi-bit errors in the same beat data.

15. The storage device according to claim 14, wherein the off-chip verification circuit further comprises:

A processing circuit is used to perform a first data integration on the first error-corrected data output by different memories, and to perform data verification on the integrated data; if no data error exists or can be corrected, then the off-chip verified data is output; if the memory needs to perform a second correction, then after receiving the second error-corrected data, the erroneous data is replaced on the integrated data based on the second error-corrected data and the data is verified again; if no data error exists or can be corrected, then the off-chip verified data is output.