CN119208130B - Semiconductor device preparation method, electrical performance adjustment method and semiconductor device - Google Patents
Semiconductor device preparation method, electrical performance adjustment method and semiconductor device Download PDFInfo
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- CN119208130B CN119208130B CN202411705557.5A CN202411705557A CN119208130B CN 119208130 B CN119208130 B CN 119208130B CN 202411705557 A CN202411705557 A CN 202411705557A CN 119208130 B CN119208130 B CN 119208130B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 226
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 64
- 239000002019 doping agent Substances 0.000 claims abstract description 32
- 230000004048 modification Effects 0.000 claims abstract description 17
- 238000012986 modification Methods 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000007423 decrease Effects 0.000 claims description 8
- 210000000746 body region Anatomy 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 206010034972 Photosensitivity reaction Diseases 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000036211 photosensitivity Effects 0.000 description 3
- 238000002835 absorbance Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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Abstract
The application discloses a preparation method of a semiconductor device, an electrical property adjustment method and the semiconductor device, wherein the preparation method of the semiconductor device comprises the steps of dividing a semiconductor wafer into a plurality of areas; the method comprises the steps of selectively implanting a first type of dopant into a semiconductor wafer to form a first doped region of the first doped type in the semiconductor wafer, forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doped region, carrying out modification treatment on the mask layer in a zoned manner to adjust the ion implantation resistance of the mask layer in a zoned manner, and implanting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is implanted into the semiconductor wafer exposed by the mask layer to form a second doped region of the second doped type, and part of the second type of dopant is implanted into the first doped region covered by the mask layer to adjust the doping concentration of the first doped region.
Description
Technical Field
The present application relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device, a method for adjusting electrical properties of the semiconductor device, and a semiconductor device.
Background
A plurality of semiconductor devices having the same structure are formed in a conventional semiconductor wafer. The electrical properties of the same semiconductor device vary across the semiconductor wafer. In general, the difference in electrical properties of semiconductor devices is particularly pronounced in the center region of the semiconductor wafer and in the edge regions of the semiconductor wafer.
The difference in electrical properties of the same semiconductor wafer is mainly due to the end result of various processes such as in-plane doping concentration difference during ion implantation, thermal in-plane difference, and gate linewidth dimension difference. The current method for adjusting the electrical properties of the semiconductor wafer is ion implantation of the wafer surface, which cannot eliminate the electrical property difference in the wafer surface. And on the premise of not newly adding a photoetching mask plate, the differential adjustment of any semiconductor device in the wafer cannot be realized.
Disclosure of Invention
In view of the foregoing, it is an object of the present application to provide a method for manufacturing a semiconductor device, a method for adjusting electrical properties, and a semiconductor device, which can realize a zonal adjustment of doping concentration of a first doping region in the same semiconductor wafer without increasing photolithography and ion implantation steps.
According to one aspect of the invention, a preparation method of a semiconductor device is provided, and the preparation method comprises the steps of dividing a semiconductor wafer into a plurality of areas, selectively implanting a first type of dopant into the semiconductor wafer, forming a first doping area of the first doping type in the semiconductor wafer, forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doping area, carrying out modification treatment on the mask layer in areas to adjust the ion implantation resistance of the mask layer in areas, and implanting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is implanted into the semiconductor wafer exposed by the mask layer to form a second doping area of the second doping type, and part of the second type of dopant is implanted into the first doping area covered by the mask layer to adjust the doping concentration of the first doping area.
Optionally, the mask layer is a photoresist mask, and the modification treatment is performed on the mask layer by exposing the mask layer with a light beam corresponding to a photosensitive wavelength of the mask layer.
Optionally, when the mask layer is modified by exposing the mask layer with a light beam, the ion implantation resistance of the mask layer is controlled by adjusting the exposure time length of the mask layer.
Optionally, when the mask layer is modified by exposing the mask layer with a light beam, the single exposure time of the light beam is constant, the ion implantation resistance of the mask layer is related to the exposure times of the mask layer, and the ion implantation resistance of the mask layer is controlled by adjusting the exposure times of the mask layer.
Optionally, when the mask layer is modified by exposing the mask layer with a light beam, the ion implantation resistance of the mask layer gradually decreases and then becomes stable as the exposure times of the mask layer increases.
According to another aspect of the invention, an electrical property adjusting method of a semiconductor device is provided, wherein the electrical property of the semiconductor device is related to the exposure times of a mask layer, the electrical property adjusting method comprises the steps of obtaining a fitting curve of the electrical property of the semiconductor device and the exposure times of the mask layer, forming a first doping region of a first doping type in a semiconductor wafer, forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doping region, realizing mask layer modification by using a light beam to expose the mask layer, enabling the single exposure time of the light beam to be constant, adjusting the exposure times of the mask layer according to the fitting curve in a region, performing modification treatment on the mask layer in a region to adjust the ion implantation resistance of the mask layer in a region, implanting a second doping type dopant opposite to the first doping type into the semiconductor wafer through the mask layer after modification, forming a second doping region of a second doping type in the semiconductor wafer exposed by the mask layer, implanting a part of the second doping type into the mask layer, and adjusting the doping region of the semiconductor wafer according to the first doping region.
Optionally, the fitted curve of the electrical property of the semiconductor device and the number of exposures of the mask layer includes an adjustment region in which the electrical property changes with increasing number of exposures and a stability region that approaches a stability value.
Optionally, the number of exposures of the mask layer in different regions is adjusted so that the electrical properties of the same semiconductor device in different regions of the same semiconductor wafer are uniform to eliminate differences in the electrical properties of the same semiconductor device in different regions of the same semiconductor wafer.
Optionally, the number of exposures of the mask layer in different regions is adjusted such that there is a difference in electrical properties of the same semiconductor device in different regions of the same semiconductor wafer to form semiconductor devices with different electrical properties in different regions of the same semiconductor wafer.
According to another aspect of the invention, a semiconductor device formed by the method is provided, and the semiconductor device comprises a semiconductor wafer, wherein the semiconductor wafer comprises a plurality of areas, a first doping area of a first doping type and a second doping area of a second doping type, the first doping area is located in the semiconductor wafer, the doping concentration of the first doping area is adjusted while the second doping area is formed, and the doping concentrations of the first doping areas in different areas are the same or different.
The unexpected technical effects of the application are:
According to the application, the same mask layer is subjected to regional modification treatment, so that the ion implantation resistance of the mask layer is adjusted in a regional manner, and the regional control of the doping concentration of the first doping region of the same semiconductor wafer is realized on the premise of not increasing photoetching and ion implantation steps.
In the process of forming the second doped region, the application realizes the adjustment of the doping concentration of the first doped region without adding extra photoetching and ion implantation steps.
The mask layer is a photoresist mask layer, and the ion implantation resistance of the mask layer is controlled by controlling the exposure time length of the mask layer, so that the ion implantation resistance of the mask layer is controlled conveniently.
The single exposure time of the light beam is fixed, the ion implantation resistance of the mask layer is further controlled by controlling the exposure times of the mask layer, and the corresponding relation between the exposure times of the mask layer and the electrical property of the semiconductor device is obtained, so that the electrical property of the semiconductor device is conveniently optimized.
The application enables the electrical properties of the same semiconductor device in different areas of the same semiconductor wafer to be consistent by controlling the ion implantation resistance of the mask layers in different areas, so as to eliminate the difference of the electrical properties of the same semiconductor device in different areas of the same semiconductor wafer.
The application controls the ion implantation resistance of the mask layer in different areas to ensure that the electrical properties of the same semiconductor device in different areas of the same semiconductor wafer are different, so that the semiconductor devices with different electrical properties are formed in different areas of the same semiconductor wafer.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings, in which:
fig. 1 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present application;
FIG. 2a-1 illustrates a schematic top view of a semiconductor wafer in accordance with an embodiment of the present application;
fig. 2a-2 shows a partial cross-sectional view of one of the semiconductor devices of fig. 2 a-1;
FIG. 2b illustrates a cross-sectional view of an embodiment of the present application after forming a first doped region in a semiconductor wafer;
Fig. 2c shows a cross-sectional view of an embodiment of the present application after forming a second mask layer PR2 on the semiconductor wafer;
FIG. 2d shows a cross-sectional view of a modification of the second mask layer PR2 according to an embodiment of the present application;
FIG. 2e shows a schematic cross-sectional view of a second ion implantation in accordance with an embodiment of the present application;
FIG. 3 is a schematic diagram showing the threshold voltage Vth distribution of the same semiconductor device in the semiconductor wafer plane in one embodiment;
FIG. 4 shows the photosites curves of different photoresist masks;
FIG. 5 illustrates a region division of a semiconductor wafer in one embodiment;
FIG. 6 is a schematic diagram showing a portion of the threshold voltage of the same semiconductor device in the semiconductor wafer shown in FIG. 5;
fig. 7 shows a fitted curve between the threshold voltage of the semiconductor device and the number of exposures;
fig. 8 shows a fitted curve between the drain saturation current and the number of exposures of the semiconductor device;
fig. 9 illustrates a region division of a semiconductor wafer in accordance with another embodiment of the present application.
Detailed Description
The application will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown.
The application may be embodied in various forms, some examples of which are described below.
Fig. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present application, and as shown in fig. 1, the method for manufacturing a semiconductor device includes:
s110, dividing a semiconductor wafer into a plurality of areas;
s120, selectively implanting a first type dopant into the semiconductor wafer to form a first doping region of a first doping type in the semiconductor wafer;
S130, forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doped region;
s140, carrying out modification treatment on the mask layer in a zoned manner so as to adjust the ion implantation resistance of the mask layer in a zoned manner, and
And S150, implanting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is implanted into the semiconductor wafer exposed by the mask layer to form a second doped region of the second doping type, and part of the second type of dopant is implanted into the first doped region covered by the mask layer to adjust the doping concentration of the first doped region.
Fig. 2a-1 to 2e are schematic structural views showing various stages in the manufacturing process of a semiconductor device according to an embodiment of the present application. The method of manufacturing the semiconductor device of the present application will be described below with reference to fig. 2a-1 to 2 e.
Fig. 2a-1 illustrates a schematic top view of a semiconductor wafer 10 in accordance with an embodiment of the present application, and fig. 2a-2 illustrates a partial cross-sectional view of one of the semiconductor devices of fig. 2 a-1.
As shown in fig. 1, 2a-1 and 2a-2, the semiconductor wafer 10 is divided into a plurality of regions 110.
The semiconductor wafer 10 includes a plurality of basic operation units (shots) 10a, each basic operation unit 10a including one or more chips (chips), each chip including one or more semiconductor devices. In the present embodiment, the semiconductor device is, for example, a MOSFET (i.e., a metal oxide semiconductor field effect transistor), but is not limited thereto. The electrical properties of the semiconductor device include the threshold voltage Vth of the MOSFET, the drain saturation current Ids, the breakdown voltage BVD, the leakage current I off, the on-resistance R, and the like.
Fig. 3 shows a schematic diagram of threshold voltage Vth distribution of the same semiconductor device in a semiconductor wafer in one embodiment. As shown in fig. 3, the semiconductor wafer 10 includes a plurality of basic operation units 10a, and each operation unit 10a includes at least one semiconductor device having the same structure, such as a MOSFET device. The threshold voltages Vth of the same semiconductor devices in the plane of the semiconductor wafer 10 are different, specifically, the absolute values of the threshold voltages Vth of the same semiconductor devices in the semiconductor wafer gradually increase from the center of the semiconductor wafer 10 to the edge of the semiconductor wafer 10.
The variation in electrical properties of the same semiconductor device in the same semiconductor wafer 10 is mainly due to the end result of various processes such as in-plane doping concentration variation during ion implantation, thermal process in-plane variation, and gate line width dimension variation.
In the embodiment of the application, the semiconductor wafer 10 is divided into a plurality of regions 110, so that the doping concentrations of the body regions (first doping regions) of different regions are respectively adjusted in the subsequent steps, the doping concentration of the body regions (first doping regions) of the same semiconductor wafer 10 is controlled in different regions, and the doping concentrations of the body regions (first doping regions) of the same semiconductor wafer are adjusted, so that the electrical performance of the device is adjusted. In this embodiment, for example, the doping concentration of the body region (first doped region) in different regions of the same semiconductor wafer is adjusted so that the electrical properties of the semiconductor devices in different regions of the same semiconductor wafer remain uniform.
As shown in fig. 2a-1, in the embodiment, the semiconductor wafer 10 is divided into a first region 110a, a second region 110b and a third region 110c, where the first region 110a, the second region 110b and the third region 110c are sequentially distributed from inside to outside, the first region 110a is a circular region located in a central region of the semiconductor wafer 10, the second region 110b is an annular region surrounding the first region 110a, and the third region 110c surrounds an annular region of the second region 110 b.
Fig. 2b shows a cross-sectional view of an embodiment of the present application after forming a first doped region in a semiconductor wafer, as shown in fig. 1 and 2b, forming a first doped region 111 of a first doping type in a semiconductor wafer 10.
In this step, a first mask layer PR1 is formed on the semiconductor wafer 10, for example, the first mask layer PR1 is patterned using a photolithography process, and a first ion implantation is performed on the semiconductor wafer 10 through the patterned first mask layer PR1 to form a first doped region 111 in the semiconductor wafer 10, wherein a first type of dopant is implanted into the semiconductor wafer 10 during the first ion implantation. In one embodiment, the first mask layer PR1 is a photoresist mask, and the first doping type is N-type doping.
Further, at least one first doped region 111 is formed in each of the plurality of regions 110.
Fig. 2c shows a cross-sectional view of an embodiment of the present application after forming a second mask layer PR2 on the semiconductor wafer, as shown in fig. 1 and 2c, forming a patterned second mask layer PR2 on the semiconductor wafer, wherein the patterned second mask layer PR2 covers the first doped region 111.
In this step, a second mask layer PR2 is formed in the semiconductor wafer, and the second mask layer PR2 is patterned, for example, using a photolithography process, to form a patterned second mask layer PR2, and the patterned second mask layer PR2 covers the first doping region 111.
Fig. 2d is a cross-sectional view illustrating modification of the second mask layer PR2 according to an embodiment of the present application, wherein the patterned second mask layer PR2 is modified to adjust the ion implantation resistance of the second mask layer PR2, as shown in fig. 1 and 2d, wherein the ion implantation resistance of the second mask layer PR2 is the same or different in different regions.
The second mask layer PR2 is, for example, a photoresist mask, and the second mask layer PR2 is modified by exposing the second mask layer PR2 to light.
The photosensitive wavelengths of the different photoresist masks are different, and the mask layer is subjected to modification treatment by exposing the mask layer with a light beam corresponding to the photosensitive wavelength of the mask layer. Fig. 4 shows the photosensitivity curves of different photoresist masks, wherein the abscissa of the photosensitivity curves is wavelength (nm), and the ordinate is absorbance, and the greater the absorbance, the greater the photosensitivity. As shown in fig. 4, the photosensitive wavelength of the first photoresist mask is 200 nm to 300 nm, and the photosensitive wavelength of the second photoresist mask is 240 nm to 260 nm.
Further, a light beam of a corresponding wavelength is selected according to the kind of the photoresist to be exposed. For example, a first photoresist mask is exposed with a light beam having a wavelength range of 200 nm to 300 nm, and a second photoresist mask is exposed with a light beam having a wavelength range of 240 nm to 260 nm.
In other embodiments, a corresponding type of photoresist mask may also be selected based on the wavelength of the light beam. The existing machine has the function of scanning light beams, such as a KLA wafer defect scanning machine, a photoetching machine, a UV irradiation machine and the like, and can select a corresponding type of photoresist mask according to the wavelength of the light beams of the existing machine.
After the second mask layer PR2 is scanned by the light of the corresponding wavelength, the molecular weight thereof becomes smaller, so that the ion implantation resistance of the second mask layer PR2 becomes weaker. Further, the ion implantation resistance of the second mask layer PR2 varies with the exposure time. Specifically, the ion implantation resistance of the second mask layer PR2 decreases as the exposure time length of the second mask layer PR2 increases, and when the exposure time length reaches a certain time length, the ion implantation resistance of the second mask layer PR2 becomes stable and no more changes occur as the exposure time length of the second mask layer PR2 increases.
The doping concentration of the first doping region 111 may be adjusted in regions by controlling the length of the exposure time of each of the plurality of regions, thereby controlling the ion implantation resistance of the second mask layer PR2 in each of the plurality of regions. In an embodiment, the single exposure time of the beam is constant, and the ion implantation resistance of the second mask layer PR2 can be adjusted by controlling the number of exposures. In the process of adjusting the doping concentration of the first doped region 111, as the number of exposure times of the second mask layer PR2 increases, the 211 doping concentration of the first doped region gradually decreases and then becomes stable.
In this embodiment, the first region 110a is exposed to the second mask layer PR2 for a first period of time, the second region 110b is exposed to the second mask layer PR2 for a second period of time, and the third region 110c is exposed to the second mask layer PR2 for a third period of time, wherein the first period of time, the second period of time, and the third period of time are different, and in one embodiment, the first period of time is less than the second period of time, the second period of time is less than the third period of time, the ion implantation resistance of the second mask layer PR2 in the first region 110a is greater than the ion implantation resistance of the second mask layer PR2 in the second region 110b, and the ion implantation resistance of the second mask layer PR2 in the second region 110b is greater than the ion implantation resistance of the second mask layer PR2 in the third region 110 c.
Fig. 2e is a schematic cross-sectional view illustrating a second ion implantation according to an embodiment of the present application, as shown in fig. 1 and 2e, the second ion implantation is performed on the semiconductor wafer 10 through the modified second mask layer PR2 to form a second doped region 112 of a second doping type in the semiconductor wafer 10, wherein the second ion implantation simultaneously adjusts the doping concentrations of the first doped regions 111 of different regions during the formation of the second doped region 112 so that the doping concentrations of the first doped regions 111 of different regions are the same or different.
In this step, the semiconductor wafer 10 is subjected to a second ion implantation through the modified second mask layer PR2, wherein the second type of dopant is implanted into the semiconductor wafer 10 during the second ion implantation. The second type of dopant is of an opposite type to the first type of dopant. Since the ion implantation resistance of the modified second mask layer PR2 is weakened, during the second ion implantation, the second type dopant is implanted into the semiconductor wafer 10 exposed by the second mask layer PR2 to form the second doped region 112 of the second doping type, and part of the second type dopant enters the first doped region 111 through the modified second mask layer PR2, and part of the first type dopant in the first doped region 111 is neutralized, so as to adjust the doping concentration of the first doped region 111.
Further, in the present embodiment, the second mask layer PR2 in different regions has different ion implantation resistance, so that the second ion implantation changes the doping concentration of the first doped region 111 in different regions. The ion implantation resistance of the second mask layer PR2 in the different regions is controlled to control the doping concentration of the first doped region 111 in the different regions, so that the difference of the doping concentrations of the first doped region 111 in the different regions can be eliminated.
In this embodiment, since the ion implantation resistance of the second mask layer PR2 in the first region 110a is greater than that of the second mask layer PR2 in the second region 110b, more of the second type dopant in the second region 110b enters the first doped region 111 relative to the first region 110a, more of the first type dopant in the first doped region 111 in the second region 110b is neutralized, and thus the difference in doping concentration between the first doped region 111 in the first region 110a and the first doped region 111 in the second region 110b is reduced or even eliminated. Similarly, the second mask layer PR2 in the second region 110b has a greater ion implantation resistance than the second mask layer PR2 in the third region 110c, and the difference in doping concentration between the first doped region 111 in the second region 110b and the first doped region 111 in the third region 110cb is reduced or even eliminated.
Further, the method of forming a semiconductor device further includes forming an active region, a source region, a drain region, a gate stack structure, and the like, to finally form a plurality of semiconductor devices in the semiconductor wafer 10.
Through the above-described method, the difference in electrical properties of the same semiconductor device in different regions of the same semiconductor wafer 10 is eliminated by adjusting the ion implantation resistance of the second mask layer PR2 in the different regions. In other embodiments, semiconductor devices having different electrical properties may also be formed in different regions of the same semiconductor wafer 10 by adjusting the ion implantation resistance of the second mask layer PR2 in the different regions.
In the above embodiment, the semiconductor wafer is divided into the plurality of regions sequentially arranged from inside to outside, it should be understood that the shape and the number of the plurality of regions and the arrangement manner among the plurality of regions are not limited thereto, and other region division forms may be provided. Fig. 5 illustrates a region division form of a semiconductor wafer in an embodiment, and as shown in fig. 5, the semiconductor wafer 20 is divided into a plurality of regions 210 distributed sequentially from top to bottom, and each region of the plurality of regions 210 is rectangular. The plurality of regions include, for example, first regions 210a to eighth regions 210h arranged in order from top to bottom.
In the process of modifying the second mask layer PR2 of the different region, the first region 210a is exposed 12 times, the second region 210b is exposed 6 times, the third region 210c is exposed 4 times, the fourth region 210d is exposed 2 times, the fifth region 210e is exposed 1 time, the sixth region 210f is exposed 2 times, the seventh region 210g is exposed 4 times, and the eighth region 210h is exposed 20 times.
Fig. 6 is a schematic view showing a portion of the threshold voltage of the same semiconductor device in a plurality of regions in the semiconductor wafer shown in fig. 5, and as shown in fig. 6, the number of exposure times of the fifth region 210e is the smallest, the threshold voltage (absolute value) of the semiconductor device 210a in the fifth region 210e is the highest, and from the fifth region 210e toward the first region 210a, the number of exposure times of each region gradually increases, and accordingly, the threshold voltage (absolute value) of the semiconductor device 210a in each region gradually decreases. Similarly, from the fifth region 210e toward the eighth region 210h, the number of exposure times per region gradually increases, and accordingly, the threshold voltage (absolute value) of the semiconductor device 210a in each region gradually decreases.
Further, the number of times of exposure of the first region 210a is much smaller than that of the eighth region 210h, but the threshold voltage (absolute value) of the semiconductor device 210a in the eighth region 210h is not significantly reduced compared to the threshold voltage (absolute value) of the semiconductor device 210a in the first region 210 a.
As can be seen from the above embodiments, the electrical performance of the semiconductor device is related to the number of exposure times of the second mask layer, and the present embodiment obtains a fitting curve of the electrical performance of the semiconductor device and the number of exposure times of the second mask layer, and adjusts the electrical performance of the semiconductor device according to the curve fitting curve. The method specifically comprises the following steps:
S200, obtaining a fitting curve of the electrical property of the semiconductor device and the exposure times of the second mask layer;
s210, dividing a semiconductor wafer into a plurality of areas;
s220, forming a first doping region of a first doping type in the semiconductor wafer;
s230, forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doped region;
S240, realizing mask layer modification by adopting a light beam to expose a mask layer, wherein the single exposure time of the light beam is constant, and the exposure times of the mask layer are adjusted according to the fitting curve in a zoned mode, and the mask layer is subjected to modification treatment in a zoned mode so as to adjust the ion implantation resistance of the mask layer in a zoned mode;
s250, implanting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is implanted into the semiconductor wafer exposed by the mask layer to form a second doping region of the second doping type, and part of the second type of dopant is implanted into the first doping region covered by the mask layer to adjust the doping concentration of the first doping region so as to adjust the electrical property of the semiconductor device;
The method comprises the steps of adjusting the exposure times of mask layers in different areas to enable the electrical properties of the same semiconductor device in different areas of the same semiconductor wafer to be consistent so as to eliminate the difference of the electrical properties of the same semiconductor device in different areas of the same semiconductor wafer, or adjusting the exposure times of the mask layers in different areas to enable the electrical properties of the same semiconductor device in different areas of the same semiconductor wafer to be different so as to form the semiconductor device with different electrical properties in different areas of the same semiconductor wafer.
Further, the fitted curve of the electrical property of the semiconductor device and the exposure times of the mask layer includes an adjustment region in which the electrical property changes with the increase of the exposure times and a stable region close to a stable value. Fig. 7 shows a fitted curve between the threshold voltage of the semiconductor device and the number of exposure times, and as shown in fig. 7, the fitted curve includes an adjustment region where the threshold voltage (absolute value) of the semiconductor device decreases with an increase in the number of exposure times, and a stable region near a stable value. That is, as the number of exposure times increases, the threshold voltage (absolute value) of the semiconductor device gradually decreases and then becomes stable.
Fig. 8 shows a fitted curve between the drain saturation current and the number of exposure times of the semiconductor device, and as shown in fig. 8, the fitted curve between the drain saturation current (absolute value) and the number of exposure times of the semiconductor device includes an adjustment region that rises with an increase in the number of exposure times, and a stable region that approaches a stable value. That is, as the number of exposure times increases, the drain saturation current (absolute value) of the semiconductor device gradually increases and then becomes stable.
In the above embodiment, in order to eliminate the difference of the electrical properties of the same semiconductor device in different regions of the semiconductor wafer, the doping concentrations of the first doped regions of the different regions are respectively adjusted by modifying the second mask layer PR2 of the different regions to different extents, so as to eliminate the difference of the doping concentrations of the body regions (first doped regions) in the different regions of the same semiconductor wafer.
In other embodiments, the semiconductor wafer may be divided into a plurality of regions, and the doping concentration of the body region (the first doping region) of the same semiconductor wafer is controlled in regions to form semiconductor devices with different electrical properties in different regions of the same semiconductor wafer.
In the above embodiments, the semiconductor wafer as a whole is divided into regions, and the semiconductor wafer further includes a plurality of basic operation units (shots), each of which includes a plurality of chips (chips), each of which includes a plurality of semiconductor devices. The division of the area may be further performed for each chip (chip).
Fig. 9 shows a region division form of a conductor substrate in another embodiment of the present application, and as shown in fig. 9, a semiconductor wafer 30 is composed of a plurality of identical basic operation units 30-1, each of which includes a plurality of identical chips (chips) 30-2, and each of the chips (chips) 30-2 includes a plurality of semiconductor devices 30a. The present embodiment divides the chip (chip) 30-2 into a plurality of regions. In the present embodiment, for example, the chip (chip) 30-2 is divided to form a first region 30-2a, a second region 30-2b, a third region 30-2c, and a fourth region 30-2d. The size and number of the plurality of areas may be set as needed, and the position distribution of the plurality of areas may be arbitrarily set as needed, which is not limited in this embodiment.
Further, the number of exposure times of each of the plurality of areas may be set as needed, which is not limited by the present embodiment. In one embodiment, the doping concentrations of the first doping regions in the first region 30-2a, the second region 30-2b, the third region 30-2c and the fourth region 30-2d are sequentially reduced. The present embodiment divides one chip (chip) 30-2 into a plurality of regions, and adjusts the doping concentration of the first doping region of the chip (chip) 30-2 by the divided regions to form semiconductor devices having different electrical properties in the same chip (chip) 30-2.
The unexpected technical effects of the application are:
According to the application, the same mask layer is subjected to regional modification treatment, so that the ion implantation resistance of the mask layer is adjusted in regions, the doping concentrations of the first doping regions of different regions are respectively adjusted, and the regional control of the doping concentrations of the first doping regions of the same semiconductor wafer is realized on the premise of not increasing photoetching and ion implantation steps.
In the process of forming the second doped region, the application realizes the adjustment of the doping concentration of the first doped region without adding extra photoetching and ion implantation steps.
The mask layer is a photoresist mask layer, and the ion implantation resistance of the mask layer is controlled by controlling the exposure time of the mask layer, so that the ion implantation resistance of the mask layer is controlled conveniently.
The single exposure time of the light beam is fixed, the exposure times of the mask layer are controlled, the ion implantation resistance of the mask layer is further controlled, and the corresponding relation between the exposure times of the mask layer and the electrical property of the semiconductor device is obtained, so that the electrical property of the semiconductor device is conveniently optimized.
The application enables the doping concentration of the first doping region of different regions to be consistent by controlling the ion implantation resistance of the mask layer in different regions so as to eliminate the difference of the electrical properties of the same semiconductor device in different regions of the same semiconductor wafer.
The application controls the ion implantation resistance of the mask layer in different areas to ensure that the doping concentration of the first doping areas in different areas is different so as to form semiconductor devices with different electrical properties in different areas of the same semiconductor wafer.
Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (9)
1. A method of fabricating a semiconductor device, comprising:
Dividing a semiconductor wafer into a plurality of regions;
Selectively implanting a first type of dopant into the semiconductor wafer to form a first doped region of a first doping type in the semiconductor wafer;
Forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doped region;
modifying the mask layer in regions to adjust the ion implantation resistance of the mask layer in regions, and
Implanting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is implanted into the semiconductor wafer exposed by the mask layer to form a second doped region of the second doping type, and part of the second type of dopant is implanted into the first doped region covered by the mask layer to adjust the doping concentration of the first doped region;
The mask layer is a photoresist mask, and is subjected to modification treatment by exposing the mask layer with a light beam corresponding to a photosensitive wavelength of the mask layer.
2. The method of claim 1, wherein the ion implantation resistance of the mask layer is controlled by adjusting the length of exposure time of the mask layer when the mask layer is modified by exposing the mask layer with a light beam.
3. The method of claim 1, wherein when the mask layer is modified by exposing the mask layer with a light beam, the single exposure time of the light beam is constant, the ion implantation resistance of the mask layer is related to the exposure times of the mask layer, and the ion implantation resistance of the mask layer is controlled by adjusting the exposure times of the mask layer.
4. A method according to claim 3, wherein when the mask layer is modified by exposing the mask layer with a light beam, the ion implantation resistance of the mask layer gradually decreases and then becomes stable as the number of exposure times of the mask layer increases.
5. A method for adjusting electrical properties of a semiconductor device, wherein the electrical properties of the semiconductor device are related to the number of exposures of a mask layer, the method comprising:
acquiring a fitting curve of the electrical property of the semiconductor device and the exposure times of the mask layer;
Forming a first doping region of a first doping type in a semiconductor wafer;
forming a patterned mask layer on a semiconductor wafer, wherein the mask layer covers the first doped region;
The mask layer is modified by adopting a light beam exposure mask layer corresponding to the photosensitive wavelength of the mask layer, the single exposure time of the light beam is constant, the exposure times of the mask layer are adjusted in a zoned mode according to the fitting curve, and the mask layer is modified in a zoned mode so as to adjust the ion implantation resistance of the mask layer in a zoned mode;
and implanting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is implanted into the semiconductor wafer exposed by the mask layer to form a second doped region of the second doping type, and part of the second type of dopant is implanted into the first doped region covered by the mask layer to adjust the doping concentration of the first doped region so as to adjust the electrical property of the semiconductor device.
6. The method of claim 5, wherein the fitted curve of the electrical property of the semiconductor device and the number of exposures of the mask layer includes an adjustment region in which the electrical property changes with increasing number of exposures and a stability region in which the stability value is near.
7. The method of claim 5, wherein the number of exposures of the mask layer in different regions is adjusted such that the electrical properties of the same semiconductor device in different regions of the same semiconductor wafer are uniform to eliminate differences in the electrical properties of the same semiconductor device in different regions of the same semiconductor wafer.
8. The method of claim 5, wherein the number of exposures of the mask layer in different regions is adjusted such that there is a difference in electrical properties of the same semiconductor device in different regions of the same semiconductor wafer to form semiconductor devices with different electrical properties in different regions of the same semiconductor wafer.
9. A semiconductor device formed by the method of any of claims 1 to 8, the semiconductor device comprising:
A semiconductor wafer comprising a plurality of regions;
a first doped region of a first doping type in the semiconductor wafer, and
A second doped region of a second doping type in the semiconductor wafer;
The second doped region is formed while the doping concentration of the first doped region is adjusted, and the doping concentrations of the first doped regions in different regions are the same or different.
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