CN119208288A - Glass substrate and method for manufacturing the same - Google Patents
Glass substrate and method for manufacturing the same Download PDFInfo
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- CN119208288A CN119208288A CN202411187969.4A CN202411187969A CN119208288A CN 119208288 A CN119208288 A CN 119208288A CN 202411187969 A CN202411187969 A CN 202411187969A CN 119208288 A CN119208288 A CN 119208288A
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- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
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- H01L21/486—Via connections through the substrate with or without pins
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
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Abstract
本申请公开一种玻璃基板及其制造方法，涉及半导体封装技术领域。玻璃基板的制造方法包括：玻璃芯板开孔、形成第一种子层、形成第一掩膜、通孔金属化、去除第一掩膜和被第一掩膜覆盖的第一种子层、塞孔并形成第一树脂层、形成第二种子层、形成第二掩膜、形成内线路层、去除第二掩膜和被第二掩膜覆盖的第二种子层、形成第二树脂层、在第一表面和第二表面的第二树脂层上开设贯通孔、形成第三种子层、形成第三掩膜、形成线路层、去除第三掩膜和被第三掩膜覆盖的第三种子层、重复至少一次步骤形成第二树脂层至步骤去除第三掩膜和被第三掩膜覆盖的第三种子层、制作阻焊层、植球，以实现减小基板的翘曲，提高基板的可靠性。
The present application discloses a glass substrate and a manufacturing method thereof, and relates to the field of semiconductor packaging technology. The manufacturing method of the glass substrate includes: opening a hole in a glass core plate, forming a first seed layer, forming a first mask, metallizing a through hole, removing the first mask and the first seed layer covered by the first mask, plugging the hole and forming a first resin layer, forming a second seed layer, forming a second mask, forming an inner circuit layer, removing the second mask and the second seed layer covered by the second mask, forming a second resin layer, opening a through hole on the second resin layer on the first surface and the second surface, forming a third seed layer, forming a third mask, forming a circuit layer, removing the third mask and the third seed layer covered by the third mask, repeating at least once the steps of forming the second resin layer to removing the third mask and the third seed layer covered by the third mask, making a solder resist layer, and planting balls, so as to reduce the warping of the substrate and improve the reliability of the substrate.
Description
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a glass substrate and a manufacturing method thereof.
Background
In the prior art, the organic substrate is generally beneficial to realizing the interconnection of the packaged chip and the device with the PCB, so as to provide a data exchange path for the chip while supporting and protecting the chip.
Today, the technologies of network and information technology develop at a high speed, such as AI, 5G, cloud computing, automatic driving and the like, and people have explosive growth on data demands, and requirements of data processing, data transmission and data storage on chips are continuously improved. In order to meet the requirement of huge amount of data processing on chips, the development of global integrated circuit technology at present improves the data processing capability, mainly follows two paths, namely, one is to utilize advanced technology nodes to continuously advance an integrated circuit to a large-size SOC (System on Chip) direction according to moore's law, the other technical path is to package chips with different IP, different technology nodes and different materials in a package body through three-dimensional heterogeneous integration, and the data processing capability of single package is improved through a high-density three-dimensional heterogeneous integration technology. The larger the SOC size, the more chips that are integrated in a single package, and the larger the substrate size that is required. As the substrate size increases, the substrate warpage increases significantly, with an increasing impact on the packaging process and reliability of the packaged device.
Disclosure of Invention
The application aims to provide a glass substrate and a manufacturing method thereof, which are used for reducing the warping of the substrate and improving the bonding force between an inner circuit layer and a glass core plate so as to improve the reliability of the substrate.
In order to achieve the above object, the present application provides the following technical solutions:
A glass substrate, comprising:
a glass core plate having a plurality of through holes, the glass core plate including a first surface and a second surface opposite in a thickness direction thereof;
A first seed layer covering an inner wall of the through hole and a surrounding area of an orifice of the through hole;
A metal layer covering the first seed layer, wherein a part of the metal layer located in the periphery area of the orifice of the through hole forms an annular metal pad;
the hole plugging material is filled in the through hole;
a first resin layer, the first resin layer being provided on both the first surface and the second surface of the glass core plate, and the annular metal pad being uncovered by the first resin layer, the annular metal pad being either level with the first resin layer or higher than the first resin layer;
The second seed layer and the inner circuit layer are stacked, the second seed layer is positioned on one side surface of the first resin layer, which is away from the glass core plate, and the inner circuit layer covers one side surface of the second seed layer, which is away from the glass core plate;
The multi-layer combined structure comprises a second resin layer, a third seed layer and a circuit layer which are sequentially arranged along the direction deviating from the glass core plate, wherein the second resin layer is provided with a through hole, and the third seed layer and the circuit layer are laminated on one side of the second resin layer deviating from the glass core plate;
The solder mask is arranged on one side of the multilayer combined structure, which is away from the glass core plate;
The solder balls are arranged on the solder mask layer, and the bottoms of the solder balls penetrate through the solder mask layer to be in contact with the outermost circuit layer.
In one implementation, the plug hole material is resin, the resin comprises ABF, RCC and/or photosensitive dry film insulating layer material, or the plug hole material is the same as the material of the first resin layer, or,
The plug hole material is metal, and the metal comprises copper, tungsten and/or titanium.
In one implementation, the first seed layer, the second seed layer, and/or the third seed layer comprises at least one sub-metal layer, or,
The first seed layer, the second seed layer and/or the third seed layer comprise a plurality of sub-metal layers, and the materials of the sub-metal layers are different.
In one implementation, the material of the sub-metal layer is titanium, copper or tungsten.
In one implementation, the solder balls include a chip solder ball and a substrate solder ball, the chip solder ball is disposed on a solder mask on one side of the glass chip, the substrate solder ball is disposed on a solder mask on the other side of the glass chip, the chip solder ball is used for bonding with a chip, and the substrate solder ball is used for bonding with a printed circuit board;
and/or one side of the substrate solder ball, which is away from the glass core plate, is a spherical surface.
In the glass substrate provided by the application, the plugging material is not a traditional vacuum plugging or a traditional vacuum silk screen printing plugging of liquid ink, but a resin or a metal plugging is adopted, so that the reliability of the glass substrate is improved. In addition, the high-rigidity supporting structure provided by the glass core plate for the integral glass substrate forms high-strength bonding of the metal layer and the glass core plate by utilizing high bonding force of the hole plugging resin for the glass core plate and the inner metal circuit, and solves the problem of poor direct bonding force between the metal layer and the surface of the glass core plate. The high-rigidity supporting structure provided by the glass core plate for the whole glass substrate can reduce the whole warping degree of the substrate, further avoid bridging of solder balls during flip-chip, avoid the conditions that short circuits are caused, the solder balls of the chip part cannot be welded with the bonding pads of the substrate to form open circuits, and further avoid the problems that larger stress is generated between the chip and the substrate due to serious warping of the substrate, and the stress changes produce solder ball cracking, substrate cracking, chip cracking and the like.
A method for manufacturing a glass substrate, comprising:
A glass core plate is perforated, a plurality of through holes are formed in the glass core plate, and the glass core plate is provided with a first surface and a second surface which are opposite;
forming a first seed layer on the surface of the glass core plate provided with the through holes;
Forming a first mask on the surface of the structure formed in the previous step, wherein the first mask covers the first surface and the second surface of the structure formed in the previous step except for the inner wall of the through hole and other parts of the surrounding areas of the orifice of the through hole;
Through hole metallization, forming a metal layer on the inner wall of the through hole of the glass core plate and the surrounding area of the hole opening of the through hole, and forming an annular metal bonding pad on the metal layer of the surrounding area of the hole opening of the through hole;
removing the first mask and the first seed layer covered by the first mask;
Filling resin or metal in the through holes of the glass core plate, and pressing the hole filling resin on the first surface and the second surface of the glass core plate to form a first resin layer on the first surface and the second surface of the glass core plate;
thinning the first resin layer so that the annular metal pad is exposed out of the first resin layer;
Forming a second seed layer on the surfaces of the first resin layers on two sides of the glass core plate;
forming a second mask on the first surface and the second surface of the structure formed in the previous step, wherein the second mask has a hollowed-out structure;
forming an inner circuit layer in the hollow structure of the second mask;
Removing the second mask and the second seed layer covered by the second mask;
Forming a second resin layer, and laminating resin on the first surface and the second surface of the structure formed in the previous step to form the second resin layer;
forming through holes in the second resin layers on the first surface and the second surface;
forming a third seed layer on the surfaces of the second resin layers on two sides of the glass core plate;
forming a third mask on the first surface and the second surface of the structure formed in the previous step, wherein the third mask has a hollowed-out structure;
Forming a circuit layer in the hollowed-out structure of the third mask;
removing the third mask and the third seed layer covered by the third mask;
repeating the step at least once to form a second resin layer until the step removes the third mask and the third seed layer covered by the third mask;
Manufacturing a solder mask layer on the first surface and the second surface of the structure formed in the previous step, wherein the solder mask layer is provided with a connecting hole corresponding to the circuit layer;
and implanting balls, wherein the first surface and/or the second surface of the structure formed in the previous step are/is welded balls.
In one implementation, the forming the first seed layer includes forming the first seed layer on the surface of the glass core plate with the through holes by deposition, and/or,
The forming of the second seed layer comprises forming the second seed layer on the surfaces of the first resin layers on two sides of the glass core plate by utilizing a deposition mode, and/or,
The forming of the third seed layer comprises the step of forming the third seed layer on the surfaces of the second resin layers on two sides of the glass core plate in a deposition mode.
In one implementation mode, the step hole plugging is specifically that resin is filled in the through hole of the glass core plate, the resin is pressed on the first surface and the second surface of the glass core plate, so that the resin fills the through hole of the glass core plate, a first resin layer is formed on the first surface and the second surface of the glass core plate, and the annular metal bonding pad is exposed out of the first resin layer.
In one implementation, the annular metal pad is level with the first resin layer height or the annular metal pad is higher than the first resin layer after the step of thinning the first resin layer.
In one implementation, the first mask is formed on the surface of the structure formed in the previous step, specifically, the first mask is formed on the surface of the structure formed in the previous step by adopting a way of manufacturing an electroplating mask through photolithography, and/or,
The second mask is formed on the first surface and the second surface of the structure formed in the previous step, specifically, the second mask is formed on the first surface and the second surface of the structure formed in the previous step by adopting a photoetching manufacturing method for manufacturing an electroplating mask.
In the glass substrate formed by the method for manufacturing the glass substrate, the plugging material is not a traditional vacuum plugging hole or a traditional vacuum silk screen printing plugging hole of liquid ink, but a resin or a metal plugging hole is adopted, so that the reliability of the glass substrate is improved. In addition, the high-rigidity supporting structure provided by the glass core plate for the integral glass substrate forms high-strength bonding of the metal layer and the glass core plate by utilizing high bonding force of the hole plugging resin for the glass core plate and the inner metal circuit, and solves the problem of poor direct bonding force between the metal layer and the surface of the glass core plate. The high-rigidity supporting structure provided by the glass core plate for the whole glass substrate can reduce the whole warping degree of the substrate, further avoid bridging of solder balls during flip-chip, avoid the conditions that short circuits are caused, the solder balls of the chip part cannot be welded with the bonding pads of the substrate to form open circuits, and further avoid the problems that larger stress is generated between the chip and the substrate due to serious warping of the substrate, and the stress changes produce solder ball cracking, substrate cracking, chip cracking and the like.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a flow chart of a method for manufacturing a glass substrate according to an embodiment of the present application;
FIG. 2 is a cross-sectional view of a glass core plate provided by an embodiment of the present application after a through hole is formed;
FIG. 3 is a top view of a glass core plate according to an embodiment of the present application with through holes;
FIG. 4 is a schematic diagram of a first seed layer according to an embodiment of the present application;
FIG. 5 is an enlarged view of a portion of area A of FIG. 4;
FIG. 6 is a schematic diagram of a first mask formed according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a through-hole metallization process according to an embodiment of the present application;
FIG. 8 is a schematic diagram of the embodiment of the present application after removing the first mask;
FIG. 9 is a cross-sectional view of an embodiment of the present application after removal of a first seed layer;
FIG. 10 is a top view of the first seed layer covered by the first mask after removal according to the embodiment of the present application;
FIG. 11 is a schematic diagram of a post-plugging step according to an embodiment of the present application;
FIG. 12 is a schematic diagram of a hole filling step according to another embodiment of the present application;
FIG. 13 is a cross-sectional view of the thinned first resin layer according to the embodiment of the present application;
FIG. 14 is a top view of the thinned first resin layer according to the embodiment of the present application;
FIG. 15 is a schematic diagram of a second seed layer formed according to an embodiment of the present application;
FIG. 16 is a schematic diagram of a second mask formed according to an embodiment of the present application;
Fig. 17 is a schematic diagram of an embodiment of the present application after forming an inner circuit layer;
FIG. 18 is a schematic diagram of the embodiment of the present application after removing the second mask;
FIG. 19 is a schematic diagram of an embodiment of the present application after removing the second seed layer covered by the second mask;
FIG. 20 is a schematic view of a second resin layer formed according to an embodiment of the present application;
FIG. 21 is a schematic view of a second resin layer with through holes according to an embodiment of the present application;
FIG. 22 is a schematic diagram of a third seed layer formed according to an embodiment of the present application;
FIG. 23 is a schematic diagram of a third mask according to an embodiment of the present application;
fig. 24 is a schematic diagram of a circuit layer formed according to an embodiment of the present application;
FIG. 25 is a schematic diagram of the embodiment of the present application after removing the third mask;
FIG. 26 is a schematic diagram of a third seed layer covered by a third mask after removal according to an embodiment of the present application;
Fig. 27 is a schematic diagram of a multi-layer circuit layer formed according to an embodiment of the present application;
FIG. 28 is a schematic diagram of a solder mask layer according to an embodiment of the present application;
Fig. 29 is a schematic view of a glass substrate according to an embodiment of the present application.
Reference numerals:
1-glass core board, 1 a-through hole, 2-first seed layer, 3-first mask, 4-metal layer, 4 a-annular metal pad, 5-first resin layer, 6-second seed layer, 7-second mask, 8-inner circuit layer, 8 a-orifice pad, 9-second resin layer, 9 a-through hole, 10-third seed layer, 11-third mask, 12-circuit layer, 13-solder resist layer, 14-chip solder ball, 15-substrate solder ball.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.
In the description of the present application, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the description of the present application, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or in communication between two elements or in an interaction relationship between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the prior art, along with explosive growth of data demands, requirements of data processing, data transmission and data storage on chips are continuously improved, the size of an organic substrate is increased, the warpage of the substrate is obviously increased, bridging of solder balls is easily caused when a flip chip is arranged, short circuits are formed, and partial solder balls of the chip cannot be welded with bonding pads of the substrate, so that open circuits are formed. In addition, the serious substrate warpage can also generate larger stress between the chip and the substrate, and when the temperature is changed, the stress change can generate reliability problems such as solder ball cracking, substrate cracking, chip cracking and the like.
In view of the above, as shown in fig. 29, an embodiment of the present application provides a glass substrate that can be manufactured by using any of the following manufacturing methods of glass substrates. The glass substrate comprises a glass core plate 1, a first seed layer 2, a metal layer 4, a hole plugging material, a first resin layer 5, a second seed layer 6, an inner circuit layer 8, a multi-layer combined structure, a solder mask layer 13 and solder balls. Wherein, the first seed layer 2, the metal layer 4, the plugging material, the first resin layer 5, the second seed layer 6, the inner circuit layer 8, the multi-layer composite structure and the solder mask layer 13 are all symmetrically arranged on two sides of the glass core plate 1.
Wherein the glass core sheet 1 has a plurality of through holes 1a, and the glass core sheet 1 includes a first surface and a second surface opposite in a thickness direction thereof. The first surface may be an upper surface and the second surface may be a lower surface. Through-hole 1a penetrates through the thickness of glass core plate 1, one orifice of through-hole 1a is located on the first surface, and the other orifice of through-hole 1a is located on the second surface. The first seed layer 2 covers the inner wall of the through hole 1a of the glass core plate 1 and the aperture surrounding area of the through hole 1a, that is, the aperture surrounding area on the first surface and the aperture surrounding area on the second surface, both of which are covered with the first seed layer 2.
The metal layer 4 covers the first seed layer 2, and a portion of the metal layer 4 located at a region around the aperture of the via hole 1a forms a ring-shaped metal pad 4a. The annular metal pad 4a is used for connecting the inner wiring layer 8. The metal layer 4 may be a single layer of metal, and the material of the single layer of metal may be copper, tungsten, titanium, or other metal. Of course, the metal layer 4 may also include multiple sub-metal layers, and the materials of the multiple sub-metal layers may be the same or different, for example, the materials of the sub-metal layers may be copper, tungsten or titanium. The thicknesses of the plurality of sub-metal layers may be the same or different.
The via hole 1a is filled with a via hole material, which may be resin or metal. In the case of filling the metal into the through hole 1a, the material of the filled metal may be copper, tungsten, titanium, or the like. In the case of filling the resin in the through hole 1a, the filled resin may include ABF (ABFAjinomoto Build-up Film), RCC (Resin Coated Copper), and/or a photosensitive dry Film insulating layer material. In addition, the material of the plug hole is the same as that of the first resin layer 5, so that the resin is filled into the through hole while the first resin layer 5 is formed, and the processing technology is simplified.
The first surface and the second surface of the glass core plate 1 are each provided with a first resin layer 5, and the annular metal pads 4a are not covered with the first resin layer 5. I.e. the annular metal pad 4a is exposed to the first resin layer 5, i.e. the annular metal pad 4a is not covered by the first resin layer 5, so that the annular metal pad 4a is connected with the inner circuit layer 8. The annular metal pad 4a is flush with the first resin layer 5 in height or the annular metal pad 4a is higher than the first resin layer 5, and the annular metal pad 4a is slightly higher than the first resin layer 5, so that the inner circuit layer is manufactured on the whole flat surface, the requirement of hole filling electroplating is avoided, and the process is simple and convenient.
The second seed layer 6 and the inner circuit layer 8 are stacked, the second seed layer 6 is located on a side surface of the first resin layer 5 facing away from the glass core plate 1, and the inner circuit layer 8 covers a side surface of the second seed layer 6 facing away from the glass core plate 1. The portion of the inner wiring layer 8 opposite to the through hole 1a and its surrounding area is an aperture pad 8a, and the aperture pad 8a is used for connecting the wiring layer 12.
The multi-layer composite structure is disposed on a side of the inner circuit layer 8 facing away from the glass core plate 1, and when a plurality of multi-layer composite structures are disposed on the upper side or the lower side of the glass core plate 1, the plurality of multi-layer composite structures are sequentially stacked. Or a multi-layered combination structure may be provided when the upper or lower side of the glass core plate 1 is provided. The multilayer composite structure comprises a second resin layer 9, a third seed layer 10 and a circuit layer 12 which are sequentially arranged along the direction away from the glass core plate 1, wherein the second resin layer 9 is provided with a through hole 9a, and the third seed layer 10 and the circuit layer 12 are laminated on one side of the second resin layer 9 away from the glass core plate 1. The plurality of through holes 9a may be respectively opposite to the plurality of orifice pads 8a to facilitate connection of the orifice pads 8a with the wiring layer 12 through the through holes 9a
The solder mask layer 13 is arranged on the side of the multilayer composite structure facing away from the glass core plate 1. The solder resist layer 13 has connection holes corresponding to the wiring layer 12 for connection with solder balls. The solder balls are arranged on the solder mask layer. The solder balls may include chip solder balls 14 and substrate solder balls 15, wherein the chip solder balls 14 are disposed on the solder mask 13 on one side of the glass chip, the substrate solder balls 15 are disposed on the solder mask 13 on the other side of the glass chip, the chip solder balls 14 are used for bonding with the chip, and the substrate solder balls 15 are used for bonding with the printed circuit board.
In the glass substrate, the plugging material does not adopt the traditional vacuum plugging or vacuum silk screen printing plugging of liquid ink, but adopts resin or metal plugging, so that the reliability of the glass substrate is improved. In addition, the high-rigidity supporting structure provided by the glass core plate for the integral glass substrate forms high-strength bonding of the metal layer and the glass core plate by utilizing high bonding force of the hole plugging resin for the glass core plate and the inner metal circuit, and solves the problem of poor direct bonding force between the metal layer and the surface of the glass core plate. The glass core plate 1 can reduce the warping degree of the whole substrate for the high-rigidity supporting structure provided by the whole glass substrate, further avoid bridging of solder balls during flip-chip, avoid short circuit and the situation that partial solder balls of the chip cannot be welded with bonding pads of the substrate to form open circuits, and further avoid the problems that larger stress is generated between the chip and the substrate due to serious substrate warping, and the stress changes produce solder ball cracking, substrate cracking, chip cracking and the like.
The chip solder ball 14 is used for bonding with a chip, and a side of the chip solder ball 14 facing away from the glass core plate 1 is provided with a plane so as to facilitate bonding with the chip.
The substrate solder ball 15 is used for bonding with a printed circuit board, and one side of the substrate solder ball 15 away from the glass core plate 1 is spherical, so that bonding with the printed circuit board is facilitated.
In the above technical solution, the first resin layer 5 may include ABF (ABF: ajinomoto Build-up Film), RCC and/or photosensitive dry Film insulating layer material. The second resin layer 9 may include ABF (ABF: ajinomoto Build-up Film), RCC, and/or photosensitive dry Film insulating layer material.
The first seed layer 2, the second seed layer 6 and/or the third seed layer 10 comprise at least one sub-metal layer. That is, the first seed layer 2, the second seed layer 6 and/or the third seed layer 10 may be a single layer of metal, and the material of the single layer of metal may be copper, tungsten, titanium or other metal. Of course, the first seed layer 2, the second seed layer 6 and/or the third seed layer 10 may also include multiple sub-metal layers, and the materials of the multiple sub-metal layers may be the same or different, for example, the materials of the sub-metal layers may be copper, tungsten or titanium. The thicknesses of the plurality of sub-metal layers may be the same or different.
Referring to fig. 1, an embodiment of the present application further provides a method for manufacturing a glass substrate, which includes:
S1, perforating a glass core plate 1, wherein a plurality of through holes 1a are formed in the glass core plate 1, and the glass core plate 1 is provided with a first surface and a second surface which are opposite.
As shown in fig. 2 and 3, specifically, the glass core plate 1 has opposite first and second surfaces in the thickness direction, both of which are perpendicular to the thickness direction of the glass core plate 1. A plurality of through holes 1a penetrating through the thickness of the glass core plate 1 are formed in the glass core plate 1, one orifice of the through hole 1a is positioned on the first surface, and the other orifice of the through hole 1a is positioned on the second surface.
In this step, holes may be formed by laser.
S2, forming a first seed layer 2, and forming the first seed layer 2 on the surface of the glass core plate 1 provided with the through holes 1 a;
As shown in fig. 4 and 5, a first seed layer 2 is formed on the surface of the glass core plate 1 perforated in step S1, the first seed layer 2 covering the first surface, the second surface, and the inner wall of the through hole 1a of the glass core plate 1. Alternatively, the first seed layer 2 may be formed by deposition, electroplating, or the like.
Thus, a regular, dense, smooth first seed layer 2 is formed on the surface of the glass core plate 1, which has a good light brightness and level distribution, so that the adhesion between the electrolyte and the metal is enhanced and the surface uniformity of the deposit is promoted.
S3, forming a first mask 3 on the surface of the structure formed in the previous step, wherein the first mask 3 covers the first surface and the second surface of the structure formed in the previous step except the inner wall of the through hole 1a and other parts of the surrounding area of the orifice of the through hole 1 a;
As shown in fig. 6, the first mask 3 is formed on the surface of the structure formed in step S2, and specifically, the first mask 3 is formed on both the first surface and the second surface of the structure formed in step S2. The first surface may be an upper surface, and the second surface may be a lower surface. The first mask 3 covers the other parts of the first surface and the second surface of the structure formed in the previous step except the inner wall of the through hole 1a and the surrounding area of the orifice of the through hole 1a, namely, the first mask 3 has a hollowed-out structure, and the hollowed-out structure of the first mask 3 is opposite to the orifice of the through hole 1a and the surrounding area thereof, so that the inner wall of the through hole 1a and the surrounding area of the orifice of the through hole 1a are not covered by the first mask 3.
In this step, a first mask 3 may be formed on the surface of the structure formed in the previous step by using a photolithography method to manufacture a plating mask, specifically, the first surface and the second surface of the structure formed in the previous step are pressed with dry films, and then exposure and development are sequentially performed to finally form the first mask 3. Wherein, the dry film is made of photosensitive polymer material. Of course, the first mask 3 may be formed in other ways, which are not limited herein.
S4, through hole metallization, wherein a metal layer 4 is formed on the inner wall of the through hole 1a of the glass core plate 1 and the surrounding area of the orifice of the through hole 1a, and an annular metal bonding pad 4a is formed on the metal layer 4 in the surrounding area of the orifice of the through hole 1 a;
As shown in fig. 7, in this step, the metal layer 4 is formed on the inner wall of the through hole 1a of the glass core plate 1 and the area around the orifice of the through hole 1a, and specifically, the metal layer 4 may be formed on the inner wall of the through hole 1a and the area around the orifice of the through hole 1a by electroplating, deposition, or the like. The portion of the metal layer 4 located around the aperture of the through-hole 1a is an annular metal pad 4a for connecting the inner wiring layer 8.
In this step, the metal layer 4 may be a single layer of metal, and the material of the single layer of metal may be copper, tungsten, titanium, or other metal. Of course, the metal layer 4 may also include multiple sub-metal layers, and the materials of the multiple sub-metal layers may be the same or different, for example, the materials of the sub-metal layers may be copper, tungsten or titanium. The thicknesses of the plurality of sub-metal layers may be the same or different.
S5, removing the first mask 3 and the first seed layer 2 covered by the first mask 3;
As shown in fig. 8 to 10, the first mask 3 and the first seed layer 2 covered by the first mask 3 are removed, leaving the metal layer 4 and the first seed layer 2 covered by the metal layer 4.
In this step, the first mask 3 and the first seed layer 2 covered by the first mask 3 may be removed in two steps, i.e. the first mask 3 is removed first and then the first seed layer 2 covered by the first mask 3 is removed. Specifically, the first mask 3 may be directly stripped by a stripping method, and then the first seed layer 2 covered by the first mask 3 may be removed by wet etching or laser etching.
S6, plugging holes and forming a first resin layer 5, filling resin or metal in the through holes 1a of the glass core plate 1, pressing resin on the first surface and the second surface of the glass core plate 1 to form the first resin layer 5 on the first surface and the second surface of the glass core plate 1, and exposing the annular metal bonding pads 4a to the first resin layer 5;
As shown in fig. 11, the through hole 1a is filled with resin in this step, that is, the through hole 1a is filled with resin. Or as shown in fig. 12, the through hole 1a is filled with metal in this step, that is, the through hole 1a is filled with metal. As shown in fig. 11, resin is pressed at the first and second surfaces of the glass core plate 1 to form a first resin layer 5 at the first and second surfaces of the glass core plate 1, and the annular metal pads 4a are exposed to the first resin layer 5.
In the case of filling the metal in the through hole 1a, the first resin layer 5 may be formed by filling the metal in the through hole 1a and then pressing the resin against the first surface and the second surface of the glass core plate 1. The material of the filled metal and the material of the metal layer 4 may be the same or different, and the material of the filled metal may be copper, tungsten, titanium, or the like.
In the case of filling the resin into the through-holes 1a, the filling of the resin may be completed simultaneously with the first resin layer 5, i.e., pressing the resin against the first and second surfaces of the glass core sheet 1, so that the resin fills the through-holes 1a of the glass core sheet 1 while forming the first resin layer 5 on the first and second surfaces of the glass core sheet 1. The filled resin may include ABF (ABF: ajinomoto Build-up Film), RCC (Resin Coated Copper), and/or photosensitive dry Film insulating layer material.
S6', thinning the first resin layer 5 so that the annular metal pad is exposed out of the first resin layer.
The annular metal pad 4a is exposed from the first resin layer 5, i.e. the annular metal pad 4a is not covered by the first resin layer 5, so as to facilitate connection of the annular metal pad 4a with the inner circuit layer 8. The first resin layer 5 may be flush with the annular metal pad 4a, or the annular metal pad 4a may be slightly higher than the first resin layer 5.
As shown in fig. 13 and 14, since the thickness of the first resin layer 5 is not controllable during the process of laminating the resin, the step S6 of plugging the holes and forming the first resin layer 5 further includes the step S6' of thinning the first resin layer 5 so that the annular metal pads are exposed to the first resin layer, and polishing the surface of the first resin layer 5 may be performed in the further step. The thickness of the thinned first resin layer 5 is 3 μm-5 μm, specifically, the first resin layer 5 may be thinned by using a grinding wheel, or the first resin layer 5 may be thinned by using a chemical mechanical Polishing method, and further, CMP (CHEMICAL MECHANICAL Polishing) may be performed after thinning to remove micro scratches on the surface. The thickness of the thinned first resin layer 5 is, for example, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm.
S7, forming a second seed layer 6, and forming the second seed layer 6 on the surfaces of the first resin layers 5 on the two sides of the glass core plate 1;
As shown in fig. 15, a second seed layer 6 is formed on the surface of the structure formed in step S7, and specifically, a second seed layer 6 is formed on the surface of the first resin layer 5 of the structure formed in the previous step facing away from the glass core plate 1, and the second seed layer 6 covers the surface of the first resin layer 5 facing away from the glass core plate 1. Alternatively, the second seed layer 6 may be formed by deposition, electroplating, or the like.
S8, forming a second mask 7 on the first surface and the second surface of the structure formed in the previous step, wherein the second mask 7 has a hollowed-out structure;
As shown in fig. 16, the second mask 7 is formed on the surface of the structure formed in step S7, and specifically, the second mask 7 is formed on both the first surface and the second surface of the structure formed in step S7. The first surface may be an upper surface, and the second surface may be a lower surface. The second mask 7 covers the first surface and the second surface of the structure formed in the previous step, the second mask 7 has a hollow structure, and the hollow structure of the second mask 7 is used for forming the inner circuit layer 8.
In this step, a second mask 7 may be formed on the surface of the structure formed in the previous step by using a photolithography method to manufacture a plating mask, specifically, the first surface and the second surface of the structure formed in the previous step are pressed with dry films, and then exposure and development are sequentially performed to finally form the second mask 7. Wherein, the dry film is made of photosensitive polymer material. Of course, the second mask 7 may be formed in other ways, which are not limited herein.
S9, forming an inner circuit layer 8 in the hollow structure of the second mask 7;
As shown in fig. 17, in this step, the inner circuit layer 8 is formed in the hollow structure of the second mask 7, and specifically, the inner circuit layer 8 may be formed in the hollow structure of the second mask 7 by electroplating, deposition, or the like. The portion of the inner wiring layer 8 opposite to the through hole 1a and its surrounding area is an orifice pad 8a for connecting the wiring layer 12. The orifice pad 8a has the same thickness as the other positions of the inner wiring layer 8.
In this step, the material of the inner circuit layer 8 may be copper, tungsten or titanium.
S10, removing the second mask 7 and the second seed layer 6 covered by the second mask 7;
As shown in fig. 18 to 19, the second mask 7 and the second seed layer 6 covered by the second mask 7 are removed, and the inner wiring layer 8 and the second seed layer 6 covered by the inner wiring layer 8 remain.
In this step, the second mask 7 and the second seed layer 6 covered by the second mask 7 may be removed in two steps, i.e. the second mask 7 is removed first and then the second seed layer 6 covered by the second mask 7 is removed. Specifically, the second mask 7 may be peeled off directly by peeling, and then the second seed layer 6 covered by the second mask 7 may be removed by wet etching or laser etching.
S11, forming a second resin layer 9, and pressing resin on the first surface and the second surface of the structure formed in the previous step to form the second resin layer 9;
As shown in fig. 20, the inner circuit layer 8 of the structure formed in the previous step is press-fitted with a resin on the side facing away from the glass core plate 1 to form a second resin layer 9. I.e. the first and second surfaces of the structure formed in the previous step are pressed with resin to form the second resin layer 9.
S12, forming through holes 9a on the second resin layer 9 on the first surface and the second surface;
As shown in fig. 21, a plurality of through holes 9a penetrating the thickness of the second resin layer 9 are formed, and the plurality of through holes 9a may be respectively opposite to the plurality of via pads 8a, so that the via pads 8a are connected to the wiring layer 12 through the through holes 9a. Preferably, the through-holes 9a may be opened in the second resin layer 9 using a laser process.
S13, forming a third seed layer 10, wherein the third seed layer 10 is formed on the surfaces of the second resin layers 9 on two sides of the glass core plate 1;
As shown in fig. 22, a third seed layer 10 is formed on the surface of the structure formed in step S12, specifically, a third seed layer 10 is formed on the surface of the second resin layer 9 of the structure formed in the previous step, which faces away from the glass core plate 1, and the third seed layer 10 is required on both the upper side and the lower side of the structure formed in the previous step, and the third seed layer 10 covers the surface of the second resin layer 9, which faces away from the glass core plate 1. Alternatively, the third seed layer 10 may be formed by deposition, electroplating, or the like.
S14, forming a third mask 11 on the first surface and the second surface of the structure formed in the previous step, wherein the third mask 11 has a hollowed-out structure;
As shown in fig. 23, the third mask 11 is formed on the surface of the structure formed in step S13, and specifically, the third mask 11 is formed on both the first surface and the second surface of the structure formed in step S13. The first surface may be an upper surface, and the second surface may be a lower surface. The third mask 11 covers the first surface and the second surface of the structure formed in the previous step, the third mask 11 has a hollow structure, and the hollow structure of the third mask 11 is used for forming the circuit layer 12.
In this step, a third mask 11 may be formed on the surface of the structure formed in the previous step by using a photolithography method to manufacture a plating mask, specifically, the first surface and the second surface of the structure formed in the previous step are pressed with dry films, and then exposure and development are sequentially performed to finally form the third mask 11. Wherein, the dry film is made of photosensitive polymer material. Of course, the third mask 11 may be formed in other ways, which are not limited herein.
S15, forming a circuit layer 12 in the hollowed-out structure of the third mask 11;
As shown in fig. 24, in this step, the circuit layer 12 is formed in the hollow structure of the third mask 11, and specifically, the circuit layer 12 may be formed in the hollow structure of the third mask 11 by electroplating, deposition, or the like.
In this step, the material of the circuit layer 12 may be copper, tungsten or titanium.
S16 removing the third mask 11 and the third seed layer 10 covered by the third mask 11;
as shown in fig. 25 to 26, the third mask 11 and the third seed layer 10 covered by the third mask 11 are removed, and the wiring layer 12 and the third seed layer 10 covered by the wiring layer 12 remain.
In this step, the third mask 11 and the third seed layer 10 covered by the third mask 11 may be removed in two steps, i.e., the third mask 11 is removed first and then the third seed layer 10 covered by the third mask 11 is removed. Specifically, the third mask 11 may be directly stripped by a stripping method, and then the third seed layer 10 covered by the third mask 11 may be removed by wet etching or laser etching.
S17, repeating the steps at least once to form the second resin layer 9 to remove the third mask 11 and the third seed layer 10 covered by the third mask 11;
as shown in fig. 27, steps S11 to S16 are repeated at least once, thereby manufacturing the multilayer wiring layer 12.
S18, manufacturing a solder mask layer 13 on the first surface and the second surface of the structure formed in the previous step, wherein the solder mask layer 13 is provided with a connecting hole corresponding to the circuit layer 12;
As shown in fig. 28, in this step, the solder resist layer 13 is formed on the first surface and the second surface of the structure formed in the previous step, that is, the solder resist layer 13 is formed on the circuit layer 12 on the upper and lower outermost layers of the structure formed in the previous step, and the solder resist layer 13 has connection holes corresponding to the circuit layer 12 for connection with solder balls.
And S19, implanting balls, wherein the first surface and/or the second surface of the structure formed in the previous step are/is welded balls.
Specifically, the first surface and the second surface of the structure formed in the previous step may be provided with a chip solder ball 14 and a substrate solder ball 15, respectively, where the chip solder ball 14 is used for bonding with a chip, and the substrate solder ball 15 is used for bonding with a printed circuit board.
As shown in fig. 29, the first surface of the structure formed in the previous step is provided with the chip solder balls 14, the second surface of the structure formed in the previous step is provided with the substrate solder balls 15, and the bottoms of the solder balls correspond to the connection holes. The chip solder ball 14 is used for bonding with a chip, and a side of the chip solder ball 14 facing away from the glass core plate 1 is provided with a plane so as to facilitate bonding with the chip. The substrate solder ball 15 is used for bonding with a printed circuit board, and one side of the substrate solder ball 15 away from the glass core plate 1 is spherical, so that bonding with the printed circuit board is facilitated.
In the glass substrate formed by the method for manufacturing the glass substrate, the plugging material is not a traditional vacuum plugging hole or a traditional vacuum silk screen printing plugging hole of liquid ink, but a resin or a metal plugging hole is adopted, so that the reliability of the glass substrate is improved. In addition, the high-rigidity supporting structure provided by the glass core plate 1 for the integral glass substrate forms high-strength bonding between the metal layer 4 and the glass core plate 1 by utilizing high bonding force of the hole plugging resin for the glass core plate 1 and the inner metal circuit, and solves the problem of poor direct bonding force between the metal layer 4 and the surface of the glass core plate 1. The glass core plate 1 can reduce the warping degree of the whole substrate for the high-rigidity supporting structure provided by the whole glass substrate, further avoid bridging of solder balls during flip-chip, avoid short circuit and the situation that partial solder balls of the chip cannot be welded with bonding pads of the substrate to form open circuits, and further avoid the problems that larger stress is generated between the chip and the substrate due to serious substrate warping, and the stress changes produce solder ball cracking, substrate cracking, chip cracking and the like.
In the description of the above embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A glass substrate, comprising:
a glass core plate having a plurality of through holes, the glass core plate including a first surface and a second surface opposite in a thickness direction thereof;
A first seed layer covering an inner wall of the through hole and a surrounding area of an orifice of the through hole;
A metal layer covering the first seed layer, wherein a part of the metal layer located in the periphery area of the orifice of the through hole forms an annular metal pad;
the hole plugging material is filled in the through hole;
a first resin layer, the first resin layer being provided on both the first surface and the second surface of the glass core plate, and the annular metal pad being uncovered by the first resin layer, the annular metal pad being either level with the first resin layer or higher than the first resin layer;
The second seed layer and the inner circuit layer are stacked, the second seed layer is positioned on one side surface of the first resin layer, which is away from the glass core plate, and the inner circuit layer covers one side surface of the second seed layer, which is away from the glass core plate;
The multi-layer combined structure comprises a second resin layer, a third seed layer and a circuit layer which are sequentially arranged along the direction deviating from the glass core plate, wherein the second resin layer is provided with a through hole, and the third seed layer and the circuit layer are laminated on one side of the second resin layer deviating from the glass core plate;
The solder mask is arranged on one side of the multilayer combined structure, which is away from the glass core plate;
The solder balls are arranged on the solder mask layer, and the bottoms of the solder balls penetrate through the solder mask layer to be in contact with the outermost circuit layer.
2. The glass substrate according to claim 1, wherein the plug hole material is a resin comprising ABF, RCC and/or photosensitive dry film insulating layer material, or the plug hole material is the same as the material of the first resin layer, or,
The plug hole material is metal, and the metal comprises copper, tungsten and/or titanium.
3. The glass substrate according to claim 1, wherein the first seed layer, the second seed layer and/or the third seed layer comprises at least one sub-metal layer, or,
The first seed layer, the second seed layer and/or the third seed layer comprise a plurality of sub-metal layers, and the materials of the sub-metal layers are different.
4. The glass substrate according to claim 3, wherein the sub-metal layer is made of titanium, copper or tungsten.
5. The glass substrate of claim 1, wherein the solder balls comprise chip solder balls and substrate solder balls, the chip solder balls are arranged on a solder mask layer on one side of the glass core board, the substrate solder balls are arranged on a solder mask layer on the other side of the glass core board, the chip solder balls are used for bonding with chips, and the substrate solder balls are used for bonding with a printed circuit board.
6. A method for manufacturing a glass substrate, comprising:
A glass core plate is perforated, a plurality of through holes are formed in the glass core plate, and the glass core plate is provided with a first surface and a second surface which are opposite;
forming a first seed layer on the surface of the glass core plate provided with the through holes;
Forming a first mask on the surface of the structure formed in the previous step, wherein the first mask covers the first surface and the second surface of the structure formed in the previous step except for the inner wall of the through hole and other parts of the surrounding areas of the orifice of the through hole;
Through hole metallization, forming a metal layer on the inner wall of the through hole of the glass core plate and the surrounding area of the hole opening of the through hole, and forming an annular metal bonding pad on the metal layer of the surrounding area of the hole opening of the through hole;
removing the first mask and the first seed layer covered by the first mask;
Plugging holes and forming a first resin layer, filling resin or metal in the through holes of the glass core plate, and pressing resin on the first surface and the second surface of the glass core plate to form the first resin layer on the first surface and the second surface of the glass core plate;
thinning the first resin layer so that the annular metal pad is exposed out of the first resin layer;
Forming a second seed layer on the surfaces of the first resin layers on two sides of the glass core plate;
forming a second mask on the first surface and the second surface of the structure formed in the previous step, wherein the second mask has a hollowed-out structure;
Forming a layer line in the pattern of the second mask;
Removing the second mask and the second seed layer covered by the second mask;
Forming a second resin layer, and laminating resin on the first surface and the second surface of the structure formed in the previous step to form the second resin layer;
forming through holes in the second resin layers on the first surface and the second surface;
forming a third seed layer on the surfaces of the second resin layers on two sides of the glass core plate;
forming a third mask on the first surface and the second surface of the structure formed in the previous step, wherein the third mask has a hollowed-out structure;
Forming a circuit layer in the hollowed-out structure of the third mask;
removing the third mask and the third seed layer covered by the third mask;
repeating the step at least once to form a second resin layer until the step removes the third mask and the third seed layer covered by the third mask;
Manufacturing a solder mask layer on the first surface and the second surface of the structure formed in the previous step, wherein the solder mask layer is provided with a connecting hole corresponding to the circuit layer;
and implanting balls, wherein the first surface and/or the second surface of the structure formed in the previous step are/is welded balls.
7. The method according to claim 6, wherein forming the first seed layer comprises forming the first seed layer on the surface of the glass core plate provided with the through-hole by deposition, and/or,
The forming of the second seed layer comprises forming the second seed layer on the surfaces of the first resin layers on two sides of the glass core plate by utilizing a deposition mode, and/or,
The forming of the third seed layer comprises the step of forming the third seed layer on the surfaces of the second resin layers on two sides of the glass core plate in a deposition mode.
8. The method according to claim 6, wherein the step of plugging is performed by filling resin into the through-holes of the glass core plate and pressing the resin against the first surface and the second surface of the glass core plate so that the resin fills the through-holes of the glass core plate and forms the first resin layer on the first surface and the second surface of the glass core plate.
9. The method of manufacturing a glass substrate according to claim 6, wherein the annular metal pad is level with the first resin layer or the annular metal pad is higher than the first resin layer after the step of thinning the first resin layer.
10. The method according to claim 6, wherein the first mask is formed on the surface of the structure formed in the previous step, in particular, the first mask is formed on the surface of the structure formed in the previous step by using photolithography to form a plating mask, and/or,
The second mask is formed on the first surface and the second surface of the structure formed in the previous step, specifically, the second mask is formed on the first surface and the second surface of the structure formed in the previous step by adopting a photoetching manufacturing method for manufacturing an electroplating mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411187969.4A CN119208288A (en) | 2024-08-27 | 2024-08-27 | Glass substrate and method for manufacturing the same |
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| CN202411187969.4A CN119208288A (en) | 2024-08-27 | 2024-08-27 | Glass substrate and method for manufacturing the same |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010042637A1 (en) * | 1998-09-03 | 2001-11-22 | Naohiro Hirose | Multilayered printed circuit board and manufacturing method therefor |
| JP2003069228A (en) * | 2001-08-23 | 2003-03-07 | Ibiden Co Ltd | Mask for filling resin and method for manufacturing multilayer printed wiring board |
| JP2004031812A (en) * | 2002-06-27 | 2004-01-29 | Ngk Spark Plug Co Ltd | Method of manufacturing wiring board |
| JP2017063152A (en) * | 2015-09-25 | 2017-03-30 | 京セラ株式会社 | Wiring board and manufacturing method thereof |
| US20190269013A1 (en) * | 2016-12-02 | 2019-08-29 | Toppan Printing Co., Ltd. | Electronic component and method of producing electronic component |
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- 2024-08-27 CN CN202411187969.4A patent/CN119208288A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010042637A1 (en) * | 1998-09-03 | 2001-11-22 | Naohiro Hirose | Multilayered printed circuit board and manufacturing method therefor |
| JP2003069228A (en) * | 2001-08-23 | 2003-03-07 | Ibiden Co Ltd | Mask for filling resin and method for manufacturing multilayer printed wiring board |
| JP2004031812A (en) * | 2002-06-27 | 2004-01-29 | Ngk Spark Plug Co Ltd | Method of manufacturing wiring board |
| JP2017063152A (en) * | 2015-09-25 | 2017-03-30 | 京セラ株式会社 | Wiring board and manufacturing method thereof |
| US20190269013A1 (en) * | 2016-12-02 | 2019-08-29 | Toppan Printing Co., Ltd. | Electronic component and method of producing electronic component |
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