CN119208372B

CN119208372B - Semiconductor device, manufacturing method thereof, chip and electronic equipment

Info

Publication number: CN119208372B
Application number: CN202411601353.7A
Authority: CN
Inventors: 王宇豪; 冯超; 刘轩
Original assignee: Shenzhen Pinghu Laboratory
Current assignee: Shenzhen Pinghu Laboratory
Priority date: 2024-11-11
Filing date: 2024-11-11
Publication date: 2025-03-07
Anticipated expiration: 2044-11-11
Also published as: CN119208372A

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, a chip, and an electronic device, which relate to the field of semiconductor technology and are intended to improve the threshold voltage of the semiconductor device while improving the reliability of the semiconductor device. The semiconductor device comprises a substrate, a barrier layer, a first cap layer, a second cap layer, a source electrode, and a drain electrode. The barrier layer is arranged on one side of the substrate, the first cap layer is arranged on the side of the barrier layer away from the substrate, the second cap layer is arranged on the side of the first cap layer away from the substrate, the source electrode and the drain electrode are located on opposite sides of the first cap layer along a first direction, and are both arranged on the side of the barrier layer away from the substrate, the first direction is parallel to the substrate, wherein the size of the second cap layer along the first direction is smaller than the size of the first cap layer along the first direction, the first cap layer and the second cap layer both comprise P-type doped semiconductor materials, and the doping concentration of the first cap layer is smaller than the doping concentration of the second cap layer. The above-mentioned semiconductor device is applied to a chip.

Description

Semiconductor device, manufacturing method thereof, chip and electronic equipment

Technical Field

The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor device, a manufacturing method thereof, a chip and electronic equipment.

Background

Compared with the first-generation semiconductor material represented by silicon, the gallium nitride semiconductor material has higher forbidden bandwidth, critical breakdown field intensity and electron saturation drift velocity, has remarkable advantages in the aspects of high frequency, high voltage resistance, high power, low on-resistance and the like, can be used as a core device in various power conversion systems, and has wide prospects in the fields of consumer electronics, 5G radio frequency, servers, telecommunication applications and the like.

Disclosure of Invention

The embodiment of the disclosure provides a semiconductor device, a preparation method thereof, a chip and electronic equipment, and aims to improve the reliability of the semiconductor device while improving the threshold voltage of the semiconductor device.

In order to achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

In one aspect, a semiconductor device is provided. The semiconductor device includes a substrate, a barrier layer, a first cap layer, a second cap layer, a source electrode, and a drain electrode. The barrier layer is disposed on one side of the substrate. The first cap layer is arranged on one side of the barrier layer away from the substrate. The second cap layer is arranged on one side of the first cap layer away from the substrate. The source electrode and the drain electrode are positioned on two opposite sides of the first cap layer along a first direction, and are both arranged on one side of the barrier layer away from the substrate, and the first direction is parallel to the substrate. The second cap layer has a dimension along the first direction that is smaller than a dimension of the first cap layer along the first direction. The first cap layer and the second cap layer both comprise P-type doped semiconductor materials, and the doping concentration of the first cap layer is smaller than that of the second cap layer.

According to the semiconductor device provided by the embodiment of the disclosure, the semiconductor device comprises the first cap layer and the second cap layer, the second cap layer is arranged on one side of the first cap layer in the semiconductor device away from the substrate, the first cap layer and the second cap layer both comprise P-type doped semiconductor materials, the doping concentration of the first cap layer is smaller than that of the second cap layer, on one hand, as the second cap layer is arranged on one side of the first cap layer in the semiconductor device away from the substrate, namely, the first cap layer is positioned between the second cap layer and the barrier layer, under the condition that the P-type impurities in the second cap layer are diffused in the process of forming the second cap layer in the semiconductor device, the P-type impurities in the second cap layer are firstly diffused into the first cap layer, the P-type impurities in the second cap layer can be prevented or relieved from diffusing into the barrier layer, the additional charges and electric fields introduced into the barrier layer can be reduced, the probability of interference caused by polarization effects of the barrier layer can be improved, the probability of the barrier layer can be further improved, the probability of the barrier layer being connected with the barrier layer can be further improved, the probability of the interface state degradation of the semiconductor device can be further improved, the interface state degradation of the barrier layer can be further improved, and the interface state degradation of the semiconductor device can be further improved, and the interface performance of the interface can be further improved.

On the other hand, the doping concentration of the first cap layer (i.e., the concentration of the P-type impurity in the first cap layer) is smaller than the doping concentration of the second cap layer (i.e., the concentration of the P-type impurity in the second cap layer), i.e., the doping concentration of the first cap layer is smaller, in the process of forming the first cap layer in the semiconductor device, the P-type impurity in the first cap layer may not or slightly diffuse into the barrier layer, so that the probability that the P-type impurity introduces additional charges and an electric field into the barrier layer and interferes with the polarization effect of the barrier layer can be further reduced, the polarization effect of the barrier layer can be further improved, the probability that the characteristic of a connection interface between the first cap layer and the barrier layer changes (e.g., the connection interface between the first cap layer and the barrier layer increases in state density) and the control capability of the gate layer in the semiconductor device is further reduced, and the probability that the dynamic on-resistance degradation problem of the semiconductor device occurs can be further reduced, and the reliability of the semiconductor device can be further improved.

In yet another aspect, since the doping concentration of the first cap layer (i.e., the concentration of the P-type impurity in the first cap layer) is smaller than the doping concentration of the second cap layer (i.e., the concentration of the P-type impurity in the second cap layer), i.e., the doping concentration of the second cap layer is greater, so that there is an energy band difference (e.g., a conduction band difference) between the second cap layer and the barrier layer, the energy band difference (e.g., a conduction band difference) between the second cap layer and the barrier layer can be used to regulate and control the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) near the connection interface of the barrier layer and the channel layer, which is beneficial to depleting the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) under the second cap layer, thereby enabling the semiconductor device to implement the enhancement mode. And because the second cap layer in the semiconductor device plays a role in exhausting Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) below the second cap layer, the semiconductor device needs to overcome a higher potential barrier when being started, which is beneficial to improving the threshold voltage of the semiconductor device.

In some embodiments, the semiconductor device includes a plurality of the second cap layers. The plurality of second cap layers are spaced apart along the first direction.

In some embodiments, the semiconductor device further comprises a gate layer. The grid electrode layer is arranged on one side, far away from the substrate, of the first cover cap layer. The gate layer covers both sides of the second cap layer opposite in the first direction, and a side surface of the second cap layer remote from the substrate.

In the case of the semiconductor device provided by the above embodiment of the present disclosure, in which the semiconductor device includes the first cap layer and the second cap layer, by disposing the gate layer in the semiconductor device on a side of the first cap layer away from the substrate, where the gate layer covers Two opposite sides of the second cap layer along the first direction (i.e., the arrangement direction of the source and the drain in the semiconductor device), and where the second cap layer is not disposed on a side surface of the second cap layer away from the substrate, i.e., between a partial region in the gate layer and the first cap layer, a portion of Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) in the semiconductor device may be collected by a partial region between the gate layer and the first cap layer through the first cap layer, without passing through the second cap layer, on the one hand, because the doping concentration of the first cap layer (i.e.e., the concentration of P-type impurities in the first cap layer) is smaller than that of the second cap layer (i.e., the concentration of the P-type impurities in the first cap layer) and the second cap layer, i.e., the concentration of electrons are more favorably trapped in the Two-dimensional electron gas (Two-35 to be trapped in the Two-dimensional gas-trap, the Two-dimensional electron gas (Two-dimensional gas-35) is more favorably trapped in the Two-dimensional gas-trap layer than the first cap layer and the Two-dimensional electron gas (35 to be trapped in the Two-dimensional gas-trap layer) and the Two-trap layer and the electron gas barrier layer) on the Two-trap layer, therefore, the probability of the occurrence of the forward drift phenomenon of the threshold voltage caused by the capture of electrons by electron traps in the transmission process can be avoided or reduced, and the stability of the threshold voltage of the semiconductor device is improved.

On the other hand, the doping concentration of the first cap layer (i.e. the concentration of the P-type impurity in the first cap layer) is smaller, so that an approximately uniformly distributed electric field exists in the first cap layer, electrons are facilitated to accelerate in the first cap layer and smoothly jump to the interface between the first cap layer and the gate layer, scattering and energy loss of the electrons in the transmission process can be reduced, and further performance stability of the semiconductor device is facilitated to be improved.

In yet another aspect, since the doping concentration of the first cap layer (i.e., the concentration of the P-type impurity in the first cap layer) is smaller than the doping concentration of the second cap layer (i.e., the concentration of the P-type impurity in the second cap layer), i.e., the doping concentration of the second cap layer is greater, so that there is an energy band difference (e.g., a conduction band difference) between the second cap layer and the barrier layer, the energy band difference (e.g., a conduction band difference) between the second cap layer and the barrier layer can be used to regulate and control the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) near the connection interface of the barrier layer and the channel layer, which is beneficial to depleting the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) under the second cap layer, thereby enabling the semiconductor device to implement the enhancement mode.

And because the second cap layer in the semiconductor device plays a role in exhausting Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) below the second cap layer, the semiconductor device needs to overcome a higher potential barrier when being started, which is beneficial to improving the threshold voltage of the semiconductor device.

In summary, in the case that the semiconductor device includes the first cap layer and the second cap layer, by disposing the gate layer in the semiconductor device on the side of the first cap layer away from the substrate, and covering the two sides of the second cap layer opposite in the first direction (i.e., the arrangement direction of the source and the drain in the semiconductor device), and the side surface of the second cap layer away from the substrate, the stability of the threshold voltage of the semiconductor device and the performance stability of the semiconductor device can be improved while the threshold voltage of the semiconductor device is improved.

In some embodiments, the gate layer is in contact with a portion of a surface of the first cap layer.

In some embodiments, a dimension of the gate layer along the first direction is less than or equal to a dimension of the first cap layer along the first direction.

In some embodiments, the second cap layer has a dimension in a second direction that is the same as a dimension of the first cap layer in the second direction, the second direction being perpendicular to the first direction, and the second direction being parallel to the substrate.

In some embodiments, the first capping layer has a doping concentration less than or equal to 5 x 10 ¹⁷ cm^-3.

In some embodiments, the second cap layer has a doping concentration greater than or equal to 5 x 10 ¹⁸ cm^-3 and less than or equal to 10 x 10 ¹⁹ cm^-3.

In some embodiments, the semiconductor device further comprises a protective layer. The protective layer is arranged between the first cover cap layer and the second cover cap layer. The protective layer and the first cap layer overlap in a thickness direction of the substrate.

In some embodiments, the material of the protective layer and the material of the second cap layer are different.

In some embodiments, the material of the protective layer includes at least one of aluminum gallium nitride and aluminum nitride.

In some embodiments, the material of the protective layer comprises a P-doped semiconductor material, and the protective layer has a doping concentration that is less than the doping concentration of the second cap layer.

In another aspect, a method of fabricating a semiconductor device is provided. The preparation method of the semiconductor device comprises the following steps:

a barrier layer is formed on one side of the substrate.

A first cap layer is formed on a side of the barrier layer remote from the substrate.

A second cap layer is formed on a side of the first cap layer remote from the substrate.

Forming a source electrode and a drain electrode. The source electrode and the drain electrode are positioned on two opposite sides of the first cap layer along a first direction, and are both arranged on one side of the barrier layer away from the substrate, wherein the first direction is parallel to the substrate.

The second cap layer has a dimension along the first direction that is smaller than a dimension of the first cap layer along the first direction. The first cap layer and the second cap layer both comprise P-type doped semiconductor materials, and the doping concentration of the first cap layer is smaller than that of the second cap layer.

In some embodiments, the forming the first cap layer and the forming the second cap layer comprise the steps of:

and sequentially forming a first initial cap layer and a second initial cap layer on one side of the barrier layer away from the substrate.

And removing the first initial cap layer and the second initial cap layer of the source region to be formed and the drain region to be formed, and forming a first cap layer and a third cap layer. The first cap layer and the third cap layer overlap in a thickness direction of the substrate.

And removing part of the third cap layer to form a second cap layer.

In yet another aspect, a chip is provided. The chip comprising a semiconductor device as described in any of the embodiments above.

In yet another aspect, an electronic device is provided. The electronic device comprises a circuit board and a chip as described above. The chip is electrically connected with the circuit board.

It can be appreciated that, the method for manufacturing a semiconductor device, the chip and the electronic device provided in the foregoing embodiments of the present disclosure may refer to the beneficial effects of the semiconductor device, and are not described herein.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

FIG. 1 is a schematic diagram of an electronic device according to some embodiments;

FIG. 2 is a second schematic structural diagram of an electronic device according to some embodiments;

FIG. 3 is a schematic cross-sectional view of a chip according to some embodiments;

FIG. 4 is a second schematic cross-sectional view of a chip according to some embodiments;

Fig. 5 is a schematic cross-sectional view of a semiconductor device according to some embodiments;

fig. 6 is a schematic cross-sectional view of a semiconductor device according to some embodiments;

fig. 7 is a schematic cross-sectional view of a semiconductor device according to some embodiments;

fig. 8 is a schematic cross-sectional view of a semiconductor device according to some embodiments;

fig. 9 is a schematic top view of a first cap layer and a second cap layer within a semiconductor device according to some embodiments;

fig. 10 is a second schematic top view of a first cap layer and a second cap layer within a semiconductor device according to some embodiments;

fig. 11 is a schematic cross-sectional view of a semiconductor device according to some embodiments;

fig. 12 is a schematic cross-sectional view of a semiconductor device according to some embodiments;

fig. 13 is a schematic cross-sectional view of a semiconductor device according to some embodiments;

fig. 14 is a schematic cross-sectional view eighth of a semiconductor device according to some embodiments;

Fig. 15 is a flow chart of a method of fabricating a semiconductor device according to some embodiments;

Fig. 16 is a schematic structural diagram of a semiconductor device corresponding to step S1 in the flowchart of the method for manufacturing a semiconductor device in fig. 15;

fig. 17 is a schematic structural diagram of a semiconductor device corresponding to step S2 and step S3 in the flowchart of the method for manufacturing a semiconductor device in fig. 15;

Fig. 18 is a schematic structural diagram of a semiconductor device corresponding to step S4 in the flowchart of the method for manufacturing a semiconductor device in fig. 15;

fig. 19 is a schematic structural diagram of a semiconductor device corresponding to step S5 and step S6 in the flowchart of the method for manufacturing a semiconductor device in fig. 15.

Reference numerals:

1000-electronic device, 100-chip, 200-circuit board, 10-semiconductor device, 1-substrate, 2-buffer layer, 31-first interposer, 32-second interposer, 4-channel layer, 5-barrier layer, 61-first cap layer, 62-second cap layer, 63-third cap layer, 64-fourth cap layer, 61 a-first initial cap layer, 62 a-second initial cap layer, 7-passivation layer, 8-protective layer, G-gate layer, S-source, D-drain, sa-to-be-formed source region, da-to-be-formed drain region.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

In the description of the present disclosure, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C" and each includes a combination of A, B and C of a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes three combinations of A only, B only, and a combination of A and B.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "about," "approximately" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

In the present disclosure, "above," "over," and "over" should be interpreted in the broadest sense such that "over" means not only "directly over" but also includes the meaning of "over" with an intermediate feature or layer therebetween, and "over" or "over" means not only "over" or "over" but also includes the meaning of "over" or "over" without an intermediate feature or layer therebetween (i.e., directly over).

The words "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

For convenience of the following description, an XYZ coordinate system is established. The third direction Z is the thickness direction of the substrate, the XY plane is perpendicular to the third direction Z, and the first direction X and the second direction Y are intersected. For example, the first direction X and the second direction Y are perpendicular to each other.

As shown in fig. 1, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 may include communication devices (e.g., satellite communication devices, wireless television receivers, etc.), radar devices (e.g., millimeter wave radar, weather radar, etc.), radio navigation devices (e.g., GPS receivers, etc.), and the like. The embodiment of the present application is not particularly limited to the specific form of the electronic device 1000 described above. An electronic device 1000 is illustrated in fig. 1 as an example of a communication device.

In some embodiments, as shown in fig. 2, fig. 2 is a schematic structural diagram of an electronic device 1000 according to some embodiments. The electronic device 1000 includes a chip 100 and a circuit board 200. The chip 100 and the circuit board 200 are electrically connected.

Illustratively, the circuit board 200 may include a printed circuit board (Printed Circuit Board, PCB) or the like.

Illustratively, the circuit board 200 may include a plurality of conductive layers. The plurality of conductive layers within the circuit board 200 may be separated from one another by dielectric layers.

The chip 100 is described in detail below.

In some embodiments, as shown in fig. 3 and 4, fig. 3 and 4 are both cross-sectional schematic views of a chip 100 according to some embodiments. The chip 100 includes a semiconductor device 10.

Illustratively, the chip 100 may include a processor chip. For example, the Processor chip may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL processors, DSPs), application Specific Integrated Circuits (ASICs), field programmable gate arrays (Field Programmable GATE ARRAY, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The semiconductor device 10 is described in detail below.

In some embodiments, with continued reference to fig. 3 and 4, semiconductor device 10 may include a substrate 1.

Illustratively, the material of the substrate 1 within the semiconductor device 10 may include one of silicon (Si), silicon carbide (SiC), sapphire, and the like.

In some embodiments, referring still to fig. 3 and 4, the semiconductor device 10 may further include a buffer layer (buffer layer) 2. A buffer layer 2 may be provided at one side of the substrate 1.

By providing the buffer layer 2 in the semiconductor device 10, and providing the buffer layer 2 on one side of the substrate 1, not only other film structures provided on the side of the buffer layer 2 away from the substrate 1 in the semiconductor device 10 can be bonded, but also the substrate 1 can be protected from intrusion of some metal ions into the substrate 1.

Illustratively, the material of the buffer layer 2 within the semiconductor device 10 may include at least one of a plurality of different compositions of nitride Al _xIn_yGa_(1-x-y) N, (0. Ltoreq.x, y. Ltoreq.1).

For example, the material of buffer layer 2 in semiconductor device 10 may include one of a plurality of different compositions of nitride Al _xIn_yGa_(1-x-y) N, (0. Ltoreq.x, y. Ltoreq.1).

As another example, the material of the buffer layer 2 in the semiconductor device 10 may include a plurality of (greater than or equal to two) nitrides Al _xIn_yGa_(1-x-y) N of a plurality of different compositions (0+.x, y+.1).

Illustratively, the buffer layer 2 within the semiconductor device 10 may be formed by a Metal-organic chemical vapor deposition (MOCVD) process (Metal-organic Chemical Vapor Deposition), a molecular beam epitaxy (Molecular Beam Epitaxy, MBE) process, a physical vapor deposition (Physical Vapor Deposition, PVD) process, or the like.

For example, the buffer layer 2 in the semiconductor device 10 may have a single-layer structure. I.e. in the third direction (i.e. the thickness direction of the substrate 1) Z, the buffer layer 2 comprises a layer structure.

Or the buffer layer 2 within the semiconductor device 10 may be a multi-layer (greater than or equal to two layers) structure. I.e., in the third direction (i.e., the thickness direction of the substrate 1) Z, the buffer layer 2 includes a multi-layer (greater than or equal to two-layer) film structure.

For example, referring still to fig. 4, semiconductor device 10 may further include a first interposer 31. The first insertion layer 31 in the semiconductor device 10 may be disposed between the substrate 1 and a buffer layer 2 in the semiconductor device 10.

The material of the first insertion layer 31 in the semiconductor device 10 may include aluminum nitride (AIN) or the like.

By providing the first insertion layer 31 between the substrate 1 and the buffer layer (buffer layer) 2 in the semiconductor device 10, on the one hand, in the case where there is a lattice constant mismatch or a difference in thermal expansion coefficient between the substrate 1 and the buffer layer (buffer layer) 2 in the semiconductor device 10, the first insertion layer 31 can alleviate stress due to the lattice constant mismatch or the difference in thermal expansion coefficient between the substrate 1 and the buffer layer (buffer layer) 2 in the semiconductor device 10, and avoid an influence of stress due to the lattice constant mismatch or the difference in thermal expansion coefficient between the substrate 1 and the buffer layer (buffer layer) 2 in the semiconductor device 10 on the performance of the semiconductor device 10, which is advantageous for improving the performance of the semiconductor device 10.

On the other hand, the first interposer 31 in the semiconductor device 10 can improve the interface characteristics between the substrate 1 and the buffer layer 2 in the semiconductor device 10, reduce the interface defects between the substrate 1 and the buffer layer 2 in the semiconductor device 10, and is beneficial to improving the stability and reliability of the semiconductor device 10.

In still another aspect, in the case where the material of the substrate 1 in the semiconductor device 10 includes silicon (Si), silicon carbide (SiC), or the like, and the material of the buffer layer 2 in the semiconductor device 10 includes at least one of a plurality of different compositions of nitrides Al _xIn_yGa_(1-x-y) N, (0+.x, y+.1), the first interposed layer 31 provided between the substrate 1 and the buffer layer 2 in the semiconductor device 10 can prevent the silicon (Si) element in the substrate 1 and the gallium (Ga) element in the buffer layer 2 from undergoing a reflow etching (Back-etching or Regrowth Etching) reaction at a high temperature, thereby avoiding damages to the substrate 1 and the buffer layer 2 in the semiconductor device 10, facilitating improvement of yield of the semiconductor device 10, and facilitating further improvement of stability and reliability of the semiconductor device 10.

In some embodiments, referring still to fig. 3 and 4, semiconductor device 10 may further include channel layer 4. The channel layer 4 within the semiconductor device 10 may be disposed at one side of the substrate 1.

For example, referring to fig. 3 and 4, in the case where the semiconductor device 10 includes a buffer layer (buffer layer) 2, the channel layer 4 within the semiconductor device 10 may be disposed on a side of the buffer layer (buffer layer) 2 away from the substrate 1.

Illustratively, the material of the channel layer 4 within the semiconductor device 10 may include gallium nitride (GaN).

Illustratively, the channel layer 4 within the semiconductor device 10 may be formed by a Metal-organic chemical vapor deposition process (Metal-organic Chemical Vapor Deposition, MOCVD), a molecular beam epitaxy process (Molecular Beam Epitaxy, MBE), or a physical vapor deposition process (Physical Vapor Deposition, PVD), among others.

In some embodiments, referring still to fig. 3 and 4, semiconductor device 10 may further include barrier layer 5. The barrier layer 5 is provided on one side of the substrate 1 in the semiconductor device 10.

Illustratively, the material of the barrier layer 5 within the semiconductor device 10 may include at least one of a variety of different compositions of nitride Al _xIn_yGa_(1-x-y) N, (0 < x.ltoreq.1, 0.ltoreq.y.ltoreq.1).

For example, the material of the barrier layer 5 within the semiconductor device 10 may include one of a plurality of different compositions of nitride Al _xIn_yGa_(1-x-y) N, (0 < x.ltoreq.1, 0.ltoreq.y.ltoreq.1).

For another example, the material of the barrier layer 5 in the semiconductor device 10 may include a plurality of (greater than or equal to two) nitrides Al _xIn_yGa_(1-x-y) N of a plurality of different compositions (0 < x.ltoreq.1, 0.ltoreq.y.ltoreq.1).

Illustratively, the barrier layer 5 within the semiconductor device 10 may be formed by a Metal-organic chemical vapor deposition process (Metal-organic Chemical Vapor Deposition, MOCVD), a molecular beam epitaxy process (Molecular Beam Epitaxy, MBE), or a physical vapor deposition process (Physical Vapor Deposition, PVD), among others.

For example, referring to fig. 3 and 4, the barrier layer 5 in the semiconductor device 10 may be disposed on a side of the channel layer 4 away from the substrate 1. I.e. the channel layer 4 is arranged between the barrier layer 5 and the substrate 1.

In the case where the barrier layer 5 in the semiconductor device 10 is provided on the side of the channel layer 4 remote from the substrate 1, and the Band gap (Band gap) of the material of the barrier layer 5 (for example, aluminum gallium nitride (AlGaN)) is larger than the Band gap (Band gap) of the material of the channel layer 4 (for example, gallium nitride (GaN)), a heterojunction structure is formed at the connection interface of the barrier layer 5 and the channel layer 4 due to the difference in electron affinity (Electron Affinity) and Work Function (Work Function) of the material of the barrier layer 5 (for example, aluminum gallium nitride (AlGaN)) and the material of the channel layer 4 (for example, gallium nitride (GaN)), which causes bending of the Band structure of the channel layer 4, thereby forming a potential well in the channel layer 4. In order to balance the charge distribution at the connection interface of the barrier layer 5 and the channel layer 4, electrons in the barrier layer 5 can transfer to a potential well in the channel layer 4, and the potential well in the channel layer 4 can limit electrons, so that electrons can only freely move in a direction parallel to the connection interface of the barrier layer 5 and the channel layer 4, and Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) is induced to be formed near the connection interface of the barrier layer 5 and the channel layer 4, which is beneficial to improving the electron mobility and improving the performance of the semiconductor device 10.

It should be noted that the above Band gap refers to that electron energy in the solid cannot be continuously valued, but forms discontinuous energy bands, wherein the energy difference between the conduction Band and the valence Band is the Band gap. Specifically, to be a free electron or hole, the bound electron must acquire enough energy to transition from the valence band to the conduction band, and the minimum of this energy is the forbidden bandwidth.

For example, referring to fig. 3 and 4, in the case where a Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) is formed within the semiconductor device 10, the semiconductor device 10 may be used to form a high electron mobility transistor (High Electron Mobility Transistor, HEMT).

For example, referring still to fig. 4, in the case where the barrier layer 5 in the semiconductor device 10 is disposed on the side of the channel layer 4 remote from the substrate 1, the semiconductor device 10 may further include the second insertion layer 32. The second insertion layer 32 in the semiconductor device 10 may be disposed between the channel layer 4 and the barrier layer 5 in the semiconductor device 10.

The material of the second insertion layer 32 within the semiconductor device 10 may include aluminum nitride (AIN) or the like.

By providing the second insertion layer 32 between the channel layer 4 and the barrier layer 5 in the semiconductor device 10, on the one hand, the second insertion layer 32 in the semiconductor device 10 can enhance the polarization effect between the channel layer 4 and the barrier layer 5, which is advantageous for increasing the concentration of Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) near the connection interface of the barrier layer 5 and the channel layer 4.

On the other hand, the second insertion layer 32 in the semiconductor device 10 may enhance the confinement of the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) near the connection interface of the barrier layer 5 and the channel layer 4, so that the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) near the connection interface of the barrier layer 5 and the channel layer 4 is further limited in a certain dimension (for example, a Two-dimensional plane), which is beneficial to enhancing the electron mobility in the semiconductor device 10, and thus is beneficial to enhancing the performance of the semiconductor device 10.

In some embodiments, referring still to fig. 3 and 4, semiconductor device 10 may further include a gate layer G. The gate layer G may be disposed on a side of the barrier layer 5 within the semiconductor device 10 remote from the substrate 1.

The gate layer G in the semiconductor device 10 is a key electrode controlling the conductivity of the semiconductor device 10, and the gate layer G does not directly participate in the conduction of current but controls the carrier concentration in the channel layer 4 in the semiconductor device 10 by an electric field effect, thereby controlling the current in the semiconductor device 10.

Illustratively, the material of the gate layer G within the semiconductor device 10 may include at least one of a conductive material such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

For example, the material of the gate layer G in the semiconductor device 10 may include one of conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

As another example, the material of the gate layer G in the semiconductor device 10 may include a plurality of (two or more) conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

In some embodiments, referring still to fig. 3 and 4, semiconductor device 10 may further include a source S and a drain D. The source S and the drain D are located on opposite sides of the gate layer G within the semiconductor device 10 along the first direction X, and are each disposed on a side of the barrier layer 5 within the semiconductor device 10 remote from the substrate 1. The first direction X is parallel to the substrate 1 within the semiconductor device 10.

For example, in the case where Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) is formed in the semiconductor device 10, the source S and the drain D in the semiconductor device 10 may form ohmic contact with the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG), so that contact resistance between the source S and the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) in the semiconductor device 10 and contact resistance between the drain D and the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) in the semiconductor device 10 may be reduced, and a low-resistance current path may be formed between the source S, the drain D and the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) in the semiconductor device 10, so that current may smoothly flow, which may be advantageous for improving performance of the semiconductor device 10.

In some embodiments, referring still to fig. 3 and 4, semiconductor device 10 may further include passivation layer 7. The passivation layer 7 may cover the gate layer G, the source electrode S, and the drain electrode D within the semiconductor device 10.

By disposing the passivation layer 7 in the semiconductor device 10, and the passivation layer 7 covers the gate layer G, the source electrode S, and the drain electrode D in the semiconductor device 10, on one hand, the passivation layer 7 can block harmful substances (e.g., oxygen, water, etc.) in the external environment, prevent the harmful substances (e.g., oxygen, water, etc.) in the external environment from directly contacting the source electrode S, the drain electrode D, and the gate layer G in the semiconductor device 10, which results in damage to the source electrode S, the drain electrode D, and the gate layer G in the semiconductor device 10, thereby being beneficial to improving the stability of the semiconductor device 10 and prolonging the service life of the semiconductor device 10.

On the other hand, the passivation layer 7 has a certain mechanical strength, and can protect the source electrode S, the drain electrode D and the gate electrode layer G in the semiconductor device 10 to a certain extent, so as to avoid the source electrode S, the drain electrode D and the gate electrode layer G in the semiconductor device 10 from being mechanically damaged, thereby being beneficial to further improving the stability of the semiconductor device 10 and further prolonging the service life of the semiconductor device 10.

Illustratively, the material of the passivation layer 7 within the semiconductor device 10 may include at least one of silicon nitride (Si ₃N₄), silicon oxide (SiO ₂), aluminum nitride (AlN), aluminum oxide (Al ₂O₃), and the like.

For example, the material of the passivation layer 7 in the semiconductor device 10 may include one of silicon nitride (Si ₃N₄), silicon oxide (SiO ₂), aluminum nitride (AlN), aluminum oxide (Al ₂O₃), and the like.

As another example, the material of the passivation layer 7 in the semiconductor device 10 may include a plurality of (two or more) kinds of silicon nitride (Si ₃N₄), silicon oxide (SiO ₂), aluminum nitride (AlN), aluminum oxide (Al ₂O₃), and the like.

The passivation layer 7 within the semiconductor device 10 may be of a single-layer structure, for example. I.e. in the third direction (i.e. in the thickness direction of the substrate 1) Z, the passivation layer 7 comprises a layer structure.

Or the passivation layer 7 within the semiconductor device 10 may be a multi-layer (greater than or equal to two layers) structure. I.e. in the third direction (i.e. in the thickness direction of the substrate 1) Z, the passivation layer 7 comprises a multilayer (greater than or equal to two) film layer structure.

For example, the passivation layer 7 in the semiconductor device 10 may have a two-layer structure. Along the third direction (i.e., the thickness direction of the substrate 1) Z, the passivation layer 7 may include a silicon nitride (Si ₃N₄) layer and an aluminum nitride (AlN) layer.

Illustratively, the passivation layer 7 within the semiconductor device 10 may be formed by at least one of a chemical vapor deposition process (Chemical Vapor Deposition, CVD) and a physical vapor deposition process (Physical Vapor Deposition, PVD) or the like.

For example, the passivation layer 7 within the semiconductor device 10 may be formed by one of a chemical vapor deposition process (Chemical Vapor Deposition, CVD) and a physical vapor deposition process (Physical Vapor Deposition, PVD) or the like.

For another example, the passivation layer 7 in the semiconductor device 10 may be formed by a plurality of (two or more) processes among a chemical vapor deposition process (Chemical Vapor Deposition, CVD) and a physical vapor deposition process (Physical Vapor Deposition, PVD) and the like.

In some embodiments, referring still to fig. 3 and 4, semiconductor device 10 may further include a fourth cap layer 64. The fourth capping layer 64 may be disposed on a side of the barrier layer 5 within the semiconductor device 10 remote from the substrate 1. The fourth cap layer 64 comprises a P-doped semiconductor material, and the fourth cap layer 64 has a doping concentration (i.e., the concentration of P-type impurities within the fourth cap layer 64) greater than or equal to 5 x 10 ¹⁸ cm^-3 and less than or equal to 1 x 10 ²⁰ cm^-3.

By including the semiconductor device 10 with the fourth cap layer 64, the fourth cap layer 64 is disposed on a side of the barrier layer 5 in the semiconductor device 10 away from the substrate 1, and the fourth cap layer 64 includes a P-type doped semiconductor material, the doping concentration of the fourth cap layer 64 (i.e., the concentration of the P-type impurity in the fourth cap layer 64) is greater than or equal to 5×10 ¹⁸ cm^-3 and less than or equal to 1×10 ²⁰cm^-3, on the one hand, an energy band difference (e.g., a conduction band difference) between the fourth cap layer 64 and the barrier layer 5 can be made, and the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) near the connection interface of the barrier layer 5 and the channel layer 4 can be regulated by using the energy band difference (e.g., a conduction band difference) between the fourth cap layer 64 and the barrier layer 5, which is advantageous for exhausting the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) under the fourth cap layer 64, thereby enabling the semiconductor device 10 to realize an enhanced work mode.

On the other hand, due to the depletion effect of the fourth cap layer 64 in the semiconductor device 10 on the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) located under the fourth cap layer 64, the semiconductor device 10 needs to overcome a higher potential barrier when turned on, which is beneficial for increasing the threshold voltage of the semiconductor device 10.

Illustratively, the material of the fourth capping layer 64 within the semiconductor device 10 may include P-type gallium nitride (P-GaN). P-type gallium nitride (P-GaN) can be formed by doping a gallium nitride (GaN) material with elements such as iron (Fe) and magnesium (Mg).

With continued reference to fig. 3 and 4, during formation of the fourth cap layer 64 within the semiconductor device 10, a P-type impurity, such as magnesium (Mg), is typically incorporated as an impurity into the semiconductor material, such as gallium nitride (GaN), to provide hole carriers, thereby adjusting the conductivity of the fourth cap layer 64.

Ideally, the P-type impurity (e.g., magnesium (Mg)) in the fourth cap layer 64 should be uniformly distributed in the semiconductor material (e.g., gallium nitride (GaN)) in the fourth cap layer 64, however, during the actual manufacturing process, the P-type impurity (e.g., magnesium (Mg)) in the fourth cap layer 64 may be diffused due to various factors (e.g., temperature, electric field, etc.) and may be diffused into the barrier layer 5 in the semiconductor device 10.

In the case where the P-type impurity (for example, magnesium (Mg)) in the fourth cap layer 64 diffuses into the barrier layer 5 in the semiconductor device 10, on the one hand, a change in the characteristics of the connection interface between the fourth cap layer 64 and the barrier layer 5 (for example, an increase in the trap state density of the connection interface between the fourth cap layer 64 and the barrier layer 5, etc.) is liable to occur, and the controllability of the gate layer G in the semiconductor device 10 is liable to be affected, thereby causing problems such as degradation of the dynamic on-resistance of the semiconductor device 10, and lowering the reliability of the semiconductor device 10.

On the other hand, when the P-type impurity (for example, magnesium (Mg)) in the fourth capping layer 64 diffuses into the barrier layer 5, additional charges and an electric field are introduced into the barrier layer 5, which tends to interfere with the polarization effect of the barrier layer 5.

Based on this, in some embodiments, as shown in fig. 5, 6, 7, and 8, fig. 5, 6, 7, and 8 are cross-sectional schematic views of semiconductor device 10 according to some embodiments. The semiconductor device 10 may further include a first capping layer 61 and a second capping layer 62. The first capping layer 61 is provided on the side of the barrier layer 5 within the semiconductor device 10 remote from the substrate 1. The second cap layer 62 is provided on a side of the first cap layer 61 away from the substrate 1 within the semiconductor device 10. That is, the first capping layer 61 within the semiconductor device 10 is closer to the barrier layer 5 than the second capping layer 62.

Wherein the first cap layer 61 and the second cap layer 62 in the semiconductor device 10 each comprise a P-type doped semiconductor material, and the doping concentration of the first cap layer 61 is smaller than the doping concentration of the second cap layer 62.

By enabling the semiconductor device 10 to comprise the first cap layer 61 and the second cap layer 62, the second cap layer 62 is arranged on one side of the first cap layer 61 in the semiconductor device 10 far away from the substrate 1, the first cap layer 61 and the second cap layer 62 comprise P-type doped semiconductor materials, the doping concentration of the first cap layer 61 is smaller than that of the second cap layer 62, on one hand, since the second cap layer 62 is arranged on one side of the first cap layer 61 in the semiconductor device 10 far away from the substrate 1, namely, the first cap layer 61 is positioned between the second cap layer 62 and the barrier layer 5, in the process of forming the second cap layer 62 in the semiconductor device 10, under the condition that P-type impurities in the second cap layer 62 diffuse, the P-type impurities in the second cap layer 62 diffuse into the first cap layer 61 first, the P-type impurities diffuse into the barrier layer 5, the probability of introducing additional charges and the barrier layer 5 into the second cap layer can be reduced, the probability of the channel-type impurities to the barrier layer 5 is further improved, the probability of the channel-polarization of the first cap layer is further improved, the probability of the channel-coupling between the first cap layer 10 and the barrier layer is further improved, the channel-coupling effect of the second cap layer 10 is further improved, the probability of the channel-coupling between the first cap layer and the barrier layer 10 is further improved, and the channel-state probability of the channel-coupling performance of the semiconductor device is further improved, and the channel-coupling performance of the channel-state performance of the semiconductor device is further improved, and the channel-resistance is improved, and the probability of the channel-resistance performance of the channel-resistance-performance is improved, and the channel-performance is improved.

On the other hand, since the doping concentration of the first cap layer 61 (i.e., the concentration of the P-type impurity in the first cap layer 61) is smaller than the doping concentration of the second cap layer 62 (i.e., the concentration of the P-type impurity in the second cap layer 62), i.e., the doping concentration of the first cap layer 61 is smaller, the P-type impurity in the first cap layer 61 may not or slightly diffuse into the barrier layer 5 during the formation of the first cap layer 61 in the semiconductor device 10, which not only can further reduce the probability that the P-type impurity introduces additional charges and electric fields into the barrier layer 5 and interferes with the polarization effect of the barrier layer 5, but also can further reduce the probability that the characteristics of the connection interface between the first cap layer 61 and the barrier layer 5 changes (e.g., the trap state density of the connection interface between the first cap layer 61 and the barrier layer 5 increases, etc.), and further reduce the probability that the control capability of the gate layer G in the semiconductor device 10 affects, thereby further reducing the probability that the dynamic on-resistance of the semiconductor device 10 occurs, and further improving the reliability of the semiconductor device 10.

In yet another aspect, since the doping concentration of the first cap layer 61 (i.e., the concentration of the P-type impurity in the first cap layer 61) is smaller than the doping concentration of the second cap layer 62 (i.e., the concentration of the P-type impurity in the second cap layer 62), i.e., the doping concentration of the second cap layer 62 is greater, so that there is an energy band difference (e.g., a conduction band difference) between the second cap layer 62 and the barrier layer 5, the energy band difference (e.g., a conduction band difference) between the second cap layer 62 and the barrier layer 5 can be used to regulate and control the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) near the connection interface of the barrier layer 5 and the channel layer 4, which is beneficial to depleting the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) under the second cap layer 62, thereby enabling the semiconductor device 10 to implement the enhancement mode.

And because of the depletion effect of the second cap layer 62 in the semiconductor device 10 on the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) located under the second cap layer 62, the semiconductor device 10 needs to overcome a higher barrier when turned on, which is beneficial to increasing the threshold voltage of the semiconductor device 10.

Illustratively, the material of the first cap layer 61 and the material of the second cap layer 62 within the semiconductor device 10 may each include P-type gallium nitride (P-GaN). P-type gallium nitride (P-GaN) can be formed by doping a gallium nitride (GaN) material with elements such as iron (Fe) and magnesium (Mg).

For example, when doping elements such as iron (Fe) and magnesium (Mg) into a gallium nitride (GaN) material to form P-type gallium nitride (P-GaN), a Gas phase doping process (Gas-phase doping process) or an ion implantation process (Ion implantation process) may be used.

Illustratively, the doping concentration of the first capping layer 61 within the semiconductor device 10 may be less than or equal to 5×10 ¹⁷cm^-3. That is, the concentration of the P-type impurity (e.g., magnesium (Mg)) in the first capping layer 61 may be less than or equal to 5×10 ¹⁷ cm^-3.

For example, the doping concentration of the first capping layer 61 in the semiconductor device 10 may be 3×10 ¹⁷ cm^-3、4×10¹⁷cm^-3 or 5×10 ¹⁷ cm^-3 or the like.

Illustratively, the doping concentration of the second cap layer 62 within the semiconductor device 10 may be greater than or equal to 5×10 ¹⁸cm^-3 and less than or equal to 10×10 ¹⁹ cm^-3. That is, the concentration of the P-type impurity (e.g., magnesium (Mg)) within the second cap layer 62 may be greater than or equal to 5×10 ¹⁸ cm^-3 and less than or equal to 10×10 ¹⁹ cm^-3.

For example, the doping concentration of the second cap layer 62 within the semiconductor device 10 may be 5×10¹⁸ cm^-3、6×10¹⁸cm^-3、7×10¹⁸ cm^-3、8×10¹⁸ cm^-3、9×10¹⁸ cm^-3、10×10¹⁸ cm^-3、3×10¹⁹ cm^-3、5×10¹⁹ cm^-3、8×10¹⁹ cm^-3 or 10×10 ¹⁹ cm^-3, or the like.

Illustratively, with continued reference to fig. 5, 6, 7, and 8, the semiconductor device 10 includes at least one second cap layer 62.

For example, with continued reference to fig. 5 and 7, semiconductor device 10 may include a second cap layer 62.

For another example, referring still to fig. 6 and 8, the semiconductor device 10 may include a plurality of second cap layers 62. In the case where the semiconductor device 10 includes a plurality of second cap layers 62, the plurality of second cap layers 62 may be disposed at intervals along the first direction (i.e., the arrangement direction of the source S and the drain D within the semiconductor device 10) X.

Note that, in the embodiment shown in fig. 6 and 8, only the case where the semiconductor device 10 includes two second cap layers 62 is illustrated as an example, but in the case where the semiconductor device 10 includes a plurality of second cap layers 62, the number of second cap layers 62 in the semiconductor device 10 is not limited thereto, and the number of second cap layers 62 in the semiconductor device 10 may be set based on actual requirements, for example, the number of second cap layers 62 in the semiconductor device 10 may be 3, 4,5, 6, 7, 8, or the like.

For example, referring to fig. 5, 6, 7 and 8, the dimension h2 of the second cap layer 62 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is smaller than the dimension h1 of the first cap layer 61 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10).

Illustratively, as shown in fig. 9 and 10, fig. 9 and 10 are top schematic views of a first cap layer 61 and a second cap layer 62 within the semiconductor device 10 according to some embodiments. Note that fig. 9 differs from fig. 10 in that the semiconductor device 10 in the embodiment shown in fig. 9 includes one second cap layer 62, and the semiconductor device 10 in the embodiment shown in fig. 10 includes a plurality of (e.g., two) second cap layers 62.

The dimension D2 of the second cap layer 62 in the semiconductor device 10 along the second direction Y is the same as the dimension D1 of the first cap layer 61 in the semiconductor device 10 along the second direction Y, the second direction Y is perpendicular to the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, and both the second direction Y and the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X are parallel to the substrate 1 in the semiconductor device 10.

It should be noted that the above-mentioned "the dimension d2 of the second cap layer 62 in the semiconductor device 10 in the second direction Y is the same as the dimension d1 of the first cap layer 61 in the semiconductor device 10 in the second direction Y" means that the difference between the dimension d2 of the second cap layer 62 in the semiconductor device 10 in the second direction Y and the dimension d1 of the first cap layer 61 in the semiconductor device 10 in the second direction Y is within the preset threshold value range. The threshold range is a relatively small range of values, and for example, the threshold range may be a range of process accuracy when forming the first cap layer 61 and the second cap layer 62 having the same size in the second direction Y.

In the case where the dimension d2 of the second cap layer 62 in the semiconductor device 10 in the second direction Y is the same as the dimension d1 of the first cap layer 61 in the semiconductor device 10 in the second direction Y, the threshold value range of the difference between the dimension d2 of the second cap layer 62 in the semiconductor device 10 in the second direction Y and the dimension d1 of the first cap layer 61 in the semiconductor device 10 in the second direction Y may be 0 to 0.1 μm.

For example, in the case where the dimension d2 of the second cap layer 62 in the semiconductor device 10 in the second direction Y is the same as the dimension d1 of the first cap layer 61 in the semiconductor device 10 in the second direction Y, the difference between the dimension d2 of the second cap layer 62 in the semiconductor device 10 in the second direction Y and the dimension d1 of the first cap layer 61 in the semiconductor device 10 in the second direction Y may be 0, 0.01 μm, 0.03 μm, 0.05 μm, 0.06 μm, 0.08 μm, 0.1 μm, or the like.

For example, with continued reference to fig. 5, 6,7 and 8, in the case where the semiconductor device 10 includes the first cap layer 61 and the second cap layer 62, the source S and the drain D in the semiconductor device 10 may be located on opposite sides of the first cap layer 61 along the first direction X and both disposed on a side of the barrier layer 5 away from the substrate 1.

In some embodiments, referring to fig. 5, 6, 7 and 8, in the case that the semiconductor device 10 includes the first cap layer 61 and the second cap layer 62, the gate layer G in the semiconductor device 10 may be disposed on a side of the first cap layer 61 away from the substrate 1, and the gate layer G covers two sides of the second cap layer 62 opposite along the first direction X, and a surface of the side of the second cap layer 62 away from the substrate 1.

In the case where the semiconductor device 10 includes the first cap layer 61 and the second cap layer 62, by disposing the gate layer G in the semiconductor device 10 on the side of the first cap layer 61 away from the substrate 1, and covering both sides of the second cap layer 62 opposite in the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), and the side surface of the second cap layer 62 away from the substrate 1, i.e., between a partial region in the gate layer G and the first cap layer 61, the second cap layer 62 is not disposed, a partial Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) in the semiconductor device 10 can be collected by the partial region in the gate layer G and between the first cap layer 61 through the first cap layer 61 without passing through the second cap layer 62 in a state where the semiconductor device 10 is turned on (i.e., the gate layer G in the semiconductor device 10 is under a forward voltage bias).

On the one hand, since the doping concentration of the first cap layer 61 (i.e., the concentration of the P-type impurity in the first cap layer 61) is smaller than the doping concentration of the second cap layer 62 (i.e., the concentration of the P-type impurity in the second cap layer 62), i.e., the doping concentration of the first cap layer 61 is smaller, the electron traps in the first cap layer 61 are fewer, which is beneficial to reducing the probability that electrons in the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) are trapped by the electron traps during the transmission process, and further to maintaining the concentration of the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) near the connection interface of the barrier layer 5 and the channel layer 4, so that the stability of the concentration of the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) is higher, thereby being capable of avoiding or reducing the probability that the threshold voltage forward drift phenomenon occurs due to the trapping of electrons during the transmission process, and being beneficial to improving the stability of the threshold voltage of the semiconductor device 10.

On the other hand, since the doping concentration of the first capping layer 61 (i.e., the concentration of the P-type impurity in the first capping layer 61) is smaller, an approximately uniformly distributed electric field exists in the first capping layer 61, which is favorable for accelerating electrons in the first capping layer 61 and smoothly transitioning to the interface between the first capping layer 61 and the gate layer G, and can reduce scattering and energy loss of electrons in the transmission process, thereby being favorable for improving the performance stability of the semiconductor device 10.

On the other hand, since the doping concentration of the first cap layer 61 (i.e., the concentration of the P-type impurity in the first cap layer 61) is smaller than the doping concentration of the second cap layer 62 (i.e., the concentration of the P-type impurity in the second cap layer 62), that is, the doping concentration of the second cap layer 62 is larger, so that there is an energy band difference (e.g., conduction band difference) between the second cap layer 62 and the barrier layer 5, the energy band difference (e.g., conduction band difference) between the second cap layer 62 and the barrier layer 5 can be used to regulate and control the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) near the connection interface of the barrier layer 5 and the channel layer 4, which is beneficial to depleting the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) under the second cap layer 62, thereby enabling the semiconductor device 10 to implement the enhancement mode.

In summary, in the case where the semiconductor device 10 includes the first cap layer 61 and the second cap layer 62, by disposing the gate layer G in the semiconductor device 10 on the side of the first cap layer 61 away from the substrate 1, and covering both sides of the second cap layer 62 opposite in the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), and the side surface of the second cap layer 62 away from the substrate 1, the stability of the threshold voltage of the semiconductor device 10 and the performance stability of the semiconductor device 10 can be improved while the threshold voltage of the semiconductor device 10 is improved.

For example, referring to fig. 5, 6, 7 and 8, the gate layer G in the semiconductor device 10 may be in contact with a portion of the surface of the first cap layer 61.

For example, referring to fig. 5, 6,7 and 8, the dimension hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is smaller than or equal to the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10).

For example, referring still to fig. 5 and 6, the dimension hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is smaller than the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10).

For another example, referring to fig. 7 and 8, a dimension hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is equal to a dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10).

Note that the above-described "the dimension hG of the gate layer G in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is equal to the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X" means that the difference between the dimension hG of the gate layer G in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is within the preset threshold value range. The threshold range is a relatively small range of values, and for example, the threshold range may be a range of process accuracy when forming the first cap layer 61 and the gate layer G equal in size in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X.

In the case where the dimension hG of the gate layer G in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is equal to the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, the threshold range of the difference between the dimension hG of the gate layer G in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X may be 0 to 2 μm.

For example, in the case where the dimension hG of the gate layer G in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is equal to the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, the difference between the dimension hG of the gate layer G in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X may be 0, 0.1 μm, 0.3 μm, 0.6 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.6 μm, 1.8 μm, 2 μm, or the like.

In some embodiments, as shown in fig. 11, 12, 13, and 14, fig. 11, 12, 13, and 14 are cross-sectional schematic views of semiconductor device 10 according to some embodiments. Note that, the difference between fig. 11 and 12, and fig. 13 and 14 is that, in the embodiment shown in fig. 11 and 12, the dimension hG of the gate layer G in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) is smaller than the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), and the dimension hG of the gate layer G in the semiconductor device 10 in the embodiment shown in fig. 13 and 14 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) is equal to the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X.

Fig. 11 and 13 differ from fig. 12 and 14 in that the semiconductor device 10 in the embodiment shown in fig. 11 and 13 includes one second cap layer 62, and the semiconductor device 10 in the embodiment shown in fig. 12 and 14 includes a plurality (e.g., two) of second cap layers 62.

With continued reference to fig. 11, 12, 13, and 14, the semiconductor device 10 may further include a protective layer 8. The protective layer 8 may be disposed between the first cap layer 61 and the second cap layer 62 within the semiconductor device 10.

The protective layer 8 and the first capping layer 61 within the semiconductor device 10 overlap in the third direction (i.e., the thickness direction of the substrate 1 within the semiconductor device 10) Z. I.e. the shape and size of the cross section of the protective layer 8 perpendicular to the third direction (i.e. the thickness direction of the substrate 1 in the semiconductor device 10) Z is the same as the shape and size of the cross section of the first cap layer 61 perpendicular to the third direction (i.e. the thickness direction of the substrate 1 in the semiconductor device 10) Z.

For example, referring still to fig. 11, 12, 13 and 14, the dimension h8 of the protective layer 8 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is the same as the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10).

It should be noted that the above-described "the dimension h8 of the protective layer 8 in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is the same as the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X" means that the difference between the dimension h8 of the protective layer 8 in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is within the preset threshold value range. The threshold range is a relatively small range of values, and for example, the threshold range may be a range of process accuracy when forming the first cap layer 61 and the protective layer 8 having the same size in the first direction (i.e., the arrangement direction of the source electrode S and the drain electrode D in the semiconductor device 10) X.

In the case where the dimension h8 of the protective layer 8 in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) is the same as the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, the threshold value range of the difference between the dimension h8 of the protective layer 8 in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X may be 0 to 0.5 μm.

For example, in the case where the dimension h8 of the protective layer 8 in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) is the same as the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, the difference between the dimension h8 of the protective layer 8 in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X may be 0, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, or the like.

In the case where the semiconductor device 10 includes the first cap layer 61 and the second cap layer 62, by disposing the protective layer 8 between the first cap layer 61 and the second cap layer 62 with the protective layer 8 and the first cap layer 61 overlapping in the third direction (i.e., the thickness direction of the substrate 1 in the semiconductor device 10) Z, the function of protecting the first cap layer 61 can be performed when the second cap layer 62 in the semiconductor device 10 is formed by an etching process, damage to the first cap layer 61 due to the etching process can be avoided, which is advantageous for improving the performance of the finally formed semiconductor device 10 and improving the reliability of the semiconductor device 10.

For example, with continued reference to fig. 11, 12, 13 and 14, the material of the protective layer 8 and the material of the second cap layer 62 within the semiconductor device 10 are different.

By making the material of the protective layer 8 and the material of the second cap layer 62 in the semiconductor device 10 different, so that the etching rate of the material of the protective layer 8 and the etching rate of the material of the second cap layer 62 are different when the second cap layer 62 in the semiconductor device 10 is formed by the etching process, the material of the protective layer 8 and the material of the second cap layer 62 can be selectively etched when the second cap layer 62 in the semiconductor device 10 is formed by the etching process, so that the etching process stops at the protective layer 8, the protective layer 8 is facilitated to protect the first cap layer 61 disposed on the side of the protective layer 8 away from the second cap layer 62, damage to the first cap layer 61 due to the etching process is avoided, the performance of the finally formed semiconductor device 10 is facilitated to be improved, and the reliability of the semiconductor device 10 is improved.

Illustratively, the material of the protective layer 8 within the semiconductor device 10 may include at least one of aluminum gallium nitride (AlGaN) and aluminum nitride (AlN).

For example, the material of the protective layer 8 in the semiconductor device 10 may include aluminum gallium nitride (AlGaN) or aluminum nitride (AlN).

As another example, the material of the protective layer 8 in the semiconductor device 10 may include aluminum gallium nitride (AlGaN) and aluminum nitride (AlN).

Illustratively, the material of the protective layer 8 within the semiconductor device 10 may comprise a P-type doped semiconductor material, and the doping concentration of the protective layer 8 is less than the doping concentration of the second cap layer 62.

For example, the material of the protective layer 8 in the semiconductor device 10 may include at least one of P-type aluminum gallium nitride (P-AlGaN) and P-type aluminum nitride (P-AlN).

P-type aluminum gallium nitride (P-AlGaN) may be formed by doping an aluminum gallium nitride (AlGaN) material with elements such as iron (Fe) and magnesium (Mg). The P-type aluminum nitride (P-AlN) may be formed by doping an element such as iron (Fe) or magnesium (Mg) into an aluminum nitride (AlN) material.

The method of manufacturing the semiconductor device 10 will be described in detail below.

In some embodiments, as shown in fig. 15, fig. 15 is a flow chart of a method of fabricating semiconductor device 10 according to some embodiments. It should be noted that the method of manufacturing the semiconductor device 10 shown in fig. 15 is not exclusive, and that other steps may be performed before, after, or between any of the steps in the method of manufacturing the semiconductor device 10 shown in fig. 15. The method for manufacturing the semiconductor device 10 includes steps S1 to S4.

S1 as shown in fig. 16, fig. 16 is a schematic structural diagram of the semiconductor device 10 corresponding to step S1 in the flowchart of the manufacturing method of the semiconductor device 10 in fig. 15. A barrier layer 5 is formed on one side of the substrate 1.

Illustratively, the barrier layer 5 may be formed on one side of the substrate 1 within the semiconductor device 10 by a Metal-organic chemical vapor deposition process (Metal-organic Chemical Vapor Deposition, MOCVD), a molecular beam epitaxy process (Molecular Beam Epitaxy, MBE), or a physical vapor deposition process (Physical Vapor Deposition, PVD) or the like.

S2 as shown in fig. 17, fig. 17 is a schematic structural diagram of the semiconductor device 10 corresponding to step S2 and step S3 in the flowchart of the manufacturing method of the semiconductor device 10 in fig. 15. A first capping layer 61 is formed on the side of the barrier layer 5 remote from the substrate 1.

With continued reference to fig. 17, a second cap layer 62 is formed on the side of the first cap layer 61 remote from the substrate 1.

S4 as shown in fig. 18, fig. 18 is a schematic structural diagram of the semiconductor device 10 corresponding to step S4 in the flowchart of the method for manufacturing the semiconductor device 10 in fig. 15. Forming a source electrode S and a drain electrode D. The source S and the drain D are located on opposite sides of the first capping layer 61 along a first direction X, and are both disposed on a side of the barrier layer 5 away from the substrate 1, the first direction X being parallel to the substrate 1.

Illustratively, portions of the barrier layer 5 of the source and drain regions may be removed by a photolithography process to thin the thickness of the barrier layer 5, facilitating the formation of the source S and drain D. When part of the barrier layer 5 of the source region and the drain region is removed by a photolithography process, a mixed gas such as Cl ₂/ClB₃ may be used as an etching gas.

Illustratively, the source S and drain D may be formed by growing source-drain metals (e.g., titanium (Ti), aluminum (Al), titanium nitride (TiN), etc.) through a sputtering process, and removing the source-drain metals (e.g., titanium (Ti), aluminum (Al), titanium nitride (TiN), etc.) outside the source and drain regions through a dry etching process.

The dimension h2 of the second cap layer 62 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is smaller than the dimension h1 of the first cap layer 61 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X.

The first cap layer 61 and the second cap layer 62 within the semiconductor device 10 each comprise a P-type doped semiconductor material, and the doping concentration of the first cap layer 61 is less than the doping concentration of the second cap layer 62.

In yet another aspect, since the doping concentration of the first cap layer 61 (i.e., the concentration of the P-type impurity in the first cap layer 61) is smaller than the doping concentration of the second cap layer 62 (i.e., the concentration of the P-type impurity in the second cap layer 62), i.e., the doping concentration of the second cap layer 62 is greater, so that there is an energy band difference (e.g., a conduction band difference) between the second cap layer 62 and the barrier layer 5, the energy band difference (e.g., a conduction band difference) between the second cap layer 62 and the barrier layer 5 can be used to regulate and control the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) near the connection interface of the barrier layer 5 and the channel layer 4, which is beneficial to depleting the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) under the second cap layer 62, thereby enabling the semiconductor device 10 to implement the enhancement mode. And because of the depletion effect of the second cap layer 62 in the semiconductor device 10 on the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) located under the second cap layer 62, the semiconductor device 10 needs to overcome a higher barrier when turned on, which is beneficial to increasing the threshold voltage of the semiconductor device 10.

In some embodiments, referring to fig. 15, step S2 (i.e. forming the first cap layer 61) and step S3 (i.e. forming the second cap layer 62) in the method for manufacturing the semiconductor device 10 include steps S231-S233.

With continued reference to fig. 17, a first initial cap layer 61a and a second initial cap layer 62a are sequentially formed on the side of the barrier layer 5 away from the substrate 1.

Illustratively, the first and second initial cap layers 61a and 62a may be sequentially formed on the side of the barrier layer 5 remote from the substrate 1 within the semiconductor device 10 by a Metal-organic chemical vapor deposition process (Metal-organic Chemical Vapor Deposition, MOCVD), a molecular beam epitaxy process (Molecular Beam Epitaxy, MBE), or a physical vapor deposition process (Physical Vapor Deposition, PVD) or the like.

Illustratively, the first initial cap layer 61a and the second initial cap layer 62a each comprise a P-type doped semiconductor material, and the doping concentration of the first initial cap layer 61a is less than the doping concentration of the second initial cap layer 62 a.

For example, the material of the first initial cap layer 61a and the material of the second initial cap layer 62a may each include P-type gallium nitride (P-GaN). P-type gallium nitride (P-GaN) can be formed by doping a gallium nitride (GaN) material with elements such as iron (Fe) and magnesium (Mg).

Illustratively, in the case where the first and second initial cap layers 61a and 62a each include a P-type doped semiconductor material and the doping concentration of the first initial cap layer 61a is less than the doping concentration of the second initial cap layer 62a, a Gas phase doping process (Gas-phase doping process) or an ion implantation process (Ion implantation process) or the like may be employed to dope P-type impurities (e.g., magnesium (Mg)) in the semiconductor material (e.g., gallium nitride (GaN)) to form the first and second initial cap layers 61a and 62a, respectively.

Or a P-type impurity (e.g., magnesium (Mg)) may be doped in a semiconductor material (e.g., gallium nitride (GaN)) using a Gas phase doping process (Gas-phase doping process) or an ion implantation process (Ion implantation process) or the like to form the second initial cap layer 62a.

During formation of the second initial cap layer 62a, a portion of the P-type impurity (e.g., magnesium (Mg)) within the second initial cap layer 62a diffuses into the first initial cap layer 61a such that the first initial cap layer 61a comprises a P-type doped semiconductor material.

With continued reference to fig. 17, the first and second initial cap layers 61a and 62a, which are to form the source region Sa and the drain region Da, are removed to form the first and third cap layers 61 and 63. The first cap layer 61 and the third cap layer 63 overlap in the thickness direction of the substrate 1.

Illustratively, the first and second preliminary cap layers 61a and 62a to form the source region Sa and the drain region Da may be removed using a photolithography process to form the first and third cap layers 61 and 63.

In removing the first and second preliminary cap layers 61a and 62a to form the source region Sa and the drain region Da using a photolithography process, a mixed gas such as Cl ₂/N₂/O₂ may be used as an etching gas.

Referring to fig. 17, a portion of the third cap layer 63 is removed to form a second cap layer 62.

Illustratively, a photolithographic process may be employed to remove a portion of the third cap layer 63 to form the second cap layer 62. In removing a portion of the third cap layer 63 using a photolithography process, a mixed gas such as Cl ₂/N₂/O₂ may be used as an etching gas.

In some embodiments, referring to fig. 15, the method for manufacturing the semiconductor device 10 may further include step S5.

S5 as shown in fig. 19, the semiconductor device 10 corresponding to step S5 and step S6 in the flowchart of the method for manufacturing the semiconductor device 10 in fig. 19 is schematically illustrated. A gate layer G is formed on a side of the first capping layer 61 remote from the substrate 1. The gate layer G covers both sides of the second cap layer 62 opposite in the first direction X, and a side surface of the second cap layer 62 remote from the substrate 1.

Illustratively, the gate electrode layer G may be formed by growing a gate metal (e.g., titanium nitride (TiN) or the like) through a sputtering process, and removing the gate metal (e.g., titanium nitride (TiN) or the like) outside the gate region through a dry etching process.

In the case where the semiconductor device 10 includes the first cap layer 61 and the second cap layer 62, by disposing the gate layer G in the semiconductor device 10 on the side of the first cap layer 61 away from the substrate 1 and covering the Two opposite sides of the second cap layer 62 in the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), and not disposing the second cap layer 62 between the partial region in the gate layer G and the first cap layer 61, in a state where the semiconductor device 10 is turned on (i.e., the gate layer G in the semiconductor device 10 is biased by a forward voltage), a portion of the Two-dimensional electron gas (Two-dimensional electron gas,2 DEG) in the semiconductor device 10 can be collected by the partial region in the gate layer G and not disposed with the second cap layer 62 in the first cap layer 61 without passing through the second cap layer 62, on the one hand, since the doping concentration of the first cap layer 61 (i.e.e., the partial region in the gate layer G) is far away from the substrate 1, and the second cap layer 62 is advantageously lower than the Two-dimensional electron gas (Two-35) in the second cap layer 62, the Two-dimensional electron gas (Two-35) is trapped in the Two-dimensional electron gas concentration of the second cap layer 35 to the Two-35, the electron gas-trap concentration of the Two-electron gas (Two-35) in the Two-dimensional electron gas trap layer 35) is reduced in the Two-trap layer of the Two-trap layer (35P-35), 2 DEG) is higher, so that the probability of occurrence of a threshold voltage forward drift phenomenon due to capture of electrons by electron traps in the transmission process can be avoided or reduced, which is beneficial to improving the stability of the threshold voltage of the semiconductor device 10.

In some embodiments, referring to fig. 15, the method for manufacturing the semiconductor device 10 may further include step S6.

S6, please continue to refer to FIG. 19, a passivation layer 7 is formed. The passivation layer 7 covers the gate layer G, the source electrode S, and the drain electrode D within the semiconductor device 10.

By forming the passivation layer 7 in the semiconductor device 10, and the passivation layer 7 covers the gate layer G, the source electrode S, and the drain electrode D in the semiconductor device 10, on the one hand, the passivation layer 7 can block harmful substances (e.g., oxygen, water, etc.) in the external environment, prevent the harmful substances (e.g., oxygen, water, etc.) in the external environment from directly contacting the source electrode S, the drain electrode D, and the gate layer G in the semiconductor device 10, which results in damage to the source electrode S, the drain electrode D, and the gate layer G in the semiconductor device 10, thereby facilitating improvement of stability of the semiconductor device 10, and facilitating prolongation of the service life of the semiconductor device 10.

In fig. 17 and 18, only the case where the semiconductor device 10 includes one second cap layer 62 is taken as an example, and steps S2, S3, and S4 in the manufacturing method of the semiconductor device 10 are schematically illustrated. In fig. 19, only the second cap layer 62 is taken as an example, and the dimension hG of the gate layer G in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is smaller than the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), step S5 in the manufacturing method of the semiconductor device 10 is schematically illustrated. However, the size relationship between the number of the second cap layers 62 in the semiconductor device 10, and the size hG of the gate layer G in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), and the size h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X in the present disclosure is not limited thereto, and the size relationship between the number of the second cap layers 62 in the semiconductor device 10, and the size hG of the gate layer G in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), and the size h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X may be set according to actual requirements.

For example, the number of second cap layers 62 in the semiconductor device 10 may be plural.

As another example, the dimension hG of the gate layer G in the semiconductor device 10 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X may be equal.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A semiconductor device, comprising:

substrate;

A barrier layer, disposed on one side of the substrate;

A first capping layer is disposed on a side of the barrier layer away from the substrate;

A second capping layer is disposed on a side of the first capping layer away from the substrate;

a source electrode and a drain electrode, located at opposite sides of the first cap layer along a first direction, and both arranged on a side of the barrier layer away from the substrate, wherein the first direction is parallel to the substrate;

A gate layer is arranged on a side of the first cap layer away from the substrate; the gate layer covers two side surfaces of the second cap layer that are opposite to each other along the first direction, and a surface of the second cap layer that is away from the substrate;

Wherein, the size of the second capping layer along the first direction is smaller than the size of the first capping layer along the first direction;

The first capping layer and the second capping layer both include P-type doped semiconductor materials, and the doping concentration of the first capping layer is less than the doping concentration of the second capping layer.

2 . The semiconductor device according to claim 1 , wherein the semiconductor device comprises a plurality of the second capping layers, and the plurality of the second capping layers are spaced apart along the first direction.

3 . The semiconductor device according to claim 1 , wherein the gate layer contacts a portion of a surface of the first capping layer.

4 . The semiconductor device according to claim 1 , wherein a dimension of the gate layer along the first direction is smaller than or equal to a dimension of the first cap layer along the first direction.

5 . The semiconductor device according to claim 1 , wherein a size of the second capping layer along a second direction is the same as a size of the first capping layer along the second direction, the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

6 . The semiconductor device according to claim 1 , wherein a doping concentration of the first capping layer is less than or equal to 5×10 ¹⁷ cm ⁻³ .

7 . The semiconductor device according to claim 6 , wherein a doping concentration of the second capping layer is greater than or equal to 5×10 ¹⁸ cm ⁻³ and less than or equal to 10×10 ¹⁹ cm ⁻³ .

8. The semiconductor device according to any one of claims 1-2 and 4-7, characterized in that the semiconductor device further comprises a protection layer disposed between the first cap layer and the second cap layer;

The protection layer and the first capping layer overlap in a thickness direction of the substrate.

9 . The semiconductor device according to claim 8 , wherein a material of the protection layer is different from a material of the second capping layer.

10 . The semiconductor device according to claim 9 , wherein the material of the protection layer comprises at least one of aluminum gallium nitride and aluminum nitride.

11 . The semiconductor device according to claim 8 , wherein the material of the protection layer comprises a P-type doped semiconductor material, and the doping concentration of the protection layer is less than the doping concentration of the second capping layer.

12. A method for preparing a semiconductor device, comprising:

forming a barrier layer on one side of the substrate;

forming a first capping layer on a side of the barrier layer away from the substrate;

forming a second capping layer on a side of the first capping layer away from the substrate;

forming a source electrode and a drain electrode; the source electrode and the drain electrode are located on opposite sides of the first cap layer along a first direction, and are both arranged on a side of the barrier layer away from the substrate, and the first direction is parallel to the substrate;

A gate layer is formed on a side of the first cap layer away from the substrate; the gate layer covers two side surfaces of the second cap layer that are opposite to each other along the first direction, and a surface of the second cap layer that is away from the substrate;

13. The method for preparing a semiconductor device according to claim 12, wherein the forming of the first capping layer and the forming of the second capping layer comprise:

forming a first initial capping layer and a second initial capping layer in sequence on a side of the barrier layer away from the substrate;

removing the first initial capping layer and the second initial capping layer in the to-be-formed source region and the to-be-formed drain region to form a first capping layer and a third capping layer, wherein the first capping layer and the third capping layer overlap in the thickness direction of the substrate;

A portion of the third capping layer is removed to form a second capping layer.

14. A chip, characterized by comprising the semiconductor device according to any one of claims 1 to 11.

15. An electronic device, comprising:

Circuit boards;

The chip as claimed in claim 14, wherein the chip is electrically connected to the circuit board.