CN119210347A - Electronic Circuits - Google Patents

Abstract

An electronic circuit includes a reference clock signal generator block and a functional module. In response to a fault detected on a signal originating from the reference frequency generator of the reference clock signal generator block, only the reference frequency generator of the reference clock signal generator block is reset, without resetting the functional module.

Description

Electronic circuit

Priority statement

The present application claims the benefit of priority from French patent application No.2306702 filed on 27, 6, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law.

Technical Field

The present disclosure relates generally to electronic circuits.

Background

For internal processes of electronic circuits, the electronic circuit generally comprises a reference oscillator in the form of a quartz oscillator, the quartz oscillator having its crystal, when powered on, delivering a signal having a frequency that is used as a reference to generate a time sequence such as a clock signal.

The reference oscillator may be sensitive to, for example, power supply variations or to environmental parameters external to the circuit, which lead to transient or permanent failures. The impact of these faults on the general circuit operation poses a problem.

It is desirable to obtain an electronic circuit that reduces the effects of faults in the reference oscillator.

It is desirable to overcome all or part of the disadvantages of known electronic circuits.

Disclosure of Invention

An embodiment provides an electronic circuit comprising a reference clock signal generator circuit and a functional circuit, the electronic circuit being configured to reset the reference clock signal generator circuit only when a fault on a signal originating from a reference frequency generator of the reference clock signal generator circuit is detected.

An embodiment provides a method of controlling an electronic circuit comprising a reference clock signal generator circuit and a functional circuit, the method comprising the step of resetting the reference clock signal generator circuit only when a fault on a signal originating from a reference frequency generator of the reference clock signal generator circuit is detected.

In an embodiment, the electronic circuit further comprises a control circuit configured to generate a signal for resetting the reference frequency generator when a fault on said signal originating from the reference frequency generator is detected, the signal being different from a reset signal common to said functional circuit and to said reference clock signal generator circuit.

In an embodiment the reference clock signal generator circuit comprises a detection circuit configured to detect whether said signal originating from the reference frequency generator is faulty and to generate a fault status signal at the output of the detection circuit depending on the result of the detection.

In an embodiment, the reference clock signal generator circuit comprises a flip-flop having a clock input coupled to an output of the detection circuit AND a reset input coupled to a first logic circuit block configured to perform an AND (AND) type logic function between an inverse of a signal for resetting the reference clock signal generator AND a reset signal common to the functional circuit AND to the reference clock signal generator circuit.

In an embodiment, the reference clock generator circuit comprises a control element having a reset input coupled to a second logic circuit configured to perform an AND logic function between a signal present on an inverting output of the flip-flop and the reset signal common to the functional circuit and to the reference clock signal generator circuit.

In an embodiment, the control element comprises an oscillator output configured to transmit a signal for controlling the reference frequency generator.

In an embodiment, the signal for controlling the reference frequency generator is configured to stop the reference frequency generator when the reset input of the control element is enabled.

In an embodiment the control element comprises a clock output configured to transmit a reference clock signal having a reference frequency, and a clock input configured to receive said signal originating from the reference frequency generator, the control element being configured such that the clock output transmits the reference clock signal based on said signal originating from the reference frequency generator after a given number of cycles have been verified.

In an embodiment, the flip-flop is coupled to the output of the detection circuit via a third logic circuit module configured to perform an AND logic function between the fault state signal and the signal for enabling the detection circuit.

In one embodiment, the flip-flop includes a data input that is set to state one.

In one embodiment, the flip-flop is a D-type flip-flop.

In an embodiment, the inverting output of the flip-flop is configured to be reset when the reset input is enabled.

In one embodiment, the reset input of the flip-flop is enabled when it receives a signal at 0.

In one embodiment, the reset input of the control element is enabled when it receives a signal at 0.

Drawings

The above features and advantages and other features and advantages are described in detail in the remainder of the disclosure of particular embodiments, which are presented by way of illustration and not of limitation with reference to the accompanying drawings wherein:

fig. 1 very schematically shows an example of an integrated circuit in the form of a circuit module;

Fig. 2 very schematically shows a circuit module of the integrated circuit of fig. 1 in the form of a circuit module, and

Fig. 3 shows very schematically in the form of a flow chart a method of controlling the circuit of fig. 2.

Detailed Description

Like features have been designated with like reference numerals throughout the several views. In particular, structural and/or functional features common to the various embodiments may have the same reference numerals and may be arranged with the same structural, dimensional, and material characteristics.

For clarity, only the steps and elements that are helpful in understanding the described embodiments have been illustrated and described in detail.

Unless otherwise indicated, when two elements are referred to as being connected together, this means that there is no direct connection of any intermediate elements other than conductors, and when two elements are referred to as being coupled together, this means that the two elements may be connected or coupled via one or more other elements.

In the following description, when referring to terms such as "edge," "rear/back," "top," "bottom," "left," "right," etc., that define an absolute position, or terms such as "above," "below," "upper," "lower," etc., that define a direction (such as the terms "horizontal," "vertical," etc.), unless otherwise indicated, refer to the orientation of the drawings.

Unless otherwise specified, the expressions "left and right", "approximately", "substantially" and "about" mean plus or minus 10%, preferably plus or minus 5%.

Fig. 1 shows very schematically an example of an integrated circuit 100 in the form of a circuit module.

The circuit 100 includes, for example, a processing circuit module 104 (CTRL), the processing circuit module 104 including one or more processors, e.g., under the control of instructions stored in an instruction memory (not shown).

The circuit 100 further includes a clock circuit module 106 (REF) having a reference clock signal generation circuit that includes an oscillator that generates a reference frequency.

The apparatus 100 may integrate other circuitry implementing other functions, such as one or more volatile and/or non-volatile memory, other processing units, input/output interfaces (I/O), represented in fig. 1 by functional circuit block 102 (FCT).

The circuit modules 102, 104, and 106 are coupled to each other and/or to the rest of the integrated circuit 100, for example, via a bus 108 that carries the desired signals.

The circuit modules 102 and/or 104 and/or 106 further include other functional circuitry. The reference clock signal generation circuit module and the functional circuits are configured to be reset by at least one reset signal common to the functional circuits and to the reference clock signal generation circuit module.

The present description more particularly relates to a clock circuit module 106 that generates a reference clock signal that is used, for example, in the process implemented by the other circuit modules 102, 104.

The reference oscillator of the reference clock signal generator circuit module may be sensitive to, for example, power supply variations or to environmental parameters external to the circuit 100, which results in transient or permanent failures. In the current embodiment, these faults cause an overall restart of the circuit 100.

In the described embodiment, the circuit module 106 is configured to reset the reference clock signal generator circuit module only when a fault on the signal originating from the reference frequency generator oscillator is detected. This enables to avoid a complete restart of the circuit 100 when the fault is, for example, likely to be only a transient fault.

Fig. 2 shows very schematically a circuit module of the integrated circuit 100 of fig. 1 in the form of a circuit module.

More specifically, fig. 2 depicts the reference clock signal generator circuit block 106 as well as other functional circuits, such as the circuit blocks 102, 104 (other circuit blocks) external to the circuit block 106 or other functional circuit blocks 240 internal or external to the circuit block 106.

The reference clock signal generator circuit block 106 includes a reference frequency generator 202 (oscillator), which is, for example, a crystal oscillator, such as a quartz crystal oscillator oscillating at 32,768 khz. For example, the reference frequency generator 202 generates a clock signal (OscClk) having a reference frequency on the output 202b under the influence of a signal applied to the input 202 a.

In the example shown, the reference clock signal generator circuit module further includes a clock detection circuit 204 (clock detector) whose input 204c is coupled (preferably connected) to the output 202b of the generator 202 at node 220. The detection circuit 204 is configured to detect whether said signal OscClk originating from the reference frequency generator 202 exhibits a fault, e.g. whether a period of time is lost or a desired frequency is not adhered to, and to generate an alarm signal (ClkFail) at the output 204a of the detection circuit, the state of which is modified according to the detection result, e.g. state 0 when no fault is detected, and to switch to state 1 with a rising edge when a fault is detected. In one example, the detection circuit 204 is a state machine. For example, the signal ClkFail may also be accessed in a register and can send an event to the control unit 270 (such as, for example, the circuit module 104) to indicate to the control unit 270 that a fault has occurred and to record an error.

In the example shown, the start and stop of the detection circuit 204 is controlled, for example, by an enable control signal (ClkDetEn).

The output 204a of the detection circuit and the detection circuit control signal ClkDetEn are coupled to inputs of the logic circuit module 212, which logic circuit module 212 is configured to perform an AND logic function according to its inputs.

In the example shown, the output of the logic circuit module 212 is coupled (preferably connected) to a clock input 210b (commonly referred to as CP input) of a flip-flop 210 (FF, memory element), such as a D-type flip-flop, for example with falling or rising edge detection. In the example shown, the flip-flop is provided with rising edge detection and further includes a reset input 210a (resetbar), a data input 210c (D) (e.g., set to 1), and an inverted output 210D (Qn), commonly referred to as Qbar. In the example of fig. 2, the enabling of input 210a is performed by falling edge detection when the signal switches to 0. The reset input 210a of the flip-flop 210 is coupled (preferably connected) to an output of the logic circuit module 214, the logic circuit module 214 being configured to perform an and-type function in dependence on a reset signal (resetn) common to the functional circuit modules 102 and/or 104 and/or 240 and to the reference clock generator circuit module 106 and in dependence on a signal (ClkReArm) for resetting the reference clock generator circuit module. The reset signal (resetn) common to the functional circuit blocks 102 and/or 104 and/or 240 is, for example, at 0 when no reset is applied, and is set to 1 on the rising edge when the overall reset of the circuit 100 is controlled, for example, by the circuit block 104.

The logic circuit module 214 is implemented based on, for example, combinational logic and sequential logic. The signal ClkReArm for resetting the reference frequency generator circuit module includes, for example, pulses controlled by a program (e.g., implemented by circuit module 104).

In the illustrated example, the reference clock signal generator circuit module 106 includes another logic circuit module 222, the logic circuit module 222 being configured to perform an and function based on the output signal 210d of the flip-flop 210 and a reset signal (resetn) common to the functional circuit modules 102 and/or 104 and/or 240 and to the reference clock generator circuit module 106.

In the illustrated example, the reference clock generator circuit module 106 includes a control circuit element 224 (start-up control). The circuit block 224 is, for example, a counter-based digital circuit block. The reset input 224a (resetbar) of the control element 224 is configured to receive an output signal (ClkOK) from the logic circuit module 222. When input 224a receives a signal past 0, control element 224 is reset. Clock input 224b (ClkIn) of control element 224 is configured to receive a signal (OscClk) from the reference frequency generator. The oscillator control output 224c (SrcEn) of the control element 224 is coupled (preferably connected) to the logic circuit module 208 of the reference clock generator circuit module 106. The logic circuit module 208 is configured to perform an and function based on the signal presented at the oscillator control output 224c and based on a signal (OscEn) for enabling the oscillator (which corresponds to a user-determined parameter, for example). Oscillator enable signal OscEn includes one or more bits, for example, allocated by a user, to enable or disable reference frequency generator 202. The output of the logic circuit module 208 is configured to transmit a control signal to the reference frequency generator at the input 202a of the reference frequency generator 202.

The control element 224 further includes an output 260, the output 260 transmitting a signal (Ready) indicating whether the reference clock signal is Ready to be transmitted by applying a delay, for example, equal to or greater than the oscillator settling time. This delay may be obtained, for example, by counting N cycles of the clock signal, N being, for example, greater than 100, for example equal to 4096.

When the clock signal has been verified, the output 250 of the control element 224 provides a reference clock signal (ClkOut) having a reference frequency. This signal ClkOut is used, for example, by a security circuit module storing the time 230 (RTC, real time clock) or may be used by other circuit modules to generate a time sequence, for example (timer).

Resetting control element 224 by common reset signal resetn or by reset signal ClkReArm, for example, includes stopping signal ClkOut and setting output 224c to 0, which stops reference frequency generator 202. When input 224a is at 0, control element 224 is reset. As long as input 224a is at 0, control element 224 will remain stopped. When input 224a switches to 1, circuit block 224 is again operational.

In operation, when the detection circuit 204 is activated by the control bit ClkDetEn, which is set to 1 in operation, for example, the detection circuit 204 detects whether there is a fault on the signal from the reference frequency generator 202, such as, for example, no signal or an erroneous frequency.

When a fault is detected, signal ClkFail changes, e.g., switches to a high level, and a rising edge is generated. The output of logic circuit block 212 includes a high signal with a rising edge applied to flip-flop 210 on clock input 210 b. Output 210d is then in state 0. The common reset signal resetn defaults to 1, whereby input 224a resetbar is set to 0, which triggers a reset of control element 224.

At this stage, only a full restart (power up) of the circuit, or a modification of signal resetn or signal ClkReArm, enables restarting of the oscillator. However, both power up of the circuit and modification of the signal resetn may result in a reset of all functional circuit modules 102, 104, and may also result in a overwriting of the security key from memory. This leads to delays in the use of the circuit and may also lead to safety problems. Thus, depending on the type of fault (temporary or permanent), a reset of the different functional circuit modules 102, 104 (in the case of a reset by modification resetn) or a reset of the circuit module 106 alone (in the case of a reset by modification ClkReArm) may be preferred.

The control unit 270, having received bit ClkFail set to 1, modifies the state of the signal ClkReArm or resetn. The selection of the signal to be modified is performed, for example, according to the type of transient or permanent fault.

The first way to determine if the fault is a transient fault is to count the number of times the signal ClkFail toggles to 1 at the time counted using the RTC module 230. This provides a failure rate that is compared to a threshold.

The second approach is to check if the power mode of the circuit 100 has been modified, for example by switching from active mode to very low power mode, when the signal ClkFail switches to 1. In fact, this may generate oscillator power supply disturbances and potential faults that are related to such variations and are therefore a priori instantaneous.

In order to reset only the circuit block 106, thereby avoiding the need to reset multiple functional circuit blocks external to the circuit block 106, the signal ClkReArm for resetting the reference frequency generator circuit block is then set high with a rising edge or in the form of a pulse. In this case, signal resetn remains at 1 or high. Signal ClkReArm is inverted prior to the and function of logic circuit block 214, and reset input 210a of flip-flop 210 receives a falling edge past 0, which enables reset of flip-flop 210 and switching of its Qn output 210d to 1. Because resetn remains at 1, then the output signal ClkOK of the logic circuit module 222 is at 1 (or high). The reset of the control element 224 is then disabled, since the control element 224 is only active when a signal at 0 is applied to the input 224 a.

In order to also reset a plurality of functional circuit blocks external to the circuit block 106, for example because there is no signal originating from an oscillator or the detected error rate is above a threshold value, the common reset signal resetn is then set to 0 or low with a falling edge. In this case, signal ClkReArm remains at 0 or low. The reset input 210a of the flip-flop 210 thus receives a falling edge passing through 0, which enables resetting the flip-flop 210 and switching its Qn output 210d to 1. Because resetn is at 0, the output signal ClkOK of the logic circuit module 222 is at 1. The reset 224a of the control element 224 is then disabled because it is only active when the input 224a is at 0.

Fig. 3 shows very schematically in the form of a flow chart a method of controlling the circuit of fig. 2.

At step 302 (clock failure detected), a failure on the signal from the reference frequency generator 202 is detected by the detection circuit 204.

Then, two steps 304 (calculating failure rate) and 303 (failure when power mode changes? either only one of them is performed, or one after the other, to estimate whether the fault is transient or permanent.

At step 303, if a fault is detected when the power mode of the circuit 100 has changed (e.g., when transitioning from an active mode to a very low power mode), the fault may be considered instantaneous. In this case, branch "Y" is followed towards step 308 (disabling the clock detector). In the opposite case (branch "N"), either step 316 (disable clock detector) or 326 (reset the entire system) is implemented, or step 304 may be performed (this case is not shown in fig. 3).

During step 304, the error rate is determined, for example, by analyzing the number of times signal ClkFail has been switched to 1 according to the time of clock circuit module 230. The time provided by the clock circuit module 230 is used to determine the failure rate per unit of time, for example, by determining the relative time between two failures. Since the clock of the circuit module 230 stops when a fault is detected, the relative time is counted, for example, by a time counter or another reference clock different from the reference clock of the clock circuit module 230.

After step 304, at step 306 (the ratio is below the threshold), the error rate determined at step 304 is compared to a predetermined threshold. If the error rate is below the threshold (branch "yes"), then step 308 is implemented. If not, then steps 316 or 326 are implemented.

Step 308 includes disabling detection circuit 204, e.g., by changing the state of bit(s) ClkDetEn, and by switching it to 0 (if it is at 1, otherwise the opposite), for example. Signal ClkFail is then reset to its default value at 0.

Step 310 (re-arm) is then performed, wherein only signal ClkReArm is modified (set to 1 by the rising edge), and signal resetn remains at 1. The input 210a of the flip-flop 210 is then set to 0. The output 210d is 1. Input 224a of control element 224 switches to 1, which restarts control element 224. The signal SrcEn at output 224c switches to 1 and oscillator 202 is re-enabled.

Next, step 312 is performed (oscillator ready. In this step, the reference signal OscClk, which is again generated and presented at the input 224b of the control element 224, is verified by the control element 224 over a large number of cycles (e.g., 4096 cycles). If the oscillator has stabilized and no error is detected, the signal Ready is set to a state indicating that the reference frequency generator 202 is Ready (branch "yes"). The reference clock signal ClkOut is then available on output 250. Step 314 (enabling the clock detector) is next implemented.

During step 314, the detection circuit 204 is re-enabled, such as by a state switch to a high state or to a bit ClkDetEn in pulse form.

The next step 315 (end process) corresponds to the end of the process.

At step 312, in the event that the signal Ready on output 260 is not detected or is not detected within a given time (timeout), reference frequency generator 202 is deemed not Ready (branch "no"), then one of steps 316 (disable clock detector) or 326 (reset the entire system) is implemented.

When following the no branch of steps 306 and 312, one of steps 316 or 326 may be implemented.

Step 316 includes disabling detection circuit 204, e.g., similar to step 308.

Step 318 is then performed (less accurate backup clock is selected for temporary use). At step 318, an alternate clock signal is selected for use in other subsequent processes in subsequent step 340 (the next process step). The alternative clock signal originates, for example, from an internal backup low frequency oscillator, which enables compensation of faults in the reference frequency generator during a limited time.

Step 340 (the next process step) includes other processes to be performed. These other procedures are, for example, readjusting the time of the circuit module 230, or protecting the secret of the circuit if it is estimated that the fault may be an attack, or otherwise requesting power up by sending bit "resetn", and if the oscillator is not restarted, then the secret (such as an encryption key) may be erased.

Step 326 includes resetting the various functional circuit blocks entirely by modifying bit resetn (e.g., by setting it to 0), and then restarting and resetting them at step 328 (re-initializing the overall system). During step 328, the security key may have to be copied from memory into the security register.

At a subsequent step 330 (re-enabling the oscillator), the reference frequency generator 202 is restarted by modifying bits SrcEn and OscEn, with bit OscEn returning to 0, which corresponds to the oscillator being turned off.

Then, step 332 (oscillator ready) similar to step 312 is performed after step 330. At this step, if the signal Ready is set to a state indicating that the reference frequency generator 202 is Ready (branch "yes"), then step 334 is implemented (clock detector enabled). At step 334, the detection circuit 204 is re-enabled, for example, by a state switch to a high state or to the pulsed bit ClkDetEn.

Otherwise, the reference frequency generator 202 is deemed not ready (branch "no") and step 340 is implemented.

Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined and that other variations will occur to those skilled in the art.

Finally, based on the functional indications given above, the actual implementation of the described examples and variants is within the competence of a person skilled in the art. In particular, with respect to input 224a of control element 224, if logic circuit module 222 is a NAND logic circuit module, that input may be enabled by a signal at a 1 or high level.

In another example, if logic circuit module 214 does not include an inverter at the input, then signal ClkReArm may be selected to be set to 0 when a restart of circuit module 106 is required.

Claims (17)

1. An electronic circuit comprising: a reference clock signal generator circuit including a reference frequency generator and a detection circuit configured to detect a fault on a signal originating from the reference frequency generator; Functional circuits; and A control circuit is configured to generate a first reset signal in response to a fault detected on a signal originating from a reference frequency generator, the first reset signal causing a reset of the reference frequency generator, wherein the first reset signal is different from a second reset signal used to cause a common reset of the functional circuit and the reference clock signal generator circuit. 2. The circuit according to claim 1, further comprising: a trigger clocked by a signal derived from a fault detected on a signal originating from a reference frequency generator; a first logic circuit configured to logically combine a first reset signal and a second reset signal; the flip-flop having a reset input coupled to the output of the first flip-flop; a second logic circuit configured to logically combine the output of the flip-flop with the second reset signal to generate a clock state signal; and The enable control circuit is configured to control the enablement of the reference frequency generator in response to the clock state signal. 3. The circuit of claim 1, wherein the detection circuit is configured to detect whether the signal originating from the reference frequency generator exhibits a fault, and to generate a fault status signal at the output of the detection circuit in dependence on a result of the detection. 4. The circuit of claim 3, wherein the reference clock signal generator circuit further comprises a flip-flop, the flip-flop having: a clock input coupled to the output of the detection circuit; and A reset input is coupled to the first logic block, the first logic block being configured to perform a logical AND of the inverse of the first reset signal and the second reset signal. 5. The circuit of claim 4 , wherein the reference clock signal generator circuit further comprises a control circuit having a reset input coupled to a second logic block, the second logic block being configured to perform a logical AND of a signal present at the inverting output of the flip-flop and the second reset signal. 6. The circuit of claim 5, wherein the inverting output of the flip-flop is configured to be reset when the reset input is enabled. 7. The circuit of claim 5, wherein the reset input of the flip-flop is enabled when it receives a signal at logic 0. 8. The circuit of claim 5, wherein the control circuit comprises an oscillator output configured to transmit a signal for controlling a reference frequency generator. 9. The circuit of claim 8, wherein the signal for controlling the reference frequency generator is configured to stop the reference frequency generator when a reset input of the control circuit is enabled. 10. The circuit of claim 5, wherein the control circuit comprises: a clock output configured to transmit a reference clock signal having a reference frequency; and a clock input configured to receive said signal originating from a reference frequency generator; Wherein the control circuit is configured to transmit a reference clock signal at the clock output based on said signal originating from the reference frequency generator after a given number of cycles have been verified. 11. The circuit of claim 4, wherein the flip-flop is coupled to the output of the detection circuit via a third logic block, the third logic block being configured to perform a logical AND of the fault status signal and a signal for enabling the detection circuit. 12. The circuit of claim 4, wherein the flip-flop includes a data input that is set to a logic 1 state. 13. The circuit of claim 4, wherein the flip-flop is a D-type flip-flop. 14. A circuit comprising: an oscillator circuit having an enable input and a clock output; a detection circuit coupled to the clock output and configured to detect a failure of the oscillator circuit; a flip-flop circuit having a clock input coupled to receive the clock failure signal output by the detection circuit; a first logic circuit configured to logically combine a first reset signal indicating a reset of the circuit module and a second reset signal indicating a reset of only the reference frequency generator; wherein a reset input of the flip-flop is coupled to an output of the first logic circuit; a second logic circuit configured to logically combine the output of the flip-flop with the second reset signal to generate a clock state signal; and A control circuit is configured to receive the clock state signal and to control a logic state of an enable signal applied to an enable input of the oscillator circuit. 15. The circuit of claim 14 , wherein the detection circuit further comprises an enable input configured to receive a detector enable signal, and further comprises a third logic circuit configured to logically combine the detector enable signal and a clock failure signal output by the detection circuit to generate a signal applied to a clock input of the flip-flop. 16. The circuit of claim 14, further comprising a fourth logic circuit configured to logically combine the oscillator enable signal and the oscillator control signal generated by the control circuit to generate an enable signal applied to an enable input of the oscillator circuit. 17. The circuit according to claim 14, wherein the oscillator circuit, the detection circuit, the trigger circuit, the first logic circuit, the second logic circuit and the control circuit are circuit components of a reference clock signal generator circuit module, the circuit further includes one or more functional circuit modules, wherein each functional circuit module is reset in response to the first reset signal, and wherein the reference clock signal generator circuit module and the one or more functional circuit modules are coupled via a circuit bus.