CN119210403A

CN119210403A - Signal transmission system and signal transmission method

Info

Publication number: CN119210403A
Application number: CN202310766963.1A
Authority: CN
Inventors: 何俊达
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2023-06-27
Filing date: 2023-06-27
Publication date: 2024-12-27

Abstract

The present application relates to a signal transmission system and a signal transmission method. The signal transmission system comprises a first transmission circuit, a second transmission circuit and a multi-phase clock signal generation circuit, wherein the first transmission circuit is operated on a first working clock signal with a first phase, the second transmission circuit is operated on a second working clock signal with a second phase, the first phase is different from the second phase, and the multi-phase clock signal generation circuit is coupled with the first transmission circuit and the second transmission circuit and is used for generating the first working clock signal and the second working clock signal.

Description

Signal transmission system and signal transmission method

Technical Field

The present invention relates to a signal transmission system and a signal transmission method, and more particularly, to a signal transmission system and a signal transmission method capable of reducing power ripple (power ripple).

Background

The prior signal transmission system comprises a plurality of transmission circuits, and each transmission circuit receives an operating clock signal and operates according to the operating clock signal. These working clock signals have the same phase and therefore will be logically level shifted at the same time, i.e. with rising or falling edges occurring simultaneously. However, such a mechanism may cause a power ripple (power ripple) in the power signal of the entire system, which may affect the operation of the entire signal transmission system or generate signal noise.

Disclosure of Invention

An objective of the present invention is to provide a signal transmission system capable of reducing power ripple.

The embodiment of the invention discloses a signal transmission system, which comprises a first transmission circuit, a second transmission circuit and a multi-phase clock signal generation circuit, wherein the first transmission circuit is operated on a first working clock signal with a first phase, the second transmission circuit is operated on a second working clock signal with a second phase, the first phase is different from the second phase, and the multi-phase clock signal generation circuit is coupled with the first transmission circuit and the second transmission circuit and is used for generating the first working clock signal and the second working clock signal.

The embodiment of the invention discloses a signal transmission system, which comprises a plurality of transmission circuits and a multi-phase clock signal generation circuit, wherein the plurality of transmission circuits respectively receive one of a plurality of working clock signals, the working clock signals have different phases, and the multi-phase clock signal generation circuit is coupled with the transmission circuits and is used for generating the working clock signals. In one embodiment, the number of transfer circuits is greater than 2.

According to the above embodiments, different transmission circuits can operate according to the working clock signals with different phases, so that the working clock signals cannot be converted into logic levels at the same time, and the problem of power supply ripple in the prior art can be improved.

Drawings

Fig. 1 shows a block diagram of a signal transfer system according to an embodiment of the invention.

Fig. 2 shows a schematic diagram of an operating clock signal used by the signal transfer system shown in fig. 1.

Fig. 3, 4 and 5 show block diagrams of signal transmission systems according to various embodiments of the invention.

FIG. 6 is an exemplary circuit of the PRBS (pseudorandom binary sequence, pseudo-random number binary sequence) generator shown in FIG. 5.

Fig. 7 shows a flow chart of a signaling method according to an embodiment of the invention.

Symbol description

100 Signal transmission system

101 Multiphase clock signal generating circuit

301PLL circuit

PI_1 first phase interpolation circuit

PI_2 second phase interpolation circuit

TC_1 first transmission circuit

TC_2 second transmission circuit

TC_1a' TC_2a TC_ka transmission circuit

501. Random clock signal generating circuit

600. Linear feedback shift register

601 XOR logic gate

Detailed Description

The following description of the present invention will be made in terms of various embodiments, and it should be noted that the "first", "second" and the like in the following description are used to define only different elements, parameters, data, signals or steps. And are not intended to limit the order in which they are presented. For example, the first device and the second device may be the same structure but different devices.

Fig. 1 shows a block diagram of a signal transfer system according to an embodiment of the invention. As shown in fig. 1, the signal transmission system 100 includes a multi-phase clock signal generating circuit 101, a first transmission circuit tc_1 and a second transmission circuit tc_2. The first transfer circuit tc_1 operates on a first operating clock signal clk_1 having a first phase. The second transfer circuit tc_2 operates on a second operating clock signal clk_2 having a second phase, wherein the first phase is different from the second phase. In one embodiment, the first transfer circuit tc_1 samples data according to a rising edge or a falling edge of the first operation clock signal clk_1, and the second transfer circuit tc_2 samples data according to a rising edge or a falling edge of the second operation clock signal clk_2.

The multi-phase clock signal generating circuit 101 is coupled to the first transmission circuit tc_1 and the second transmission circuit tc_2 for generating a first working clock signal clk_1 and a second working clock signal clk_2. In one embodiment, the first transmission circuit tc_1 and the second transmission circuit tc_2 are transmission circuits on different channels (channels) or different lanes (lanes). In addition, in one embodiment, the first working clock signal clk_1 and the second working clock signal clk_2 are respectively received by drivers (drivers) in the first transmission circuit tc_1 and the second transmission circuit tc_2, and the drivers respectively operate on the first working clock signal clk_1 and the second working clock signal clk_2, that is, respectively correspond to rising edges, falling edges or logic levels of the first working clock signal clk_1 and the second working clock signal clk_2.

Fig. 2 shows a schematic diagram of an operating clock signal used by the signal transfer system shown in fig. 1. As shown in fig. 2, the first and second operating clock signals clk_1 and clk_2 have different phases. In one embodiment, the first and second operating clock signals clk_1 and clk_2 have the same clock frequency and duty cycle, but different phases. By doing so, the rising edge and the falling edge of the first working clock signal clk_1 and the second working clock signal clk_2 can not occur simultaneously, so that the problem of power supply ripple in the prior art can be improved.

In the embodiment of fig. 1, two transmission circuits are illustrated. The signal transmission system of the present invention may comprise more than two transmission circuits. For example, in one embodiment, the signal transmission system provided by the present invention includes M transmission circuits (M > 2). In such an embodiment, the M operating clock signals used by the M transmit circuits all have different phases. As shown in fig. 2, M working clock signals clk_1, clk_2. In such an embodiment, the signal transmission system provided by the present invention may be simply shown as a signal transmission system, which includes a plurality of transmission circuits respectively receiving one of a plurality of working clock signals, the working clock signals having different phases, and a multi-phase clock signal generating circuit coupled to the transmission circuits for generating the working clock signals. It should be noted that the signal transmission system provided by the present invention is not limited to all the working clock signals used by the transmission circuits having different phases, but may also have different phases for some of the working clock signals used by the transmission circuits, but have the same phase for some of the working clock signals used by the transmission circuits. Such architecture may also be employed in other embodiments below.

The multiphase clock signal generation circuit 101 shown in fig. 1 can be implemented by various circuits. Fig. 3, 4 and 5 show block diagrams of signal transmission systems according to various embodiments of the invention. In the embodiment of fig. 3, the multiphase clock signal generation circuit 101 is a PLL (Phase-locked loop) circuit 301. As shown in fig. 3, the multi-phase clock signal generating circuit 101 is configured to generate a plurality of clock signals PH0, PH 1..ph (N-1) having different phases, and then take two of the clock signals PH0, PH 1..ph (N-1) as the working clock signals clk_1, clk_2.

In the embodiment of fig. 4, the multi-phase clock signal generating circuit 101 includes a PLL circuit 301, a first phase interpolation circuit pi_1, and a second phase interpolation circuit pi_2. In such an embodiment, the clock signals PH0, PH 1..ph (N-1) generated by the PLL circuit 301 are candidate clock signals. The first phase interpolation circuit pi_1 generates a first working clock signal clk_1 according to at least one first candidate clock signal of the candidate clock signals, and the second phase interpolation circuit pi_2 generates a second working clock signal clk_2 according to at least one second candidate clock signal of the candidate clock signals. The first phase interpolation circuit pi_1 and the second phase interpolation circuit pi_2 may be circuits of various forms. In an embodiment, the first phase interpolation circuit pi_1 and the second phase interpolation circuit pi_2 have adjustable current sources, and the adjustable current sources can be adjusted to determine phases of the working clock signals output by the first phase interpolation circuit pi_1 and the second phase interpolation circuit pi_2. Other detailed structures of the phase interpolation circuit are disclosed in the prior art, for example, the phase interpolation circuit is described in detail in US patent No. US8564352, and thus are not described herein.

In the embodiment of fig. 5, the multi-phase clock signal generating circuit 101 includes a random clock signal generating circuit 501 for generating a random clock signal, i.e., generating a plurality of random clock signals having different phases. In one embodiment, the random clock signal generation circuit 501 is a PRBS (pseudorandom binary sequence ) generator. The PRBS generator is configured to randomly generate 0 or 1 within a numerical cycle.

Fig. 6 is an exemplary circuit of the PRBS generator shown in fig. 5. In the embodiment of fig. 6, the random clock signal generation circuit 501 is a Linear feedback shift register 600 (LFSR), which can be used as a PRBS generator. As shown in fig. 6, the linear feedback shift register 600 includes registers l_1, l_2, l_3, l_4, l_5, l_6, and l_7, which correspond to the equation x7+x6+1=0. The linear feedback shift register 600 takes as input a linear function of the output, i.e., the output is processed by the XOR logic gate 601 and then shifts the number of bits in registers l_1, l_2, l_3, l_4, l_5, l_6, and l_7. The initial values in registers L_1, L_2, L_3, L_4, L_5, L_6, and L_7 are referred to as "seeds". Taking fig. 6 as an example, the seed is 0000001. The detailed operation of the linear feedback shift register 600 is well known to those skilled in the art, and will not be described herein. It is also noted that the PRBS generator may contain other structures than the example shown in fig. 6. In addition, the multi-phase clock signal generating circuit 101 may be other circuits that generate clock signals having different phases, in addition to the above embodiments. For example, the multi-phase clock signal generation circuit 101 may be a delay line (DELAY CHAIN) circuit.

Referring to fig. 5, after the random clock signal generating circuit 501 generates a plurality of clock signals with different phases, the clock signals can be directly used as the working clock signals operated by different transmission circuits. In one embodiment, after one of the clock signals generated by the random clock signal generating circuit 501 is selected, the working clock signals operated by different transmission circuits are generated according to the selected clock signal. Taking fig. 5 as an example, the random clock signal generating circuit 501 generates N clock signals, and then selects the clock signal with phase j therein to generate the working clock signals operated by different transmission circuits. In the embodiment of fig. 5, however, there are K transmission circuits tc_1a, tc_2a..tc_ka, and these transmission circuits have phases j, j+1, j+2..phase j+k, respectively. The adjacent phases have a predetermined phase difference, respectively. For example, phase j and phase j+1 have a predetermined phase difference, and phase j+k-1 and phase j+k also have a predetermined phase difference.

According to the foregoing embodiment, a signal transmission method can be obtained. Fig. 7 shows a flow chart of a signaling method according to an embodiment of the invention, which is used in a signaling system and comprises the following steps:

Step 701

A first operating clock signal (e.g., the first operating clock signal clk_1 shown in fig. 2) having a first phase is generated.

Step 703

A second operating clock signal (e.g., the second operating clock signal clk_2 shown in fig. 2) having a second phase is generated.

Wherein the first phase is different from the second phase.

Step 705

A first transfer circuit (e.g., the first transfer circuit TC_1 shown in FIG. 1) in the signal transfer system is operated on the first operation clock signal.

Step 707

A second transfer circuit (e.g., the second transfer circuit TC_2 shown in FIG. 1) in the signal transfer system is operated on the second operation clock signal.

The foregoing description is only of the preferred embodiments of the present invention, and all equivalent changes and modifications made in the claims should be construed to fall within the scope of the present invention.

Claims

1. A signal transmission system, comprising:

A first transmission circuit operates on a first working clock signal with a first phase:

a second transmitting circuit operating on a second working clock signal having a second phase, wherein the first phase is different from the second phase; and

A multi-phase clock signal generating circuit is coupled to the first transmitting circuit and the second transmitting circuit, and is used for generating the first working clock signal and the second working clock signal.

2 . The signal transmission system as claimed in claim 1 , wherein the first transmission circuit and the second transmission circuit are transmission circuits of different channels or paths.

3. The signal transmission system as claimed in claim 1, wherein the drivers in the first transmission circuit and the second transmission circuit receive the first working clock signal and the second working clock signal respectively, and operate on the first working clock signal and the second working clock signal respectively.

4. The signal transmission system as claimed in claim 1, wherein the multi-phase clock signal generating circuit is a phase-locked loop circuit.

5. The signal transmission system as claimed in claim 1, wherein the multi-phase clock signal generating circuit comprises:

a phase-locked loop circuit for generating a plurality of candidate clock signals, wherein the plurality of candidate clock signals have different phases;

a first phase interpolation circuit, coupled to the phase-locked loop circuit and the first transmission circuit, for generating the first working clock signal according to at least one first candidate clock signal among the plurality of candidate clock signals;

A second phase interpolation circuit is coupled to the phase-locked loop circuit and the second transmission circuit, and is used to generate the second working clock signal according to at least one second candidate clock signal among the plurality of candidate clock signals.

6 . The signal transmission system as claimed in claim 1 , wherein the multi-phase clock signal generating circuit comprises a random clock signal generating circuit.

7. The signal transmission system as claimed in claim 6, wherein the random clock signal generating circuit is a pseudo-random binary number sequence generator.

8. The signal transmission system as claimed in claim 1, wherein the multi-phase clock signal generating circuit is a delay line circuit.

9. A signal transmission system, comprising:

A plurality of transmission circuits, each receiving one of a plurality of working clock signals, wherein the plurality of working clock signals have different phases; and

A multi-phase clock signal generating circuit is coupled to the plurality of transmitting circuits to generate the plurality of working clock signals.

10. The signal transmission system of claim 9, wherein the number of the plurality of transmission circuits is greater than 2.