CN119254163B

CN119254163B - A rail-to-rail input bias circuit

Info

Publication number: CN119254163B
Application number: CN202411303446.1A
Authority: CN
Inventors: 富浩宇; 高晨
Original assignee: Beijing Shimao Microelectronics Co ltd
Current assignee: Beijing Shimao Microelectronics Co ltd
Priority date: 2024-09-18
Filing date: 2024-09-18
Publication date: 2025-05-16
Anticipated expiration: 2044-09-18
Also published as: CN119254163A

Abstract

The present application relates to a rail-to-rail input bias circuit, which is used to provide a bias voltage for the input stage of a rail-to-rail input operational amplifier; the circuit includes a detection module and a bias module; the detection module is used to generate a selection control signal according to a differential input amplitude and output it to the bias module; the differential input amplitude is the voltage difference between an external input signal and an output signal of the rail-to-rail input operational amplifier; the bias module is used to control the input of an external input signal or a common-mode input signal in response to the selection control signal and transmit the generated bias voltage to the input stage of the rail-to-rail input operational amplifier; wherein, when the differential input amplitude is greater than a detection threshold, the bias module inputs a common-mode input signal; when the differential input amplitude is less than or equal to the detection threshold, the bias module inputs an external input signal; the rail-to-rail input bias circuit of the present application can avoid the influence of the offset ripple at the output end on the bias current, and improve the common-mode rejection ratio of the rail-to-rail input operational amplifier.

Description

Rail-to-rail input bias circuit

Technical Field

The application relates to the field of circuit design, in particular to a rail-to-rail input bias circuit.

Background

Rail-to-Rail input operational amplifiers (Rail-to-Rail Input Operational Amplifier) employ a Rail-to-Rail input stage constructed of Complementary differential input pair tubes (completions DIFFERENTIAL PAIR) whose input voltage range can cover both positive and negative supply voltages, allowing a wider input signal range. The rail-to-rail input operational amplifier can dynamically adjust the bias current of the complementary differential input pair tube according to the common-mode input signal through the rail-to-rail input bias circuit so as to maintain the transconductance of the operational amplifier constant. In practice, the operational amplifier has output offset, and the output offset can be reduced by using a chopping (chopping) technology, but offset ripple generated at the output end of the rail-to-rail input operational amplifier can influence a traditional input bias circuit when using chopping technology, so that the absolute value of offset voltage changes along with the working phase of chopping, and the output offset can not be thoroughly counteracted.

Disclosure of Invention

In view of this, the present application provides a rail-to-rail input bias circuit, which can avoid the influence of offset ripple generated at the output end on the rail-to-rail input bias circuit when chopping technology is used, and improve the common mode rejection ratio of the rail-to-rail input operational amplifier.

According to one aspect of the application, a rail-to-rail input bias circuit is provided and is used for providing bias voltage for an input stage of a rail-to-rail input operational amplifier, the rail-to-rail input bias circuit comprises a detection module and a bias module, the detection module is used for generating a selection control signal according to a differential input amplitude and outputting the selection control signal to the bias module, the differential input amplitude is a voltage difference value between an external input signal and an output signal of the rail-to-rail input operational amplifier, the bias module is used for responding to the selection control signal to control the input of the external input signal or a common-mode input signal and transmitting the bias voltage generated according to the input external input signal or the common-mode input signal to the input stage of the rail-to-rail input operational amplifier, the common-mode input signal is the sum of the external input signal and the output signal divided by 2, and the bias module is used for responding to the selection control signal to input the common-mode input signal when the differential input amplitude is larger than a detection threshold value, and the bias module responds to the selection control signal to the external input signal when the differential input amplitude is smaller than or equal to the detection threshold.

In one possible implementation manner, the bias module includes a multiplexer, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; the control end of the multiplexer inputs the selection control signal, the first input end of the multiplexer inputs the common-mode input signal, the second input end of the multiplexer inputs the external input signal, the output end of the multiplexer is connected with the grid electrode of the second NMOS tube, the multiplexer responds to the received selection control signal to control the common-mode input signal of the first input end of the multiplexer or the external input signal of the second input end to input the grid electrode of the second NMOS tube through the output end, the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the drain electrode of the third NMOS tube are connected, the drain electrode of the first NMOS tube, the drain electrode of the first PMOS tube and the grid electrode of the first PMOS tube are connected, the drain electrode of the second NMOS tube, the drain electrode of the second PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected, the drain electrode of the third NMOS tube, the drain electrode of the fourth NMOS tube and the grid electrode of the fourth PMOS tube are connected, the first voltage of the third NMOS tube is connected with the grid electrode of the first PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are connected with positive power supply voltage of the rail-to-rail input operational amplifier, the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are connected with negative power supply voltage of the rail-to-rail input operational amplifier, and the grid electrode of the first PMOS tube and the grid electrode of the fourth NMOS tube are used for outputting the bias voltage.

In one possible implementation manner, the detection module comprises a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a sixth PMOS tube, a seventh PMOS tube, a ninth PMOS tube and an OR gate, wherein the grid electrode of the tenth NMOS tube is input with the external input signal, the grid electrode of the eleventh NMOS tube is input with the output signal, the source electrode of the tenth NMOS tube, the source electrode of the eleventh NMOS tube and the drain electrode of the seventh NMOS tube are connected, the drain electrode of the tenth NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the eighth PMOS tube are connected, the drain electrode of the eleventh NMOS tube, the grid electrode of the seventh PMOS tube and the grid electrode of the ninth PMOS tube are connected, the grid electrode of the seventh NMOS tube, the grid electrode of the eighth NMOS tube and the grid electrode of the ninth NMOS tube are connected with a second voltage in parallel, the drain electrode of the eighth NMOS tube, the drain electrode of the eighth PMOS tube, the grid electrode of the eighth PMOS tube and the gate of the eighth PMOS tube are connected with the grid electrode of the eighth PMOS tube, the grid electrode of the eighth NMOS tube and the gate of the ninth PMOS tube are connected with the output voltage of the eighth PMOS tube, the gate of the eighth PMOS tube, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the eighth PMOS tube, the drain electrode of the eighth PMOS tube is connected with the gate of the gate tube, the gate of the eighth PMOS tube is connected with the gate.

In one possible implementation manner, the input stage of the rail-to-rail input operational amplifier comprises a first input NMOS tube, a second input NMOS tube, a first input PMOS tube, a second input PMOS tube, a fifth NMOS tube and a fourth PMOS tube, wherein the grid electrode of the first input NMOS tube is connected with the grid electrode of the first input PMOS tube to form the positive input end of the rail-to-rail input operational amplifier, the grid electrode of the second input NMOS tube is connected with the grid electrode of the second input PMOS tube to form the negative input end of the rail-to-rail input operational amplifier, the source electrode of the first input NMOS tube, the source electrode of the second input NMOS tube and the drain electrode of the fifth NMOS tube are connected, the grid electrode of the first input PMOS tube, the source electrode of the second input PMOS tube and the drain electrode of the fourth PMOS tube are connected with the grid electrode of the fourth NMOS tube to receive the bias voltage, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the first PMOS tube to form the negative input end of the rail-to-rail input operational amplifier, and the source electrode of the fourth input NMOS tube is connected with the positive input voltage of the rail-to the rail amplifier.

In one possible implementation manner, the output end of the rail-to-rail input operational amplifier is connected with the positive input end or the negative input end of the rail-to-rail input operational amplifier, wherein when the output end of the rail-to-rail input operational amplifier is connected with the negative input end of the rail-to-rail input operational amplifier, the positive input end of the rail-to-rail input operational amplifier inputs the external input signal, and when the output end of the rail-to-rail input operational amplifier is connected with the positive input end of the rail-to-rail input operational amplifier, the negative input end of the rail-to-rail input operational amplifier inputs the external input signal.

In one possible implementation manner, the selection control signal is at a high level when the differential input amplitude is greater than the detection threshold, the multiplexer is responsive to the selection control signal to input the common-mode input signal to the gate of the second NMOS, and is at a low level when the differential input amplitude is less than or equal to the detection threshold, and the multiplexer is responsive to the selection control signal to input the external input signal to the gate of the second NMOS.

In one possible implementation manner, the detection threshold is adjusted and set according to at least one of the width-to-length ratio of the seventh NMOS transistor, the width-to-length ratio of the eighth NMOS transistor, the width-to-length ratio of the ninth NMOS transistor, the width-to-length ratio of the sixth PMOS transistor, the width-to-length ratio of the seventh PMOS transistor, the width-to-length ratio of the eighth PMOS transistor, or the width-to-length ratio of the ninth PMOS transistor.

The detection module of the rail-to-rail input offset circuit can automatically detect the differential input amplitude of the rail-to-rail input operational amplifier and generate the selection control signal, when the differential input amplitude exceeds the detection threshold value, the offset module can respond to the selection control signal to provide offset voltage and offset current according to common-mode input signals of the rail-to-rail input operational amplifier, so that input transconductance change can be avoided, the rail-to-rail input operational amplifier has the rail-to-rail input range when responding to large-amplitude transient input, when the differential input amplitude is not greater than the detection threshold value, the offset module can respond to the selection control signal to provide offset voltage and offset current according to external input signals of the rail-to-rail input operational amplifier, offset current and output signals are decoupled, and offset current change caused by offset ripple waves generated at an output end when a chopping technology is used can be avoided, output offset ripple caused by common-mode input signals does not change, and the common-mode rejection ratio can be remarkably improved.

Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the application and together with the description, serve to explain the principles of the application.

Fig. 1 shows a schematic diagram of a switched capacitor circuit driven using an operational amplifier.

Fig. 2 shows a schematic circuit configuration of a non-rail-to-rail input operational amplifier.

Fig. 3 is a schematic diagram showing a circuit configuration of a rail-to-rail input operational amplifier and a conventional rail-to-rail input bias circuit.

Fig. 4 shows a schematic diagram of a rail-to-rail input bias circuit according to an embodiment of the application.

Fig. 5 shows a schematic circuit diagram of a bias module of a rail-to-rail input bias circuit and a schematic circuit diagram of a rail-to-rail input operational amplifier according to an embodiment of the present application.

Fig. 6 is a schematic circuit diagram of a detection module of a rail-to-rail input bias circuit according to an embodiment of the present application.

Detailed Description

Various exemplary embodiments, features and aspects of the application will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following description in order to provide a better illustration of the application. It will be understood by those skilled in the art that the present application may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present application.

The input signal is a low-frequency continuous time signal, and the output is used for driving a discrete-time switched capacitor circuit, so that the input signal is a typical application scene of an operational amplifier. When the operational amplifier loads the switched capacitor circuit, the switched capacitor circuit capacitance at the output end of the operational amplifier is switched, a transient pull-down signal or a transient overshoot signal is caused at the output end of the operational amplifier, and the transient signal at the output end controls the input of the operational amplifier through a feedback loop to provide a transient charging and discharging path for the switched capacitor circuit. Fig. 1 shows a schematic diagram of a switched capacitor circuit driven by an operational amplifier, wherein the input signal at the positive input end of the operational amplifier is a low frequency signal, and the output end is connected with the negative input end through a feedback network as shown in fig. 1. When the switch PH1 is turned on and PH2 is turned off, the output end of the operational amplifier is connected with the input end of the switch capacitor circuit, and if the voltage of the left electrode plate of the capacitor in the switch capacitor circuit is lower than the voltage of the output end of the operational amplifier, the voltage of the output end of the operational amplifier is pulled down, and the output end of the operational amplifier generates a transient pull-down signal. The transient pull-down signal at the output end of the operational amplifier is fed back to the negative input end of the operational amplifier through a feedback network, so that the negative input end of the operational amplifier also generates the transient pull-down signal. The operational amplifier can charge the capacitor until the voltage of the left electrode plate of the capacitor is the same as the voltage of the output end of the operational amplifier. After a certain setup time, the differential input voltage of the operational amplifier is set up to be about 0, that is, the voltage of the signal VINP at the positive input end is approximately equal to the voltage of the signal VINN at the negative input end, and the voltage of the output end is set up to be about a steady state value. Since the frequency of the external input signal VIN is low and almost unchanged, the steady-state value of the voltage at the output end of the operational amplifier is consistent with the initial voltage value before the transient pull-down signal comes.

The non-rail-to-rail input operational amplifier refers to an operational amplifier in which the input voltage range cannot fully reach the positive and negative voltages of the power supply. Conventional non-rail-to-rail input operational amplifiers use either a differential input pair of PMOS transistors or a differential input pair of NMOS transistors to input differential signals. Fig. 2 shows a schematic circuit diagram of a non-rail-to-rail input operational amplifier, as shown in fig. 2, in which an NMOS differential input pair transistor is used as an input stage, a low-frequency signal VIN is input at a positive input terminal, and an output terminal is connected with a negative input terminal to form a feedback loop. If the feedback coefficient is large, for example, the feedback coefficient is 1, the signal VO at the output end is fed back to the negative input end, when the load switch capacitor circuit of the non-rail-to-rail input operational amplifier is switched, if the amplitude of the transient pull-down signal or the transient overshoot signal generated at the output end is large when the capacitor is switched, although the low-frequency signal VIN input by the non-feedback end (i.e. the positive input end) is almost unchanged, the large transient signal jump at the feedback input end (i.e. the negative input end) will cause significant change of the common-mode input signal, wherein the common-mode input signal vcm= (vinp+vinn)/2, VINP is the input signal at the positive input end, and VINN is the input signal at the negative input end. The common-mode input range of the non-rail-to-rail input operational amplifier is limited, the drain-source voltage of the bias current tube MN1 of the differential input pair tube changes along with the common-mode input signal, and the output impedance of the bias current tube MN1 is limited, for the NMOS differential input pair tube in fig. 2, when the common-mode input signal greatly jumps downwards, the bias current ITAILN provided by the bias current tube MN1 is reduced, when the drain-source voltage of MN1 is compressed to be smaller than the overdrive voltage, MN1 enters a linear region, and the bias current is more attenuated, which means that the input transconductance is greatly attenuated. The input transconductance represents the rate of change of the output current when the input signal voltage of the operational amplifier changes, and can reflect the amplification performance of the amplifier. The large attenuation of the input transconductance will cause the bandwidth and gain of the operational amplifier to drop significantly, and the process of setting up the operational amplifier to steady state will be slowed down significantly.

Therefore, a rail-to-rail input stage consisting of complementary differential input pair transistors is generally employed in CMOS-based operational amplifiers, the rail-to-rail input stage having a rail-to-rail common mode input range, and the input swing of the negative power rail to the positive power rail can be realized. Such an operational amplifier whose input voltage range can approach or reach the positive and negative voltages of the power supply is referred to as a rail-to-rail input operational amplifier. Fig. 3 is a schematic circuit diagram of a rail-to-rail input operational amplifier and a conventional rail-to-rail input bias circuit for providing a bias voltage and a bias current to an input stage of the rail-to-rail input operational amplifier. As shown in fig. 3, the input stage of the rail-to-rail input operational amplifier is implemented by a complementary differential input pair of NMOS differential input pair transistors and a PMOS differential input pair transistor. The rail-to-rail input operational amplifier has the input voltage of the positive input end of the VINP, the input voltage of the negative input end of the VINN, the NMOS differential input pair tube is conducted when the common-mode input voltage approaches to the positive power rail VDD, the input transconductance is completely provided by the bias current ITAILN of the NMOS differential input pair tube, the bias current ITAILP =0 of the PMOS differential input pair tube, the PMOS differential input pair tube is conducted when the common-mode input voltage approaches to the negative power rail VSS, the input transconductance is completely provided by the bias current ITAILP of the PMOS differential input pair tube, and the bias current ITAILN =0 of the NMOS differential input pair tube, so that at least one differential input pair tube is conducted in the whole rail-to-rail input range, and the input transconductance is provided. When the common-mode input voltage is located at the middle position of the power supply rail, that is, when the common-mode input voltage is close to (VDD-VSS)/2, the NMOS differential input pair transistor and the PMOS differential input pair transistor are simultaneously turned on, each NMOS differential input pair transistor and PMOS differential input pair transistor needs to provide half input transconductance, ITAILN and ITAILP are usually biased to be half of that when the NMOS differential input pair transistor or the PMOS differential input pair transistor is separately turned on (that is, the NMOS differential input pair transistor and the PMOS differential input pair transistor are in a subthreshold region) or 1/4 (that is, the NMOS differential input pair transistor and the PMOS differential input pair transistor are in a saturation region), so that the equivalent input transconductance is the same as that when the NMOS differential input pair transistor or the PMOS differential input pair transistor is separately turned on.

The rail-to-rail input operational amplifier can dynamically adjust the bias currents of the NMOS differential input pair tube and the PMOS differential input pair tube according to a common-mode input signal through a rail-to-rail input bias circuit so as to maintain the equivalent input transconductance provided by the differential input pair tube to be approximately constant. When the common-mode input signal jumps downwards, the rail-to-rail input bias circuit can adjust the bias current ITAILP of the PMOS differential input pair tube to be high and reduce the bias current ITAILN of the NMOS differential input pair tube, when the common-mode input signal jumps upwards, the rail-to-rail input bias circuit can adjust the bias current ITAILP of the PMOS differential input pair tube to be low and adjust the bias current ITAILN of the NMOS differential input pair tube to be high, and therefore the equivalent input transconductance provided by the differential input pair tube can be kept approximately constant in the whole rail-to-rail input range. Fig. 3 shows a conventional rail-to-rail input bias circuit, which is composed of a differential input pair tube formed by MN1 and MN2 and a current mirror, wherein one end of the differential input pair tube (i.e. the gate of MN 1) is input with a P/N switching threshold voltage Vr, vr is generally equal to (VDD-VSS)/2, and the other end of the differential input pair tube (i.e. the gate of MN 2) is connected with the common-mode input voltage vin_cm, vin_cm= (vinp+vinn)/2 of the rail-to-rail input operational amplifier. The rail-to-rail input bias circuit may respectively deliver the generated bias voltages (i.e., the gate voltage of MP1 and the gate voltage of MN 4) to the gate of MP4 and the gate of MN5, such that MP4 may generate the bias current ITAILP and MN5 may generate the bias current ITAILN, which may provide the bias current for the input stage of the rail-to-rail input operational amplifier. When vr=vin_cm, the bias current provided by the rail-to-rail input bias circuit is equally divided by the NMOS differential input pair and the PMOS differential input pair, i.e., ITAILN = ITAILP, at which time both the NMOS differential input pair and the PMOS differential input pair are on, when vin_cm increases beyond Vr, the bias current provided by the rail-to-rail input bias circuit flows primarily through the NMOS differential input pair, i.e., ITAILN > ITAILP, and when vin_cm approaches the positive power rail VDD, the bias current flows entirely through the NMOS differential input pair, and when vin_cm decreases below Vr, the bias current provided by the rail-to-rail input bias circuit flows primarily through the PMOS differential input pair, i.e., ITAILN < ITAILP, and when vin_cm approaches the negative power rail, the bias current flows entirely through the PMOS differential input pair.

The op-amp is typically used in a negative feedback loop, for example, the rail-to-rail input op-amp shown in fig. 3 is configured in a unity gain negative feedback mode, with one input terminal coupled to the input signal VIN and the other terminal coupled to the output signal VO at the output terminal. This means that the common mode input voltage of the operational amplifier is output dependent, i.e. the bias currents of the NMOS differential input pair and the PMOS differential input pair are output dependent.

Although the rail-to-rail input stage expands the common-mode input range, in practice, the operational amplifier has problems such as output offset and 1/f noise. To reduce output offset, op-amps typically use chopping technology. Conventional chopping technology is implemented by adding chopping switches in the op-amp, as shown in fig. 3, with chopping switches chop1 at the input of the rail-to-rail input op-amp and chopping switches chop2 and chop3 at the load. chopping is divided into two phases, one side of each chopping switch is turned on when the first phase is operated, and the other side of each chopping switch is turned on when the second phase is operated. For example, for chop1, during a first phase operation, the rail-to-rail input operational amplifier has its positive input connected to input signal VIN through chop1 and its negative input connected to the output through chop1, and during a second phase operation, its positive input connected to the output through chop1 and its negative input connected to input signal VIN through chop 1. Because the input signal VIN is switched by two stages chopping of switches, the polarity of the input signal is changed twice, the signal seen at the output terminal is not changed, and the main offset voltage only passes through one stage chopping of switches (chop 2 or chop 3), so that in an ideal case, the offset output is identical in magnitude and opposite in polarity under two phases of chopping, and the output of the operational amplifier appears as a signal periodically overlapping a positive offset output and a negative offset output after chopping, which means that the output offset voltage can be offset averagely in the time domain.

The input signal VIN of the operational amplifier is typically a direct current or a slowly varying signal. When the common-mode input voltage is located at one end of the power rail, only one differential input pair tube of the input stage of the operational amplifier is conducted, although the output end of the operational amplifier can generate offset ripple waves to cause the change of the common-mode input voltage due to chopping, because the differential input pair tube is in a single-side overdrive state, the bias current completely flows through the NMOS differential input pair tube or completely flows through the PMOS differential input pair tube, the bias current of the differential input pair tube is not influenced by the common-mode input voltage, and therefore when the common-mode input voltage is located near the power rail, the static working point of the circuit cannot be changed along chopping, namely the absolute value of the offset voltage of the operational amplifier cannot be changed along with chopping, and chopping can normally offset output offset. When the common-mode input voltage is located at the middle position of the power rail, the NMOS differential input pair tube and the PMOS differential input pair tube of the input stage of the operational amplifier are conducted, and when chopping technology is used, offset ripple waves at the output end of the operational amplifier can cause the common-mode input voltage to change, and further cause bias current of the NMOS differential input pair tube and the PMOS differential input pair tube to change. The offset currents of the NMOS differential input pair and the PMOS differential input pair change at two operating phases of chopping, the static operating point of which changes at two operating phases of chopping, and the output offset of the operational amplifier is related to the static operating point thereof, which means that the absolute value of the offset voltage of the operational amplifier is not equal at the two operating phases, and chopping leaks, i.e., the output offset cannot be completely offset in the time-averaged sense.

As described above, when the operational amplifier is turned on chopping, the output offset may be cancelled when the common-mode input voltage approaches the power rail, and when the common-mode input voltage is located at the middle position of the power rail, the output offset may not be completely cancelled, and there is a residual output offset. That is, the output offset varies significantly with the variation of the common-mode input voltage, and the ratio of the output offset to the variation of the common-mode input voltage is referred to as the common-mode rejection ratio (Common Mode Rejection Ratio, CMRR). Therefore, as shown in fig. 3, when the operational amplifier is configured in the negative feedback mode, the output offset cannot be sufficiently cancelled when the common-mode input voltage is in the middle region of the power supply rail after the operational amplifier is turned on chopping due to the fact that the output signal is coupled to perform bias current judgment, and the common-mode rejection ratio is significantly deteriorated.

In view of this, the embodiment of the application provides a rail-to-rail input bias circuit, which can avoid the influence of offset ripple generated when chopping technology is used on the bias current provided by the rail-to-rail input bias circuit and improve the common mode rejection ratio of the rail-to-rail input operational amplifier.

Fig. 4 shows a schematic diagram of a rail-to-rail input bias circuit that may be used to provide bias voltages and bias currents to an input stage of a rail-to-rail input operational amplifier, as shown in fig. 4, which may include a detection module 401 and a bias module 402, in accordance with an embodiment of the present application.

The detection module 401 is configured to generate a selection control signal according to a differential input amplitude and output the selection control signal to the bias module 402, where the differential input amplitude is a voltage difference between an external input signal and an output signal of the rail-to-rail input operational amplifier.

The bias module 402 is configured to control the input of the external input signal or the common-mode input signal in response to the selection control signal, and to transmit the bias voltage generated according to the input external input signal or the common-mode input signal to an input stage of the rail-to-rail input operational amplifier, wherein the bias current is generated according to the bias voltage, the common-mode input signal is a sum of the external input signal and the output signal divided by 2, wherein when the differential input amplitude is greater than a detection threshold, the bias module 402 inputs the common-mode input signal in response to the selection control signal, and when the differential input amplitude is less than or equal to the detection threshold, the bias module 402 inputs the external input signal in response to the selection control signal.

The detection module of the rail-to-rail input offset circuit can automatically detect the differential input amplitude of the rail-to-rail input operational amplifier and generate the selection control signal, when the differential input amplitude exceeds the detection threshold, the offset module can respond to the selection control signal to provide offset voltage and offset current according to common-mode input signals of the rail-to-rail input operational amplifier, so that input transconductance change can be avoided, the rail-to-rail input operational amplifier has an input range from rail to rail when responding to large-amplitude transient input, when the differential input amplitude is not greater than the detection threshold, the offset module can respond to the selection control signal to provide offset voltage and offset current according to external input signals of the rail-to-rail input operational amplifier, the offset current is decoupled from the output signal, and the offset current is directly offset by the external input signal, so that offset ripple generated at an output end can be prevented from causing offset current change when the chopping technology is used, output offset is not changed along with the common-mode input signals, and the common-mode rejection ratio can be remarkably improved.

Illustratively, the rail-to-rail input bias circuit of embodiments of the present application may be used to provide bias currents to the NMOS differential input pair and PMOS differential input pair of the input stage of the rail-to-rail input operational amplifier shown in fig. 3.

The rail-to-rail input operational amplifier shown in fig. 5 is identical in circuit configuration to the rail-to-rail input operational amplifier shown in fig. 3 described above. As shown in FIG. 5, the input stage of the rail-to-rail input operational amplifier may include a first input NMOS transistor MN_in1, a second input NMOS transistor MN_in2, a first input PMOS transistor MP_in1, a second input PMOS transistor MP_in2, a fifth NMOS transistor MN5, and a fourth PMOS transistor MP4, where the gate of MN_in1 and the gate of MP_in1 are connected to form the positive input terminal of the rail-to-rail input operational amplifier, the gate of MN_in2 and the gate of MP_in2 are connected to form the negative input terminal of the rail-to-rail input operational amplifier, the source of MN_in1, the source of MN_in2 and the drain of MN5 are connected, the source of MP_in1, the source of MP_in2 and the drain of MP4 are connected, the source of MP4 is connected to the positive power supply voltage of the rail-to-rail input operational amplifier, and the source of MN5 is connected to the negative power supply voltage VSS of the rail-to rail input operational amplifier. Mn_in1 and mn_in2 constitute one NMOS differential input pair tube, mp_in1 and mp_in2 constitute one PMOS differential input pair tube, and the NMOS differential input pair tube and the PMOS differential input pair tube constitute a complementary differential input pair tube.

The output of the rail-to-rail input operational amplifier may be connected to either the positive or negative input of the rail-to-rail input operational amplifier. When the rail-to-rail input operational amplifier uses chopping technology, at the first working phase of chopping, the positive input end of the rail-to-rail input operational amplifier can be input with an external input signal VIN, the output end of the rail-to-rail input operational amplifier can be connected with a negative input end, i.e. the output signal VO of the output end of the rail-to-rail input operational amplifier can be fed back to the negative input end, and at the second working phase of chopping, the negative input end of the rail-to-rail input operational amplifier can be input with the external input signal VIN, the output end of the rail-to-rail input operational amplifier can be connected with the positive input end, i.e. the output signal VO of the output end of the rail-to-rail input operational amplifier can be fed back to the positive input end. The external input signal VIN may be a low frequency continuous time signal.

The bias module of the rail-to-rail input bias circuit shown in fig. 5 may include a Multiplexer (MUX), a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, and a third PMOS transistor MP3.

As shown in fig. 5, the control terminal of the MUX inputs the selection control signal SW, the first input terminal of the MUX inputs the common mode input signal vin_cm, wherein vin_cm= (vin+vo)/2, the second input terminal of the MUX inputs the external input signal VIN, the output terminal of the MUX is connected to the gate of MN2, the MUX controls the common mode input signal vin_cm of the first input terminal or the external input signal VIN of the second input terminal to input the gate of MN2 through the output terminal in response to the received selection control signal SW, the source of MN1, the source of MN2 and the drain of MN3 are connected, the drain of MN1, the drain of MP1 and the gate of MP1 are connected, the drain of MN2, the drain of MP2 and the gate of MP3 are connected, the drain of MP3, the drain of MN4 and the gate of MN4 are connected, the gate of MN1 is connected to the P/N switching threshold voltage Vr, the Vr may be equal to (VDD-VSS)/2, the gate of MN3 is connected to the first voltage vbn_1, vbn_1 may be set by a person skilled in the art, and the source of MN1 and the source of MN3 is connected to the source of MN 3. The gate of MN4 is connected to the gate of MN5 in the rail-to-rail input operational amplifier input stage and the gate of MP1 is connected to the gate of MP4 in the rail-to-rail input operational amplifier input stage. The bias module may generate a bias voltage and output the bias voltage to a gate of MP4 through a gate of MP1, output the bias voltage to a gate of MN5 through a gate of MN4, the MP4 may generate a bias current ITAILP according to the bias voltage received by the gate, and the MN5 may generate a bias current ITAILN according to the bias voltage received by the gate. In this way, the bias module may provide bias current ITAILN for NMOS differential input pairs in the rail-to-rail input operational amplifier input stage and bias current ITAILP for PMOS differential input pairs in the rail-to-rail input operational amplifier input stage.

Fig. 6 is a schematic circuit diagram of a detection module of a rail-to-rail input bias circuit according to an embodiment of the present application. The detection module of the rail-to-rail input bias circuit shown in fig. 6 may include a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, and an OR gate OR.

As shown in fig. 6, the gate of MN10 inputs the external input signal VIN, the gate of MN11 inputs the output signal VO, the source of MN10, the source of MN11 and the drain of MN7 are connected, the drain of MN10, the drain of MP6, the gate of MP6 and the gate of MP8 are connected, the drain of MN11, the drain of MP7, the gate of MP7 and the gate of MP9 are connected, the gate of MN7, the gate of MN8 and the gate of MN9 are connected in parallel with the second voltage vb, the values of vb can be set by those skilled in the art according to actual needs, the source of MP6, the source of MP7, the source of MP8 and the source of MP9 are connected to VDD, the source of MN7, the source of MN8 and the source of MN9 are connected to VSS, the drain of MN8, the drain of MP8 and the first input of or gate are connected, the drain of MN9, the drain of MP9 and the second input of or gate are connected, and the output of the or gate outputs the selection control signal SW.

The detection module of the rail-to-rail input bias circuit may detect the differential input amplitude of the differential input signals VIN and VO (i.e., the voltage difference between VIN and VO) of the rail-to-rail input operational amplifier before chopping switches. The gate of MN10 inputs VIN, the gate of MN11 inputs VO, the current flowing into MN10 is denoted IN1, and the current flowing into MN12 is denoted IN2.IN1 is copied to IN3 via a first current mirror formed by MP6 and MP8, and IN2 is copied to IN4 via a second current mirror formed by MP7 and MP 9. The currents of MN8, MN7, MN9 can be biased at Ith1, ISS, ith2, respectively, by setting vb, and the ratio between Ith1, ISS, ith2 can be adjusted by adjusting the ratio between the aspect ratio of MN8, the aspect ratio of MN7, and the aspect ratio of MN 9. IN3 is compared with Ith1, IN4 is compared with Ith2, if IN3< Ith1, the pull-down current between MP8 and MN8 is larger than the pull-up current, the pull-down current is larger so that the voltage vin_h between the drain of MP8 and the drain of MN8 is low, if IN3> Ith1, the pull-up current between MP8 and MN8 is larger than the pull-down current, the pull-up current is larger so that vin_h is high, if IN4< Ith2, the pull-down current between MP9 and MN9 is larger than the pull-up current, the voltage vo_h between the drain of MP9 and the drain of MN9 is low, and if IN4> Ith2, the pull-up current between MP9 and MN9 is larger than the pull-down current, and vo_h is high. VIN_H and VO_H are respectively input to a first input terminal and a second input terminal of the OR gate, and the OR gate outputs a selection control signal SW according to VIN_H and VO_H.

Illustratively, the current replication ratio of the first current mirror can be adjusted by adjusting the ratio between the width-to-length ratio of MP6 and the width-to-length ratio of MP8, so that the ratio between IN3 and IN1 can be adjusted, the current replication ratio of the second current mirror can be adjusted by adjusting the ratio between the width-to-length ratio of MP7 and the width-to-length ratio of MP9, so that the ratio between IN4 and IN2 can be adjusted, the ratio between Ith1, ISS, ith2 can also be adjusted by adjusting the ratio between the width-to-length ratio of MN8, the width-to-length ratio of MN7, and the width-to-length ratio of MN9, so that the detection threshold can be flexibly adjusted, so that the control signal SW is selected to be high when the differential input amplitude is greater than the detection threshold, and the control signal SW is selected to be low when the differential input amplitude is not greater than the detection threshold. The detection threshold may be set by those skilled in the art according to actual needs.

IN one embodiment, assuming that the ratio between the aspect ratio of MP6 and MP8 is 1:1, the ratio between the aspect ratio of MP7 and MP9 is 1:1, the ratio between the aspect ratio of MN7 and MN9 is m 1:m, the current replication ratio of the current mirror formed by MP6 and MP8 and the current mirror formed by MP7 and MP9 is 1:1, in3=in1, in4=in2, ith 1=ith 2=m×iss. Assuming that ith1=ith2=ith, it is possible to let ISS/2< Ith < ISS by adjusting the value of m, and let Ith be larger than the larger one of IN1 and IN2 when the differential input amplitude does not exceed the detection threshold, and let Ith be smaller than the larger one of IN1 and IN2 when the differential input amplitude exceeds the detection threshold.

When the differential input amplitude is 0 (i.e., when VIN is equal to VO), the gate voltages of MN10 and MN11 are equal, where in1=in2=iss/2. Since in3=in1, in4=in2, in3=in 4=iss/2. Since ISS/2< Ith, IN3< Ith, IN4< Ith, where vin_h and vo_h are both low, or the selection control signal SW output from the or gate is low, the multiplexer of the bias module may input the external input signal VIN to the gate of MN2 IN response to the selection control signal SW of low level.

When the differential input amplitude is positive (i.e., VIN is greater than VO) and the detection threshold is not exceeded, the gate voltage of MN10 is greater than the gate voltage of MN11, IN1> IN2, where IN1> ISS/2, IN2< ISS/2, i.e., IN3> ISS/2, IN4< ISS/2. Since ISS/2< Ith < ISS and Ith is greater than the larger of IN1 and IN2 (i.e., ith > IN 1) when the differential input amplitude does not exceed the detection threshold, IN3< Ith, IN4< Ith, where VIN_H and VO_H are both low, or the selection control signal SW output by the OR gate is low, the multiplexer of the biasing module can input the external input signal VIN to the gate of MN2 IN response to the selection control signal SW of low.

When the differential input amplitude is negative (i.e., VIN is less than VO) and the detection threshold is not exceeded, the gate voltage of MN11 is greater than the gate voltage of MN10, IN2> IN1, where IN1< ISS/2, IN2> ISS/2, i.e., IN3< ISS/2, IN4> ISS/2. Since ISS/2< Ith < ISS and Ith is greater than the larger of IN1 and IN2 (i.e., ith > IN 2) when the differential input amplitude does not exceed the detection threshold, IN3< Ith, IN4< Ith, where VIN_H and VO_H are both low, the OR gate outputs a select control signal SW that is low, and the multiplexer of the bias module inputs an external input signal VIN to the gate of MN2 IN response to the select control signal SW that is low.

When the differential input amplitude is positive and exceeds the detection threshold, IN1> IN2, IN1> ISS/2, IN2< ISS/2, i.e., IN3> ISS/2, IN4< ISS/2. Since ISS/2< Ith < ISS and Ith is smaller than the larger of IN1 and IN2 when the differential input amplitude exceeds the detection threshold (i.e., ith < IN 1), then IN3> Ith, IN4< Ith, where VIN_H is high, VO_H is low, or the select control signal SW output by the OR gate is high, the multiplexer of the bias module inputs the common mode input signal VIN_CM to the gate of MN2 IN response to the select control signal SW of high.

When the differential input amplitude is negative and exceeds the detection threshold, IN1< IN2, IN1< ISS/2, IN2> ISS/2, i.e., IN3< ISS/2, IN4> ISS/2. Since ISS/2< Ith < ISS and Ith is smaller than the larger one of IN1 and IN2 (i.e., ith < IN 2) when the differential input amplitude exceeds the detection threshold, IN3< Ith, IN4> Ith, at which time vin_h is low, vo_h is high, or the selection control signal SW output from the or gate is high, the multiplexer of the bias module inputs the common mode input signal vin_cm to the gate of MN2 IN response to the selection control signal SW of high level.

Compared with the conventional rail-to-rail input bias circuit shown in fig. 3, the rail-to-rail input bias circuit of the embodiment of the application is added with a detection module and a multiplexer, and the differential input amplitude of the rail-to-rail input operational amplifier can be automatically detected through the detection module. Since the external input signal VIN is generally a low-frequency continuous time signal, when the differential input amplitude exceeds the detection threshold, meaning that the output signal VO is greatly hopped, the common-mode input signal vin_cm will be significantly changed, at this time, the selection control signal SW output by the detection module is at a high level, the control terminal of the multiplexer in the bias module receives the selection control signal at the high level, and inputs the common-mode input signal vin_cm to the gate of MN 2. When the output transient signal is gradually built to be near a steady state value, the differential input amplitude gradually approaches 0, when the detection module detects that the differential input amplitude is not larger than a detection threshold value, the selection control signal SW output by the detection module is in a low level, the control end of the multiplexer in the bias module receives the selection control signal in the low level, and the external input signal VIN is input to the grid electrode of the MN 2. Since the bias currents ITAILN and ITAILP of the input stage are determined by the external input signal VIN, rather than by the common-mode input signal vin_cm, before the transient response of the rail-to-rail input operational amplifier ends, the offset ripple at the output of the rail-to-rail input operational amplifier caused by chopping does not cause a change in the bias current provided by the rail-to-rail input bias circuit. In addition, since at the end of the transient response, the output signal VO has been established to near the steady state value, vin=vo is approximately established, and the external input signal VIN is almost equal to the common-mode input signal (vin+vo)/2 of the actual circuit, so that the normal operation of the rail-to-rail input operational amplifier is not affected while the offset ripple effect is eliminated.

The embodiment of the application provides a simple rail-to-rail input bias circuit which can detect the change of the differential input amplitude of a rail-to-rail input operational amplifier in real time and dynamically adjust the bias current of a complementary differential input pair tube of an input stage. When the input differential amplitude is larger, the rail-to-rail input bias circuit is configured in a conventional rail-to-rail bias mode, and common-mode input signals are input into the bias module, so that the bias current of the complementary differential input pair transistors can be dynamically adjusted according to the output transient response, the input range of the rail-to-rail input operational amplifier is maximized, and the large-amplitude transient signals can be normally responded. When the transient input signal is built near a steady state value and the differential input amplitude is smaller, the bias current of the complementary differential input pair tube is allocated according to the external input signal, the bias current of the complementary differential input pair tube is decoupled from the output signal, the bias is completely carried out by the external input signal, the influence of offset ripple caused by chopping at the output end on the bias current is avoided, the output offset is not changed along with the amplitude of the input signal, and the common mode rejection ratio of the rail-to-rail input operational amplifier is remarkably improved.

The foregoing description of embodiments of the application has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. The rail-to-rail input bias circuit is characterized by being used for providing bias voltage for an input stage of a rail-to-rail input operational amplifier, and comprises a detection module and a bias module;

The detection module is used for generating a selection control signal according to a differential input amplitude and outputting the selection control signal to the bias module, wherein the differential input amplitude is a voltage difference value between an external input signal and an output signal of the rail-to-rail input operational amplifier;

the bias module is used for responding to the selection control signal to control the input of the external input signal or the common-mode input signal and transmitting the bias voltage generated according to the input external input signal or the common-mode input signal to the input stage of the rail-to-rail input operational amplifier, wherein the common-mode input signal is the sum of the external input signal and the output signal divided by 2;

wherein when the differential input amplitude is larger than a detection threshold value, the bias module responds to the selection control signal to input the common-mode input signal, when the differential input amplitude is smaller than or equal to the detection threshold value, the bias module responds to the selection control signal to input the external input signal,

The bias module comprises a multiplexer, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube and a third PMOS tube;

the control end of the multiplexer inputs the selection control signal, the first input end of the multiplexer inputs the common-mode input signal, and the second input end of the multiplexer inputs the external input signal;

The output end of the multiplexer is connected with the grid electrode of the second NMOS tube, and the multiplexer responds to the received selection control signal to control the common-mode input signal of the first input end of the multiplexer or the external input signal of the second input end to input the grid electrode of the second NMOS tube through the output end; the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the drain electrode of the third NMOS tube are connected, the drain electrode of the first NMOS tube, the drain electrode of the first PMOS tube and the gate electrode of the first PMOS tube are connected, the drain electrode of the second NMOS tube, the drain electrode of the second PMOS tube, the gate electrode of the second PMOS tube and the gate electrode of the third PMOS tube are connected, the drain electrode of the third PMOS tube, the drain electrode of the fourth NMOS tube and the gate electrode of the fourth NMOS tube are connected, the gate electrode of the first NMOS tube is connected with P/N switching threshold voltage, the gate electrode of the third NMOS tube is connected with first voltage, the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with positive power supply voltage of the rail-to-rail input operational amplifier, the source electrodes of the third NMOS tube and the fourth NMOS tube are connected with power supply voltage of the rail-to-input operational amplifier, the gate electrodes of the first NMOS tube and the fourth NMOS tube are connected with P/N switching threshold voltage, the first bias voltage and the fourth gate electrode of the fourth NMOS tube are used for outputting bias voltages respectively,

The detection module comprises a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube and an OR gate;

The method comprises the steps of inputting an external input signal to a grid electrode of a tenth NMOS tube, inputting a second voltage to a grid electrode of the eleventh NMOS tube, connecting a source electrode of the tenth NMOS tube, a source electrode of the eleventh NMOS tube and a drain electrode of a seventh NMOS tube, connecting a drain electrode of the tenth NMOS tube, a drain electrode of the sixth PMOS tube, a grid electrode of the sixth PMOS tube and a grid electrode of the eighth PMOS tube, connecting a drain electrode of the eleventh NMOS tube, a drain electrode of the seventh PMOS tube, a grid electrode of the seventh PMOS tube and a grid electrode of the ninth PMOS tube, connecting a grid electrode of the seventh NMOS tube, a grid electrode of the eighth NMOS tube and a grid electrode of the ninth NMOS tube in parallel with a second voltage, connecting a source electrode of the sixth PMOS tube, a source electrode of the eighth PMOS tube and a source electrode of the ninth PMOS tube with a positive power supply voltage of a rail-to-rail input operational amplifier, connecting a source electrode of the seventh NMOS tube, a drain electrode of the eighth NMOS tube and a source electrode of the eighth PMOS tube and a drain electrode of the eighth PMOS tube, connecting a source electrode of the eighth NMOS tube and a drain electrode of the eighth PMOS tube with a gate-to-rail input operational amplifier, and connecting a source electrode of the eighth NMOS tube and a drain electrode of the eighth PMOS tube and a gate-to a drain electrode of the eighth PMOS tube.

2. The rail-to-rail input bias circuit of claim 1, wherein the input stage of the rail-to-rail input operational amplifier comprises a first input NMOS transistor, a second input NMOS transistor, a first input PMOS transistor, a second input PMOS transistor, a fifth NMOS transistor, and a fourth PMOS transistor;

The grid electrode of the first input NMOS tube is connected with the grid electrode of the first input PMOS tube to form a positive input end of the rail-to-rail input operational amplifier, the grid electrode of the second input NMOS tube is connected with the grid electrode of the second input PMOS tube to form a negative input end of the rail-to-rail input operational amplifier, the source electrode of the first input NMOS tube, the source electrode of the second input NMOS tube and the drain electrode of the fifth NMOS tube are connected, the source electrode of the first input PMOS tube, the source electrode of the second input PMOS tube and the drain electrode of the fourth PMOS tube are connected, the grid electrode of the fifth NMOS tube is connected with the grid electrode of the fourth NMOS tube to receive the second bias voltage, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the first PMOS tube to receive the first bias voltage, the source electrode of the fourth PMOS tube is connected with the positive power supply voltage of the rail-to-rail input operational amplifier, and the source electrode of the fifth NMOS tube is connected with the negative power supply voltage of the rail-to-rail input operational amplifier.

3. The rail-to-rail input bias circuit of claim 2, wherein an output of the rail-to-rail input operational amplifier is connected to either a positive input or a negative input of the rail-to-rail input operational amplifier, wherein the positive input of the rail-to-rail input operational amplifier inputs the external input signal when the output of the rail-to-rail input operational amplifier is connected to the negative input of the rail-to-rail input operational amplifier, and wherein the negative input of the rail-to-rail input operational amplifier inputs the external input signal when the output of the rail-to-rail input operational amplifier is connected to the positive input of the rail-to-rail input operational amplifier.

4. The rail-to-rail input bias circuit of claim 1, wherein the select control signal is high when the differential input amplitude is greater than the detection threshold, the multiplexer inputs the common-mode input signal to the gate of the second NMOS in response to the select control signal, and wherein the select control signal is low when the differential input amplitude is less than or equal to the detection threshold, the multiplexer inputs the external input signal to the gate of the second NMOS in response to the select control signal.

5. The rail-to-rail input bias circuit of claim 1, wherein the detection threshold is adjusted based on at least one of a width-to-length ratio of the seventh NMOS transistor, a width-to-length ratio of the eighth NMOS transistor, a width-to-length ratio of the ninth NMOS transistor, a width-to-length ratio of the sixth PMOS transistor, a width-to-length ratio of the seventh PMOS transistor, a width-to-length ratio of the eighth PMOS transistor, or a width-to-length ratio of the ninth PMOS transistor.