CN119275717B

CN119275717B - Edge emitting laser chip and method for manufacturing the same

Info

Publication number: CN119275717B
Application number: CN202411197459.5A
Authority: CN
Inventors: 魏思航; 周江昊; 刘巍
Original assignee: Wuhan Minxin Semiconductor Co ltd
Current assignee: Wuhan Minxin Semiconductor Co ltd
Priority date: 2024-08-29
Filing date: 2024-08-29
Publication date: 2025-06-20
Anticipated expiration: 2044-08-29
Also published as: CN119275717A

Abstract

The application provides an edge-emitting laser chip and a manufacturing method thereof, wherein the edge-emitting laser chip comprises a reference electrode, an N-type injection layer, an active region and a P-type injection layer which are sequentially arranged above the reference electrode, at least two electric isolation regions are arranged in the P-type injection layer, a first channel is formed between the at least two electric isolation regions, two sides of the at least two electric isolation regions, which are away from the first channel, are respectively formed with a second channel, one side of the P-type injection layer, which is away from the active region, is provided with a forward electrode and at least two reverse electrodes, the forward electrode is positioned between the at least two reverse electrodes, the forward electrode has a positive potential compared with the reference electrode, when the forward electrode loads forward voltage, holes are injected into a quantum well of the active region through the first channel, electrons are also injected into the quantum well through the first channel, and when the at least two reverse electrodes load reverse voltage, holes on one side of the quantum well flow into the forward electrode through the second channel, and electrons on the other side of the quantum well flow into the reference electrode.

Description

Edge-emitting laser chip and manufacturing method thereof

Technical Field

The application belongs to the technical field of lasers, and particularly relates to an edge-emitting laser chip and a manufacturing method thereof.

Background

In many fields such as optical communication and laser processing, a high-performance laser chip has been a key component. With the continuous development of technology, the performance requirements on the laser chip are increasingly improved, such as higher power output, better stability, lower energy consumption and the like.

The traditional edge-emitting laser chip has certain limitations on structure and performance, and is easy to generate end surface COD (Catastrophic Optical Damage ), which greatly influences the reliability and service life of the laser chip.

Disclosure of Invention

Therefore, the technical problem to be solved by the application is to provide an edge-emitting laser chip and a manufacturing method thereof, which can reduce the temperature of an active region of the chip, improve the high-temperature saturation output power of the chip and avoid the occurrence of thermal failure and COD (chemical oxygen demand) phenomenon of the chip.

In order to solve the above problems, according to an aspect of the present application, there is provided an edge-emitting laser chip, including a reference electrode, one side of the reference electrode is sequentially provided with an N-type injection layer, an active region and a P-type injection layer, at least two electrical isolation regions are provided in the P-type injection layer, a first channel is formed between at least two of the electrical isolation regions, and two sides of the at least two electrical isolation regions facing away from the first channel are respectively formed with a second channel;

A positive electrode and at least two reverse electrodes are arranged on one side of the P-type injection layer, which is away from the active region, and the positive electrode is positioned between the at least two reverse electrodes;

When the positive electrode is loaded with a positive voltage, holes are injected into a quantum well of the active region through the first channel, and electrons are also injected into the quantum well;

At least two of the counter electrodes have a negative potential compared to the reference electrode, and when at least two of the counter electrodes are subjected to a reverse voltage, the holes on one side of the quantum well flow into the counter electrode through the second channel, and the electrons on the other side of the quantum well flow into the reference electrode.

Optionally, the active region includes an optical gain layer, the optical gain layer is an InGaAsP layer, the thickness of the optical gain layer is 6 nm-8 nm, and the symmetry center of the optical gain layer coincides with the symmetry center of the forward electrode.

Optionally, in the vertical direction, two sides of the optical gain layer are respectively provided with non-doped clutter guiding layers, and in the horizontal direction, two sides of the optical gain layer are respectively provided with N-type doped clutter guiding layers.

Optionally, the orthographic projection of the optical gain layer on the N-type injection layer is separated from or at least partially coincides with the orthographic projections of at least two of the electrically isolated regions on the N-type injection layer.

Optionally, the electrical isolation region penetrates through the P-type injection layer.

Optionally, the electrical isolation region does not penetrate through the P-type injection layer, and the distance between the electrical isolation region and the active region is 100 nm-400 nm.

Optionally, the electrical isolation region is a groove formed on the P-type injection layer.

Optionally, the grooves are filled with an electrically isolated N-type material, and the electrically isolated N-type material is InP.

In another aspect of the present application, there is provided a method for manufacturing an edge-emitting laser chip, including:

growing an N-type injection layer on one side of the substrate;

Growing an active region on one side of the N-type injection layer away from the substrate;

Growing a P-type injection layer on one side of the active region, which is away from the N-type injection layer;

removing part of the material of the P-type injection layer to form at least two grooves;

growing electrically isolated N-type material in at least two of the grooves to form at least two electrically isolated regions;

Manufacturing a forward electrode at the position of the P-type injection layer, which is away from one side of the active region and is opposite to the quantum well of the active region, and manufacturing a reverse electrode at two sides of the forward electrode in the horizontal direction at a certain distance;

and thinning the substrate to manufacture a reference electrode.

Optionally, the step of growing an active region on a side of the N-type implanted layer facing away from the substrate includes:

Sequentially growing an undoped waveguide layer, an optical gain layer and an undoped waveguide layer on one side of the N-type injection layer, which is away from the substrate;

removing the undoped waveguide layer, the optical gain layer and the undoped clutter layer in the first region;

growing an N-type clutter-doped guide layer in the first area;

The first area is at least a partial area of the forward electrode outside the projection range of the active area.

Advantageous effects

The embodiment of the invention provides an edge-emitting laser chip and a manufacturing method thereof, wherein when the edge-emitting laser chip works, a forward electrode is loaded with forward voltage to promote holes and electrons to be injected into a quantum well of an active region. At this time, the quantum well generates gain, but part of energy is lost in the form of heat radiation, and the temperature rises. However, when the reverse electrode is charged with a reverse voltage, holes on one side of the quantum well flow back into the forward electrode, and electrons on the other side flow back into the reference electrode, bringing heat to both the forward electrode and the reference electrode. Thus, heat is rapidly transferred from the area near the quantum well to the surface of the edge-emitting laser chip, thereby lowering the temperature near the quantum well. And the temperature of the quantum well can be flexibly adjusted by controlling the bias voltage of the counter electrode, so that the temperature of the quantum well can be effectively controlled even under the working condition of high temperature and high current by the edge-emitting laser chip, and the stable operation of the edge-emitting laser chip is ensured. Meanwhile, the temperature of the quantum well is accurately regulated and controlled, so that the edge-emitting laser chip can obtain larger high-temperature saturation output power in a high-temperature environment. In addition, the temperature of the quantum well at the end face is controlled, the current threshold and the power threshold of COD (catastrophic optical damage) can be improved, the occurrence probability of the end face catastrophic optical damage is obviously reduced, the reliability of the edge-emitting laser chip is greatly improved, and the service life of the edge-emitting laser chip is prolonged. Furthermore, the unique electrode structure design and carrier injection and outflow mechanism of the edge-emitting laser chip can realize accurate regulation and control of carriers and temperature in the quantum well, and avoid performance fluctuation caused by over-high temperature or carrier accumulation and other problems, so that the performance stability of the edge-emitting laser chip under different working conditions is enhanced.

Drawings

FIG. 1 is a cross-sectional view of an edge-emitting laser chip of an alternative embodiment of the present application;

FIG. 2 is a top view of an edge-emitting laser chip according to an alternative embodiment of the present application;

FIG. 3 is a flow chart of a method of fabricating an edge-emitting laser chip according to an alternative embodiment of the present application;

FIG. 4 is a schematic diagram showing the structure of one of the steps of fabricating an edge-emitting laser chip according to the present application;

FIG. 5 is a schematic diagram showing the structure of one of the steps of fabricating an edge-emitting laser chip according to the present application;

FIG. 6 is a schematic diagram showing the structure of one of the steps of fabricating an edge-emitting laser chip according to the present application;

FIG. 7 is a schematic diagram showing the structure of one of the steps of fabricating an edge-emitting laser chip according to the present application;

FIG. 8 is a schematic diagram showing the structure of one of the steps of fabricating an edge-emitting laser chip according to the present application;

FIG. 9 is a schematic diagram showing the structure of one of the steps of fabricating an edge-emitting laser chip according to the present application;

FIG. 10 is a schematic diagram showing the structure of one of the steps of fabricating an edge-emitting laser chip according to the present application;

FIG. 11 is a schematic diagram showing the structure of one of the steps of fabricating an edge-emitting laser chip according to the present application;

fig. 12 is a schematic diagram of a structure of one step of fabricating an edge-emitting laser chip according to the present application.

The reference numerals are expressed as:

1. Reference electrode, 2, N-type injection layer, 3, active region, 31, optical gain layer, 32, non-doped clutter guide layer, 33, N-doped clutter guide layer, 4, P-type injection layer, 5, electric isolation region, 6, forward electrode, 7, reverse electrode, 8, substrate.

Detailed Description

In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or in communication between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.

Referring to fig. 1 and 2, an embodiment of a first aspect of the present application provides an edge-emitting laser chip, which includes a reference electrode 1, one side of the reference electrode 1 is sequentially provided with an N-type injection layer 2, an active region 3 and a P-type injection layer 4, at least two electrical isolation regions 5 are disposed in the P-type injection layer 4, a first channel is formed between the at least two electrical isolation regions 5, two sides of the at least two electrical isolation regions 5 facing away from the first channel are respectively formed with a second channel, one side of the P-type injection layer 4 facing away from the active region 3 is provided with a forward electrode 6 and at least two reverse electrodes 7, the forward electrode 6 is located between the at least two reverse electrodes 7, the forward electrode 6 has a positive potential compared with the reference electrode 1, holes are injected into a quantum well of the active region 3 through the first channel, electrons are also injected into the quantum well through the first channel, the at least two reverse electrodes 7 have a negative potential compared with the reference electrode 1, and holes on one side of the quantum well flow into the reverse electrode 7 through the second channel when the reverse electrode 7 loads a reverse voltage.

When the edge-emitting laser chip is in operation, the forward electrode 6 is applied with a forward voltage to cause holes and electrons to be injected into the quantum well of the active region 3. At this time, the quantum well generates gain, but part of energy is lost in the form of heat radiation, and the temperature rises. However, when the counter electrode 7 is charged with a reverse voltage, holes on one side of the quantum well flow back into the counter electrode 7, and electrons on the other side flow back into the reference electrode 1, bringing heat to the counter electrode 7 and the reference electrode 1. Thus, heat is rapidly transferred from the area near the quantum well to the surface of the edge-emitting laser chip, thereby lowering the temperature near the quantum well. And by controlling the bias voltage of the counter electrode 7, the temperature of the quantum well can be flexibly adjusted, so that the temperature of the quantum well can be effectively controlled even under the working condition of high temperature and high current of the edge-emitting laser chip, and the stable operation of the edge-emitting laser chip is ensured. Meanwhile, the temperature of the quantum well is accurately regulated and controlled, so that the edge-emitting laser chip can obtain larger high-temperature saturation output power in a high-temperature environment. In addition, the temperature of the quantum well at the end face is controlled, the current threshold and the power threshold of COD (catastrophic optical damage) can be improved, the occurrence probability of the end face catastrophic optical damage is obviously reduced, the reliability of the edge-emitting laser chip is greatly improved, and the service life of the edge-emitting laser chip is prolonged. Furthermore, the unique electrode structure design and carrier injection and outflow mechanism of the edge-emitting laser chip can realize accurate regulation and control of carriers and temperature in the quantum well, and avoid performance fluctuation caused by over-high temperature or carrier accumulation and other problems, so that the performance stability of the edge-emitting laser chip under different working conditions is enhanced.

The reference electrode 1, the forward electrode 6 and the reverse electrode 7 may be made of metals such as titanium, platinum or gold. For example, when the reference electrode 1, the forward electrode 6 and the reverse electrode 7 are made of titanium, the thicknesses of the reference electrode 1, the forward electrode 6 and the reverse electrode 7 are 30nm to 130nm, when the reference electrode 1, the forward electrode 6 and the reverse electrode 7 are made of platinum, the thicknesses of the reference electrode 1, the forward electrode 6 and the reverse electrode 7 are 30nm to 130nm, and when the reference electrode 1, the forward electrode 6 and the reverse electrode 7 are made of gold, the thicknesses of the reference electrode 1, the forward electrode 6 and the reverse electrode 7 are 450nm to 550nm.

The reference electrode 1 is arranged on the back surface of the edge-emitting laser chip, the forward electrode 6 and the reverse electrode 7 are arranged on the front surface of the edge-emitting laser chip, and the forward electrode 6 and the reverse electrode 7 are coplanar.

An N-type injection layer 2, an active region 3 and a P-type injection layer 4 are arranged between the reference electrode 1 and the forward electrode 6 and the reverse electrode 7, the active region 3 is located between the N-type injection layer 2 and the P-type injection layer 4, the N-type injection layer 2 is located at one side of the active region 3 close to the reference electrode 1, and the P-type injection layer 4 is located at one side of the active region 3 close to the forward electrode 6 and the reverse electrode 7.

Specifically, the P-type injection layer 4 may be made of an electrically injected P-type material, which after being injected into the P-type material, causes a large amount of holes to be generated in the P-type material, and the N-type injection layer 2 may be made of an electrically injected N-type material, which after being injected into the N-type material, causes a large amount of electrons to be generated in the N-type material. It will be appreciated that the P-type injection layer 4 and the N-type injection layer 2 are used to provide a carrier source for the active region 3, and when holes and electrons are injected into the active region 3, the holes and electrons recombine in the active region 3 to generate photons, thereby achieving light emission or amplification.

Wherein, the electric injection P type material and the electric injection N type material can be InP, and the thicknesses of the P type injection layer 4 and the N type injection layer 2 can be 1000 nm-1400 nm.

Wherein holes are positively charged carriers and electrons are negatively charged carriers.

Wherein holes move in the low potential direction and electrons move in the high potential direction.

Specifically, the potential value of the forward electrode 6 is higher than that of the reference electrode 1, and when the forward electrode 6 is subjected to a forward voltage, holes generated by the P-type injection layer 4 move toward the reference electrode 1 and flow into the active region 3 between the forward electrode 6 and the reference electrode 1. Meanwhile, electrons generated by the N-type injection layer 2 move toward the forward electrode 6 and flow into the active region 3 between the forward electrode 6 and the reference electrode 1, and similarly, the potential value of the reverse electrode 7 is lower than that of the reference electrode 1, and when the reverse electrode 7 is charged with a reverse voltage, holes generated by the P-type injection layer 4 move toward the reverse electrode 7 and flow into the reverse electrode 7. Electrons generated by the N-type injection layer 2 move toward the reference electrode 1 and flow toward the reference electrode 1. It will be appreciated that holes flowing into the counter electrode 7 and electrons flowing into the reference electrode 1 are used to carry heat to the counter electrode 7 and the reference electrode 1. Thereby, heat is rapidly transferred from the area near the active region 3 to the surface of the edge-emitting laser chip, thereby lowering the temperature of the active region 3.

The reference electrode 1 may be a zero potential electrode, the forward electrode 6 may be a two volt positive potential electrode, and the reverse electrode 7 may be a two volt negative potential electrode.

Specifically, only one forward electrode 6 may be provided, the forward electrode 6 is located in the middle of the front face of the edge-emitting laser chip, at least two reverse electrodes 7 may be provided, and at least two reverse electrodes 7 are located in the front edge of the edge-emitting laser chip and are disposed opposite to each other. It will be appreciated that the forward electrode 6 is located in the middle of the front surface of the edge-emitting laser chip, and can concentrate injection of holes and electrons into the active region 3, so as to ensure stable excitation of the quantum well to generate light under normal operating conditions. And at least two counter electrodes 7 are provided at the edges, enabling heat extraction from the quantum wells from at least two directions. Meanwhile, at least two opposite electrodes 7 which are oppositely arranged can form more uniform electric field distribution, so that heat flows out of the periphery of the quantum well more uniformly in the process of being extracted, the situation of local overheating or supercooling is avoided, and the accuracy of temperature regulation is further improved. That is, the layout is helpful to realize dynamic balance of carrier injection and extraction, and improves the utilization efficiency of carriers in the quantum well, thereby enhancing the light emission or amplification effect.

In this embodiment, two counter electrodes 7 are provided.

The positive electrode 6 is located between two opposite electrodes 7, and the positive electrode 6 is spaced from both electrodes in a certain distance. It will be appreciated that a distance apart may avoid electric field interference between the forward electrode 6 and the reverse electrode 7, ensuring a more orderly and stable injection and extraction of carriers. When the reverse electrode 7 is loaded with reverse voltage, heat is conducted from the quantum well to the reverse electrodes 7 on two sides, and the forward electrode 6 and the reverse electrode 7 are separated by a certain distance, so that the flow path of the heat is not blocked, the heat can be more quickly and uniformly transferred from the area near the quantum well to the surface of the chip, and the temperature near the quantum well is reduced. This helps to improve the accuracy of temperature regulation and avoid damage to chip performance caused by local overheating.

At least two electric isolation regions 5 are arranged in the P-type injection layer 4 and used for dividing the channel region of the P-type injection layer 4 so as to ensure orderly flow of carriers in different channels and avoid unnecessary cross interference.

It should be noted that the number of the electrically isolated regions 5 is determined by the number of the positive electrodes 6. For example, when one forward electrode 6 is provided, two electrical isolation regions 5 are provided, when two forward electrodes 6 are provided, three electrical isolation regions 5 are provided, and when three forward electrodes 6 are provided, four electrical isolation regions 5 are provided. In this embodiment, one forward electrode 6 is provided, and two electrically isolated regions 5 are provided.

Specifically, the two electrically isolated regions 5 extend in the thickness direction of the P-type implanted layer 4, so that a first channel is successfully built between the two electrically isolated regions 5, and a second channel is formed on each of two sides of the two electrically isolated regions 5 facing away from the first channel.

Wherein, in the thickness direction of the P-type injection layer 4, the first channel is arranged opposite to the forward electrode 6, and the second channel is arranged opposite to the reverse electrode 7.

Specifically, when the forward electrode 6 is subjected to a forward voltage, holes can be precisely injected into the quantum well of the active region 3 through the first channel provided opposite to the forward electrode 6, and efficient carrier injection can be achieved. Meanwhile, when the counter electrode 7 is charged with a reverse voltage, holes on one side of the quantum well can smoothly flow into the counter electrode 7 through a second channel arranged opposite to the counter electrode 7, and the heat transfer process is completed.

In some specific examples, the projections of the forward electrode 6 and the counter electrode 7 on the P-type implanted layer 4 coincide with at least part of the electrically isolated region 5.

In other specific examples, the projections of the forward electrode 6 and the reverse electrode 7 on the P-type implanted layer 4 are separated from the electrically isolated region 5.

In some possible embodiments of the disclosure, referring to fig. 1, the active region 3 includes an optical gain layer 31, where the optical gain layer 31 is an InGaAsP layer, the thickness of the optical gain layer 31 is 6 nm-8 nm, and the symmetry center of the optical gain layer 31 coincides with the symmetry center of the forward electrode 6. Thereby, carriers injected from the forward electrode 6 can be more uniformly distributed in the optical gain layer 31. This contributes to efficient recombination of carriers in the optical gain layer 31, further enhancing the light generation and amplification effect. Meanwhile, the method is also beneficial to avoiding local overheating phenomenon and improving the thermal stability of the edge-emitting laser chip. When the reverse electrode 7 is subjected to reverse voltage for temperature regulation, heat can be more effectively transferred from the region near the optical gain layer 31 to the surface of the emitting laser chip, and the temperature near the optical gain layer 31 can be reduced.

The optical gain layer 31 may be made of InGaAsP material, which has good optical gain characteristics.

The thickness of the optical gain layer 31 may be 6nm to 8nm. For example, the thickness of the optical gain layer 31 is 6.0nm, or 6.1nm, or 6.2nm, or 6.3nm, or 6.4nm, or 6.5nm, or 6.6nm, or 6.7nm, or 6.8nm, or 6.9nm, or 7.0nm, or 7.1nm, or 7.2nm, or 7.3nm, or 7.4nm, or 7.5nm, or 7.6nm, or 7.7nm, or 7.8nm, or 7.9nm, or 8.0nm. It is understood that the thickness of the optical gain layer 31 may be other values than the above values, as long as the thickness of the optical gain layer 31 is within a range of 6nm to 8nm. The optical gain layer 31 having a thickness of 6nm to 8nm can realize efficient optical amplification in the active region 3. When the forward electrode 6 is charged with a forward voltage, holes and electrons are injected into the active region 3, and photons are generated by recombination in the optical gain layer 31, and the photons can be sufficiently enhanced therein due to the moderate thickness of the optical gain layer 31, thereby improving the light emission efficiency.

In some specific examples, the projection of the optical gain layer 31 onto the N-type implanted layer 2 is separated from the projections of the two electrically isolated regions 5 onto the N-type implanted layer 2. Thereby, the disturbance of the carrier flow in the optical gain layer 31 by the electrically isolated region 5 can be reduced. The carriers can more smoothly participate in the recombination process in the optical gain layer 31, improving optical gain efficiency.

In other specific examples, the front projection of the optical gain layer 31 onto the N-type implanted layer 2 at least partially coincides with the front projections of the two electrically isolated regions 5 onto the N-type implanted layer 2. This can guide the carriers to flow more intensively to the optical gain layer 31, and increase the concentration of the carriers in the optical gain layer 31, thereby enhancing the optical gain effect.

In some possible embodiments of the present disclosure, referring to fig. 1, undoped waveguide layers 32 are provided on both sides of the optical gain layer 31 in the vertical direction, respectively.

It will be appreciated that the undoped waveguide layer 32 and the optical gain layer 31 form a refractive index difference in the vertical direction. This difference causes the propagation of light in the vertical direction to be restricted, and more light is confined to the optical gain layer 31 and its vicinity, thereby improving the light utilization efficiency. This helps to enhance the optical gain effect, making the edge-emitting laser chip more excellent in light emission or amplification. Meanwhile, by effectively confining the light, the undoped waveguide layer 32 can reduce the possibility of leakage of the light from the optical gain layer 31 to the surrounding area, ensure more concentrated and stable propagation of the light inside the edge-emitting laser chip, and improve the intensity and quality of the optical signal.

Wherein the vertical direction may be the thickness direction of the optical gain layer 31. In the vertical direction, undoped waveguide layers 32 are provided on both sides of the optical gain layer 31, respectively, that is, undoped waveguide layers 32 are provided above and below the optical gain layer 31.

Wherein the undoped waveguide layer 32 may be made of InGaAsP material. The InGaAsP material may provide a refractive index matching the optical gain layer 31 so that confinement of light can be better achieved in the vertical direction. Light is totally or partially reflected at the interface between the undoped waveguide layer 32 and the optical gain layer 31, thereby confining the light to the optical gain layer 31 and its vicinity, improving the light transmission efficiency and optical gain effect.

The thickness of the non-doped waveguide layer 32 may be 150nm to 250nm.

Wherein the width of the undoped waveguide layer 32 may be the same as the width of the optical gain layer 31.

In some possible embodiments of the present disclosure, referring to fig. 1, N-type clutter-doped guiding layers 33 are disposed on two sides of the optical gain layer 31 in the horizontal direction.

It can be understood that the N-type clutter-doped guiding layer 33 has a certain heat conduction capability, and the heat generated by the optical gain layer 31 can diffuse to two sides through the N-type clutter-doped guiding layer 33, so that under the condition that the reverse electrode 7 is loaded with a reverse voltage, holes and electrons can carry heat to flow into the reverse electrode 7 and the reference electrode 1 respectively, and heat dissipation is completed. In addition, the N-doped waveguide layer 33 may also serve as an additional heat dissipation path to conduct heat away from the vicinity of the optical gain layer 31.

The horizontal direction may be the width direction of the optical gain layer 31. In the horizontal direction, the optical gain layer 31 is provided with N-type clutter guiding layers 33 on both sides, that is, the optical gain layer 31 is provided with N-type clutter guiding layers 33 on both left and right sides.

The N-type doped waveguide layer 33 may be made of InGaAsP material. The InGaAsP material itself has a certain heat conduction capability, and the heat conduction performance of the InGaAsP material can be further improved after the N type doping. When the edge-emitting laser chip works to generate heat, the N-type clutter-doped guide layer 33 can conduct heat out more quickly, and the temperatures of the optical gain layer 31 and other parts of the edge-emitting laser chip are reduced.

The thickness of the N-type doped waveguide layer 33 may be 150nm to 250nm.

Specifically, the thickness of the N-type doped waveguide layer 33 is the sum of the thickness of the optical gain layer 31 and the thickness of the two undoped waveguide layers 32.

In some possible embodiments of the present disclosure, referring to fig. 12, the electrically isolated region 5 extends through the P-type implanted layer 4. Therefore, the P-type injection layer can be thoroughly divided into different areas, carriers in all channels are ensured to flow strictly according to a preset path, carrier cross interference among different channels is avoided, and the ordering and controllability of carrier flow are improved. That is, compared to the partially isolated design, the penetrating type electric isolation region 5 can provide a stronger electric isolation effect, reduce the risk of electric leakage and crosstalk, and improve the stability of the electric performance of the edge-emitting laser chip.

Furthermore, the electrically isolated regions 5 may be arranged as follows:

Referring to fig. 1, the electrical isolation region 5 does not penetrate the P-type implantation layer 4, and the distance between the electrical isolation region 5 and the active region 3 is 100 nm-400 nm. This can reduce stress concentration due to abrupt structural changes. This helps to reduce performance fluctuations and risk of damage to the edge-emitting laser chip during operation due to thermal expansion and mechanical stress, and to improve mechanical stability and reliability of the edge-emitting laser chip. That is, the unperforated electrically isolated regions 5 may be easier to implement and control in the manufacturing process than a pass-through design. The specific interval distance also provides a certain margin for controlling the process precision, and improves the feasibility and the yield of manufacturing the edge-emitting laser chip.

In some possible embodiments of the present disclosure, referring to fig. 9, the electrically isolated region 5 is a recess formed on the P-type implanted layer 4. It will be appreciated that the recess as electrically isolated region 5 enables to clearly delimit the different carrier channels. The flow of the carriers in the P-type injection layer is strictly limited in a specific area, disordered diffusion and cross interference of the carriers are avoided, and the directionality and controllability of the carrier flow are improved. Meanwhile, the shape and the position of the groove are relatively fixed, and stable structural support is provided for the carrier channel. This helps to maintain the stability of the carrier channel under different operating conditions, ensuring that carriers can be continuously and stably injected into the quantum well of the active region 3.

Wherein the grooves may be rectangular grooves or the like.

In some possible embodiments of the present disclosure, referring to fig. 10, the grooves are filled with an electrically isolating N-type material, which is InP. It will be appreciated that InP, as an electrically isolating N-type material, fills the grooves and can effectively prevent lateral diffusion of carriers between different channels. Because InP has specific electrical properties, it can form a region of high resistance, and limit the flow of carriers, thereby enhancing the electrical isolation effect and ensuring that carriers in each channel can flow independently and orderly. Meanwhile, the InP material has certain heat conduction capability. When InP is filled into the grooves, it can act as a heat conduction channel to help conduct away the heat generated near the quantum wells. Meanwhile, the thermal expansion coefficients of InP and the P-type injection layer 4 and other surrounding materials are relatively matched, so that the thermal stress caused by the thermal expansion difference is reduced, and the thermal stability of the chip is improved.

In the present application, the edge-emitting laser chip may employ materials, thicknesses, and refractive indices as shown in the following table. It will be appreciated that in other implementations, the materials, thicknesses, and refractive indices of the layers may be adjusted by the operator according to actual needs, and the application is not limited in any way.

TABLE 1 materials, thicknesses and refractive indices of layers of edge-emitting laser chips

In the embodiment of the second aspect of the present application, referring to fig. 3 to 12, there is provided a method for manufacturing an edge-emitting laser chip, which can precisely control the thickness and material quality of each layer by sequentially growing an N-type injection layer 2, an active region 3 and a P-type injection layer 4 on a substrate 8. The growth mode can ensure the clear interface between layers, reduce interface defects and improve the performance and reliability of the chip. Meanwhile, by removing part of the material of the P-type implanted layer 4 to form a recess and then growing an electrically isolated N-type material in the recess, the position, shape and size of the electrically isolated region 5 can be precisely controlled. The method can realize accurate division of the carrier channels and improve the flow efficiency and isolation effect of carriers. Meanwhile, a forward electrode 6 is manufactured at the side of the P-type injection layer 4, which is away from the active region 3, relative to the quantum well position of the active region 3, and a reverse electrode 7 is manufactured at two sides of the forward electrode 6 in the horizontal direction at a certain distance. The layout is beneficial to realizing efficient injection and extraction of carriers and improving the utilization efficiency of carriers in the quantum well, thereby enhancing the light emission or amplification effect. Meanwhile, the interval distance between the forward electrode 6 and the reverse electrode 7 can be accurately adjusted according to actual requirements, so that electric field interference is avoided, and the injection and extraction processes of carriers are ensured to be more orderly and stable. Meanwhile, the reasonable electrode spacing can optimize the heat conduction path and improve the thermal stability of the chip.

The method is implemented by the following steps:

step S101, growing an N-type implanted layer 2 on one side of the substrate 8.

The substrate 8 is a basic supporting material for chip manufacture, and provides a stable platform for the growth of subsequent layers. It has good mechanical strength, thermal stability and chemical stability, can bear the influence of various process steps and external environment in the chip manufacturing process.

The N-type implanted layer 2 may be grown by using a semiconductor epitaxial growth technique, such as Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). The techniques can accurately control parameters such as temperature, pressure, gas flow, doping concentration and the like in the growth process, thereby realizing the growth of the high-quality and uniform N-type injection layer 2.

Specifically, first, the substrate 8 is cleaned and pretreated to remove impurities and contaminants from the surface, ensuring the cleaning and flatness of the surface of the substrate 8. The substrate 8 is then placed in a growth apparatus, and parameters of the growth apparatus, such as temperature, pressure, gas flow, etc., are adjusted in preparation for growing the N-type implanted layer 2. In the growth apparatus, an N-type implanted layer 2 is deposited on the surface of a substrate 8 by introducing a precursor gas containing an N-type dopant, such as phosphane, etc., and reacting with other reactive gases, such as arsine, hydrogen, etc., under specific temperature and pressure conditions. In the growth process, parameters such as growth rate, doping concentration, layer thickness and the like need to be strictly controlled so as to ensure that the quality and performance of the N-type implanted layer 2 meet the requirements. After the growth is completed, the N-type implanted layer 2 is inspected and analyzed, such as measuring layer thickness, doping concentration, crystal quality, etc. If problems are found, appropriate post-treatments, such as annealing, etching, etc., may be performed to improve the performance of the N-type implanted layer 2.

Step S201, growing an active region 3 on the side of the N-type implanted layer 2 facing away from the substrate 8.

The N-type implanted layer 2 is a semiconductor layer with specific electrical properties, which provides a basis for the growth of the active region 3. The active region 3 is grown on one side of the N-type injection layer 2, which is far away from the substrate 8, on one hand, the N-type injection layer 2 can provide electron carriers for the active region 3, and the active region 3 can generate photons by recombination of electrons and holes in the region in the subsequent working process, so that light emission or amplification is realized, and on the other hand, the layered structure is favorable for realizing directional injection and recombination of the carriers, and the light generation efficiency is improved.

The active region 3 is the core of the edge-emitting laser chip, which determines the optical properties of the chip. The active region 3 includes a structure such as an optical gain layer 31, which mainly functions to generate photons by recombination of electrons and holes and to amplify light. Specifically, when the forward electrode 6 is applied with a forward voltage, electrons from the N-type injection layer 2 and holes from the P-type injection layer 4 are injected into the active region 3. In the active region 3, electrons and holes recombine under specific conditions (as in a quantum well structure), releasing energy, producing photons. These photons are continually reflected and amplified within the active region 3, ultimately forming a laser output.

The epitaxial growth mode of the active region 3 and the N-type implanted layer 2 is the same, and will not be described here again.

Step S301 of growing a P-type implanted layer 4 on the side of the active region 3 facing away from the N-type implanted layer 2.

The P-type injection layer 4 may be made of an electrically injected P-type material, for example, a semiconductor material such as InP, which is formed by a specific doping process. The doped impurities are typically acceptor impurities, such as zinc, which can form holes in the material, increasing the concentration of holes.

The P-type injection layer 4 has a certain conductivity, and can provide a channel for hole transmission. The N-type semiconductor device and the N-type injection layer 2 and the active region 3 form a PN junction structure together, and the injection and recombination of carriers are promoted under the action of forward voltage.

The P-type implantation layer 4 and the active region 3 have the same epitaxial growth mode, and will not be described herein.

Step S401, removing part of the material of the P-type implanted layer 4 to form at least two grooves.

Wherein the grooves are used for realizing electrical isolation. By removing part of the material of the P-type injection layer 4 to form the grooves, different areas can be divided in the chip, and carriers are prevented from flowing in an unnecessary direction, so that the electrical performance and stability of the chip are improved.

In particular, photolithography and etching techniques may be used to remove portions of the material of the P-type implanted layer 4 to form the recess. First, a photoresist is coated on the surface of the P-type implant layer 4, and then a specific pattern is exposed on the photoresist using a photolithography machine. The exposed photoresist is chemically changed such that during development, the exposed or unexposed portions are dissolved away, thereby forming a mask (SiO ₂) on the photoresist that is the same as the desired groove pattern. Next, the portion of the P-type implanted layer 4 not protected by the photoresist is removed using an etching process. The etching process may be a dry etching or a wet etching. The dry etching generally uses plasma or reactive ion etching and other technologies, and has higher etching precision and selectivity, while the wet etching uses chemical solution to dissolve the material of the P-type injection layer 4, and has higher etching rate, but has relatively lower etching precision and selectivity.

Step S501 of growing electrically isolated N-type material in at least two recesses to form at least two electrically isolated regions 5.

It will be appreciated that by growing electrically isolating N-type material within the recess, the electrical isolation between the different regions may be further enhanced. This helps to prevent carriers from flowing in unnecessary directions, reduce problems such as leakage and crosstalk, and improve the electrical properties and stability of the edge-emitting laser chip.

Among them, an N-type material having good electrical insulation properties can be selected as the electrical isolation material. For example, a semiconductor material such as InP, alGaAs, or the like may be selected and doped to have N-type conductivity. These materials can form a good interface with the surrounding semiconductor layer during growth, ensuring electrical isolation.

Specifically, during growth, the electrically isolating material gradually fills the recess until it is level with or slightly above the surrounding semiconductor layer. In order to ensure good filling effect, multilayer growth or gradual growth and other technologies can be adopted, so that the occurrence of voids or non-uniformity is avoided.

In step S601, a forward electrode 6 is manufactured at a position of the P-type injection layer 4, which is away from the active region 3 and is opposite to the quantum well of the active region 3, and a reverse electrode 7 is respectively manufactured at two sides of the forward electrode 6 in the horizontal direction at a certain distance.

It will be appreciated that the forward electrode 6 is fabricated on the side of the P-type injection layer facing away from the active region 3 and at a quantum well location relative to the active region 3, primarily for efficient carrier injection. The quantum well is a main area of optical gain, injected carriers can enter the quantum well more directly by arranging the forward electrode 6 near the position, the recombination efficiency of the carriers and photons is improved, and therefore the light emission or amplification effect is enhanced, and the reverse electrode 7 is manufactured at two sides of the forward electrode 6 in the horizontal direction at a certain distance so as to realize specific electric field distribution and carrier extraction functions. The electric field between the counter electrode 7 and the forward electrode 6 can control the flow direction and distribution of carriers in the chip, while also contributing to heat dissipation and temperature control. Short circuit and interference between electrodes can be avoided by a certain distance, and meanwhile, certain flexibility is provided for structural design and performance optimization of the chip.

Specifically, first, the surface of the P-type implanted layer 4 is cleaned and treated to ensure that the electrode adheres well. Then, the positions and dimensions of the forward electrode 6 and the reverse electrode 7 are determined according to design requirements, and a mask of an electrode pattern is made on the chip surface using a technique such as photolithography. Then, a suitable electrode material, such as a metal (e.g., gold, aluminum, etc.), or an electrically conductive oxide, etc., is selected, and the electrode material is deposited on the chip surface by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or electroplating, etc. In the deposition process, parameters such as deposition rate, thickness, uniformity and the like need to be controlled to ensure the quality and performance of the electrode. Finally, etching or other technique is used to remove the excess electrode material, forming the desired pattern of the forward electrode 6 and the reverse electrode 7. In the etching process, the etching depth and the etching precision need to be controlled, so that other parts of the chip are prevented from being damaged.

Step S701, thinning the substrate 8 to manufacture the reference electrode 1.

It will be appreciated that thinning the substrate 8 may reduce the overall thickness of the edge-emitting laser chip, making it easier to handle during subsequent processes for making the reference electrode 1, etc. Thinner substrates 8 may reduce material usage, reduce cost, and in some applications, thinner edge-emitting laser chips may be more advantageous for integration and packaging. Meanwhile, the heat dissipation area of the edge-emitting laser chip can be increased by thinning the substrate 8, and the heat dissipation efficiency is improved. When the edge-emitting laser chip works, certain heat can be generated, and if heat cannot be timely dissipated, the performance and the service life of the edge-emitting laser chip can be affected. By thinning the substrate 8, heat can be more quickly dissipated, and the operating temperature of the edge-emitting laser chip can be reduced.

Among them, the substrate 8 may be thinned by mechanical polishing, chemical Mechanical Polishing (CMP), dry etching, or the like. These methods can precisely control the thickness of the substrate 8 and ensure the surface flatness and smoothness after thinning. During the thinning process, care should be taken to avoid damage to other parts of the chip.

Wherein the reference electrode 1 is fabricated on the thinned substrate 8. Metal deposition, photolithography, etching, etc. process steps may be employed to pattern the reference electrode 1. Suitable electrode materials, such as gold, aluminum, copper, etc., are selected to ensure good conductivity and stability. The thickness, shape and position of the electrode need to be strictly controlled in the manufacturing process to meet the design requirements.

In some possible embodiments provided by the present application, step S201 includes:

in step S2011, an undoped waveguide layer 32, an optical gain layer 31 and an undoped waveguide layer 32 are sequentially grown on the side of the N-type injection layer 2 facing away from the substrate 8.

Specifically, the undoped waveguide layer 32 is grown on the N-type implanted layer 2 using a semiconductor epitaxial growth technique such as Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE), or the like. After the growth of the undoped waveguide layer 32 is completed, the growth of the optical gain layer 31 is continued. Finally, an undoped waveguide layer 32 is grown again on the optical gain layer 31 to form a sandwich structure.

Step S2012, removing the undoped waveguide layer 32, the optical gain layer 31 and the undoped waveguide layer 32 of the first region.

Wherein the first region is at least a partial region of the forward electrode 6 outside the projection range of the active region 3.

Specifically, a photoresist is coated on the surface of the layered structure formed in step S2011, and then a specific pattern is exposed on the photoresist by using a photolithography machine, so that a first area is defined on the photoresist. The exposed photoresist is chemically changed and the exposed or unexposed portions are dissolved during development to form the same mask on the photoresist as the desired removed area pattern. Next, an etching process is used to remove the layers of material of the areas not protected by the photoresist. The etching process may be a dry etching or a wet etching.

In step S2013, an N-type doped waveguide layer 33 is grown in the first region.

Specifically, before the N-type clutter-doped layer 33 is grown, the first region needs to be surface treated to ensure that its surface is clean and flat so that new materials can grow well. A suitable waveguide material, such as InGaAsP or the like, is then selected and epitaxially grown under specific growth conditions by introducing a precursor gas containing an N-type dopant, such as a phosphine or the like. By precisely controlling the concentration of the dopant and parameters during growth, the desired N-type doping level and waveguide layer performance can be achieved.

It will be readily appreciated by those skilled in the art that the above advantageous ways can be freely combined and superimposed without conflict.

The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application. The foregoing is merely a preferred embodiment of the present application, and it should be noted that it will be apparent to those skilled in the art that modifications and variations can be made without departing from the technical principles of the present application, and these modifications and variations should also be regarded as the scope of the application.

Claims

1. The edge-emitting laser chip is characterized by comprising a reference electrode (1), wherein an N-type injection layer (2), an active region (3) and a P-type injection layer (4) are sequentially arranged on one side of the reference electrode (1), at least two electric isolation regions (5) are arranged in the P-type injection layer (4), a first channel is formed between the at least two electric isolation regions (5), and second channels are respectively formed on two sides, deviating from the first channel, of the at least two electric isolation regions (5);

A positive electrode (6) and at least two reverse electrodes (7) are arranged on one side, away from the active region (3), of the P-type injection layer (4), and the positive electrode (6) is positioned between the at least two reverse electrodes (7);

the positive electrode (6) has a positive potential compared to the reference electrode (1), when the positive electrode (6) is loaded with a positive voltage, holes are injected into the quantum well of the active region (3) through the first channel, and electrons are also injected into the quantum well;

at least two of the counter electrodes (7) have a negative potential compared to the reference electrode (1), when at least two of the counter electrodes (7) are subjected to a counter voltage, holes on one side of the quantum well flow into the counter electrode (7) through the second channel, and electrons on the other side of the quantum well flow into the reference electrode (1).

2. The edge-emitting laser chip according to claim 1, wherein the active region (3) comprises an optical gain layer (31), the optical gain layer (31) is an InGaAsP layer, the optical gain layer (31) has a thickness of 6nm to 8nm, and a center of symmetry of the optical gain layer (31) coincides with a center of symmetry of the forward electrode (6).

3. The edge-emitting laser chip according to claim 2, wherein undoped waveguide layers (32) are provided on both sides of the optical gain layer (31) in a vertical direction, and N-type clutter-doped waveguide layers (33) are provided on both sides of the optical gain layer (31) in a horizontal direction.

4. Edge-emitting laser chip according to claim 2, characterized in that the orthographic projection of the optical gain layer (31) on the N-type injection layer (2) is separated from or at least partially coincides with the orthographic projections of at least two of the electrically isolated regions (5) on the N-type injection layer (2).

5. The edge-emitting laser chip according to claim 1, characterized in that the electrically isolated region (5) extends through the P-type injection layer (4).

6. The edge-emitting laser chip according to claim 1, wherein the electrical isolation region (5) does not penetrate the P-type injection layer (4), and a distance between the electrical isolation region (5) and the active region (3) is 100 nm-400 nm.

7. The edge-emitting laser chip according to claim 1, characterized in that the electrically isolated region (5) is a recess provided in the P-type injection layer (4).

8. The edge-emitting laser chip of claim 7, wherein the recess is filled with an electrically isolated N-type material, the electrically isolated N-type material being InP.

9. A method of fabricating an edge-emitting laser chip, comprising:

Growing an N-type injection layer (2) on one side of a substrate (8);

Growing an active region (3) on the side of the N-type injection layer (2) facing away from the substrate (8);

growing a P-type injection layer (4) on one side of the active region (3) away from the N-type injection layer (2);

removing part of the material of the P-type injection layer (4) to form at least two grooves;

growing electrically isolated N-type material in at least two of said recesses to form at least two electrically isolated regions (5);

Manufacturing a forward electrode (6) at the position of the P-type injection layer (4) which is away from one side of the active region (3) and is opposite to the quantum well of the active region (3), and manufacturing a reverse electrode (7) at two sides of the forward electrode (6) in the horizontal direction at a certain distance;

And thinning the substrate (8) to manufacture a reference electrode (1), wherein the manufacturing mode of the reference electrode (1) is that metal is deposited and patterned on the back surface of the thinned substrate (8).

10. The method of fabricating an edge-emitting laser chip according to claim 9, wherein the step of growing an active region (3) on a side of the N-type implanted layer (2) facing away from the substrate (8) comprises:

sequentially growing an undoped waveguide layer (32), an optical gain layer (31) and the undoped waveguide layer (32) on one side of the N-type injection layer (2) away from the substrate (8);

-removing the undoped waveguide layer (32), the optical gain layer (31) and the undoped waveguide layer (32) of the first region;

growing an N-doped waveguide layer (33) in the first region;

Wherein the first region is at least a partial region of the forward electrode (6) outside the projection range of the active region (3).