CN119277795A - Random access memory structure and manufacturing method thereof - Google Patents
Random access memory structure and manufacturing method thereof Download PDFInfo
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- H10B—ELECTRONIC MEMORY DEVICES
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Abstract
本发明提供了一种随机存取存储器结构及其制作方法。该方法包括：基底，基底包括毗邻设置的阵列区和逻辑区，基底具有台阶结构，台阶结构具有对应阵列区的第一台阶面以及对应逻辑区的第二台阶面；第一导电通道，第一导电通道自第一台阶面延伸至阵列区中的第一金属连线层；第二导电通道，第二导电通道自第二台阶面延伸至逻辑区中的第二金属连线层；随机存取存储器单元，随机存取存储器单元设置于第一台阶面上且与第一导电通道接触设置；顶部金属层，顶部金属层至少与随机存取存储器单元远离第一导电通道的一侧接触设置。通过本申请，减少了光罩的数量，简化了工艺流程，从而大大降低了随机存取存储器结构的制作成本。
The present invention provides a random access memory structure and a manufacturing method thereof. The method comprises: a substrate, the substrate comprises an array area and a logic area arranged adjacent to each other, the substrate has a step structure, the step structure has a first step surface corresponding to the array area and a second step surface corresponding to the logic area; a first conductive channel, the first conductive channel extends from the first step surface to the first metal wiring layer in the array area; a second conductive channel, the second conductive channel extends from the second step surface to the second metal wiring layer in the logic area; a random access memory unit, the random access memory unit is arranged on the first step surface and is arranged in contact with the first conductive channel; a top metal layer, the top metal layer is arranged in contact with at least one side of the random access memory unit away from the first conductive channel. Through the present application, the number of masks is reduced, the process flow is simplified, and thus the manufacturing cost of the random access memory structure is greatly reduced.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a random access memory structure and a method for manufacturing the same.
Background
MRAM memory cells MTJ are typically composed of three basic cells of ferromagnetic layers, an insulating tunneling layer, and a pinned layer. When the magnetic moment directions of the ferromagnetic layer and the fixed layer are opposite, the memory device is in a high-resistance state Rap, when the magnetic moment directions of the two layers are the same, the memory device is in a low-resistance state Rp, and information '1' and '0' are stored through the distinction of the high-resistance state and the low-resistance state. As a novel memory, MRAM has great advantages in terms of read-write speed and device reliability compared with traditional Flash storage. However, the existing technology for restricting the development of MRAM has the major drawbacks of low array density and high manufacturing cost.
There is therefore a need for a further reduction in manufacturing costs by optimizing the process integration scheme, reducing the number of process steps.
Disclosure of Invention
The present invention provides a random access memory structure and a method for fabricating the same, which solves the problem of high fabrication cost of forming the random access memory structure in the prior art.
In order to achieve the above object, according to one aspect of the present invention, there is provided a random access memory structure including a substrate including an array region and a logic region disposed adjacently, the substrate having a step structure having a first step surface corresponding to the array region and a second step surface corresponding to the logic region, a first conductive via extending from the first step surface to a first metal wiring layer in the array region, a second conductive via extending from the second step surface to a second metal wiring layer in the logic region, a random access memory cell disposed on the first step surface and in contact with the first conductive via, and a top metal layer disposed in contact with at least a side of the random access memory cell remote from the first conductive via.
Further, the method includes the step of disposing a top metal layer in contact with a side of the random access memory cell away from the first conductive via and the second conductive via, respectively.
Further, a barrier layer is provided in contact with the random access memory cell and the first conductive via, respectively.
Further, the random access memory cell includes any one of a magnetic random access memory cell, a phase change random access memory cell, and a resistive random access memory cell.
In order to achieve the above object, according to one aspect of the present invention, there is provided a method for manufacturing a random access memory structure, comprising providing a substrate including an array region and a logic region disposed adjacently, wherein the array region has a first conductive channel therein, the logic region has a second conductive channel therein, the first conductive channel and the second conductive channel are formed in the same etching step and the same filling step, etching at least a portion of the substrate corresponding to the array region to form a step structure in the substrate, the step structure having a first step surface corresponding to the array region and a second step surface corresponding to the logic region, and the first conductive channel extends from the first step surface to a first metal wiring layer of the array region, the second conductive channel extends from the second step surface to a second metal wiring layer of the logic region, forming a random access memory cell on the first step surface, the random access memory cell being disposed in contact with the first conductive channel, and forming a first metal layer disposed in contact with at least a side of the random access memory cell away from the first conductive channel.
The step structure forming method comprises the steps of forming a step structure on a substrate, forming a first mask plate on the substrate, forming a hollow area on the first mask plate, forming the hollow area at least corresponding to the array area, and etching the substrate corresponding to the hollow area to remove part of the substrate corresponding to the array area to form the step structure.
Further, forming a second metal layer in contact with a side of the random access memory cell remote from the first conductive via and the second conductive via, respectively.
Further, the step of forming the random access memory unit comprises the steps of forming a random access memory unit film layer on at least the first step surface, arranging a second mask plate on the random access memory unit film layer, wherein the second mask plate is provided with a preset pattern, at least exposing the rest part except the corresponding preset pattern in the random access memory unit film layer, and etching the random access memory unit film layer according to the preset pattern sequence to remove the exposed random access memory unit film layer so as to form the random access memory unit.
Further, after the step of forming the step structure and before the step of forming the random access memory cell, the manufacturing method further comprises the steps of forming a barrier material layer on the first step surface and the second step surface, forming a random access memory cell film layer on one side of the barrier material layer far away from the first conductive channel in the step of forming the random access memory cell, and sequentially etching the random access memory cell film layer to form the random access memory cell and the barrier layer.
Further, after the step of forming the barrier material layer, the step of forming a random access memory cell film layer before the step of forming the random access memory cell and the barrier layer includes forming a lower electrode material layer covering the barrier material layer, removing a portion of the lower electrode material layer by chemical mechanical polishing so that the remaining lower electrode material layer located in the array region has a first thickness in a first direction, thinning the remaining lower electrode material layer located in the array region so that the lower electrode material layer after thinning has a second thickness in the first direction, the first thickness being greater than the second thickness, forming an intermediate material layer covering at least the lower electrode material layer after thinning and an upper electrode material layer covering the intermediate material layer, and forming the random access memory cell film layer after thinning the lower electrode material layer, the intermediate material layer, and the upper electrode material layer.
By applying the technical scheme of the application, a random access memory structure is provided. Since the substrate of the random access memory structure comprises an array region and a logic region which are adjacently arranged, and the substrate is provided with a step structure, the step structure can be provided with a first step surface corresponding to the array region and a second step surface corresponding to the logic region, further, since the substrate is also provided with a first conductive channel and a second conductive channel, wherein the first conductive channel is positioned in the array region, the second conductive channel is positioned in the logic region, the first conductive channel and the second conductive channel are formed in the same etching step and the same filling step, and the substrate is correspondingly provided with a first metal connecting line layer positioned in the array region and a second metal connecting line layer positioned in the logic region, the first conductive channel extends from the first step surface to the first metal connecting line layer in the array region, and the second conductive channel extends from the second step surface to the second metal connecting line layer in the logic region, so that a random access memory unit which is arranged in contact with the first conductive channel and at least contacts with the top metal connecting line layer of the random access memory unit can be arranged on the first step surface. Namely, the application can realize that the first conductive channel and the second conductive channel which are positioned in the random access memory unit are formed in the same step, thereby reducing the number of etching photomasks and greatly reducing the manufacturing cost of the random access memory structure compared with the prior art that the bottom through hole corresponding to the first conductive channel and the top through hole corresponding to the second conductive channel are required to be formed through different etching steps.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
FIG. 1 is a schematic cross-sectional view of a random access memory structure according to an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of a substrate provided in a random access memory structure according to an embodiment of the invention;
FIG. 3 is a schematic cross-sectional view showing the formation of a step structure in the substrate shown in FIG. 2;
FIG. 4 is a schematic cross-sectional view showing the formation of a lower electrode material layer, a random access memory cell film layer, and an upper electrode material layer on the structure shown in FIG. 3;
FIG. 5 is a schematic cross-sectional view showing the structure of FIG. 4 being etched to form a random access memory cell and to form a protective layer;
FIG. 6 is a schematic diagram showing a cross-sectional structure of an insulating dielectric layer formed on the structure shown in FIG. 5;
FIG. 7 shows a schematic cross-sectional structure of forming a top metal layer;
Fig. 8 is a schematic view showing a cross-sectional structure of forming a barrier material layer and a lower electrode material layer on the structure shown in fig. 3;
FIG. 9 is a schematic cross-sectional view showing the structure of the lower electrode material layer in the structure shown in FIG. 8 after chemical mechanical polishing;
fig. 10 is a schematic view showing a cross-sectional structure after further etching back the lower electrode material layer on the basis of the structure shown in fig. 9;
FIG. 11 is a schematic cross-sectional view showing the formation of a layer of a random access memory cell and a layer of upper electrode material on the structure shown in FIG. 10;
FIG. 12 is a schematic cross-sectional view showing the structure of FIG. 11 being etched to form a random access memory cell and to form a protective layer;
fig. 13 is a schematic cross-sectional view showing the formation of an insulating dielectric layer on the structure shown in fig. 12.
Wherein the above figures include the following reference numerals:
10. The semiconductor device comprises a substrate, 20 parts of a first metal connecting layer, 30 parts of a second metal connecting layer, 40 parts of a first conductive channel, 50 parts of a second conductive channel, 51 parts of a random access memory unit film layer, 60 parts of a lower electrode material layer, 70 parts of an intermediate material layer, 80 parts of an upper electrode material layer, 90 parts of a random access memory unit, 100 parts of a protective layer, 110 parts of an insulating medium layer, 120 parts of a top metal layer, 130 parts of a blocking material layer.
Detailed Description
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As mentioned in the background art, the prior art, which restricts the development of MRAM, has the major drawbacks of low array density and high manufacturing cost, and in order to solve the above technical problems, the present inventors provide a random access memory structure and a manufacturing method thereof.
In some alternative embodiments, a random access memory structure is provided, the random access memory structure comprising a substrate comprising an array region and a logic region disposed adjacent to each other, the substrate having a step structure with a first step surface corresponding to the array region and a second step surface corresponding to the logic region, a first conductive via extending from the first step surface to a first metal wiring layer in the array region, a second conductive via extending from the second step surface to a second metal wiring layer in the logic region, a random access memory cell disposed on the first step surface and in contact with the first conductive via, and a top metal layer disposed in contact with at least a side of the random access memory cell remote from the first conductive via.
The first direction is a direction perpendicular to the first step surface, the first conductive channel has a first height in the first direction, the second conductive channel has a second height in the first direction, and the first height is smaller than the second height, optionally, a height difference between the first height and the second height may be 50 nm-200 nm. Further, the material of the first conductive path and the second conductive path may be any one or more selected independently from titanium (Ti) tungsten (W), tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN).
It should be noted that the first conductive path and the second conductive path are formed in the same etching step and the same filling step, and then the step structure is etched.
Further, the above-mentioned random access memory structure further includes a protective layer and an insulating dielectric layer, where the protective layer is disposed on the periphery of the random access memory unit and the first step surface, that is, the above-mentioned magnetoresistive random access memory unit has an exposed surface on a side far away from the first conductive channel, and the dielectric insulating layer is disposed on a side far away from the substrate of the protective layer, so that in a process that a top metal layer is formed on a side far away from the first conductive channel of the above-mentioned magnetoresistive random access memory unit, the above-mentioned top metal layer can be electrically connected with the exposed surface of the magnetoresistive random access memory unit, and by disposing the above-mentioned insulating dielectric layer, the sum of thicknesses of the above-mentioned protective layer and insulating dielectric layer is consistent with the thickness of the above-mentioned magnetoresistive random access memory unit in a direction perpendicular to the first step surface, so that at least a top metal layer with a uniform thickness can be formed in an array region corresponding to the first step surface.
According to the application, the substrate of the random access memory structure comprises an array area and a logic area which are adjacently arranged, and the substrate is provided with a step structure, so that the step structure can be provided with a first step surface corresponding to the array area and a second step surface corresponding to the logic area, further, as the substrate is also provided with a first conductive channel and a second conductive channel, wherein the first conductive channel is positioned in the array area, the second conductive channel is positioned in the logic area, the first conductive channel and the second conductive channel are formed in the same etching step and the same filling step, and the substrate is correspondingly provided with a first metal connecting layer positioned in the array area and a second metal connecting layer positioned in the logic area, therefore, under the condition that the array area and the logic area correspond to the step structure, the first conductive channel extends from the first step surface to the first metal connecting layer in the array area, and the second conductive channel extends from the second step surface to the second metal connecting layer in the logic area, and in a first direction perpendicular to the first step surface, so that the first conductive channel has a first metal connecting layer in the first direction, the first conductive channel has a first metal connecting layer in the first direction and a first metal connecting with the first random access cell is arranged at least a height. That is, by the above-mentioned random access memory structure of the present application, the first conductive channel and the second conductive channel located in the random access memory unit can be formed in the same step, so that compared with the prior art that the bottom via corresponding to the first conductive channel and the top via corresponding to the second conductive channel need to be formed by different etching steps, the number of photomasks is reduced, and the manufacturing cost of the random access memory structure is greatly reduced.
In some alternative embodiments, the random access memory structure further includes a top metal layer disposed in contact with a side of the random access memory cell remote from the first conductive via and the second conductive via, respectively.
Specifically, in an alternative embodiment, the random access memory structure includes a substrate having a step structure, a first conductive via in an array region of the substrate and a second conductive via in a logic region of the substrate, a random access memory cell in contact with the first conductive via, and a top metal layer in contact with the random access memory cell.
Specifically, in another alternative embodiment, the top metal layer in the random access memory structure is disposed not only in contact with the random access memory cell but also in contact with the second conductive channel in the logic region. With this embodiment, the array region and the logic region in the above-described random access memory structure are electrically connected.
In some alternative embodiments, the random access memory structure further includes a barrier layer disposed in contact with the random access memory cell and the first conductive via, respectively.
Specifically, in an alternative embodiment, the random access memory structure includes a substrate having a step structure, a first conductive via in an array region of the substrate and a second conductive via in a logic region of the substrate, a barrier layer contacting the first conductive via, a random access memory cell contacting the barrier layer, and a top metal layer contacting at least the random access memory cell. In the embodiment, the barrier layer is arranged between the first conductive channel and the random access memory unit, so that the quality of each film layer of the formed random access memory unit is better.
Specifically, in another alternative embodiment, the random access memory structure has not only a barrier layer disposed in contact with the first conductive via and the random access memory cell, respectively, but also a top metal layer disposed in contact with the upper electrode of the random access memory cell and the second conductive via in the logic region, respectively. In this embodiment, by providing the barrier layer, the quality of each film layer of the formed random access memory unit is better, and the top metal layer is respectively in contact with the upper electrode and the second conductive channel, so that the electrical connection between the array area and the logic area in the random access memory structure is realized.
In some alternative embodiments, the random access memory cell includes any one of a magnetic random access memory cell, a phase change random access memory cell, and a resistive random access memory cell.
Specifically, any one of the magnetic random access memory cell, the phase change random access memory cell and the resistive random access memory cell can be replaced by the random access memory cell according to any one of the embodiments of the present application, so as to obtain random access memory structures under different requirements.
Wherein, in the case that the random access memory cell is the magnetic random access memory cell, the random access memory cell may include a lower electrode, a magnetic tunnel junction, and an upper electrode sequentially stacked along a side facing away from the substrate, wherein the magnetic tunnel junction includes a free magnetic layer, a tunnel gate layer, and a fixed magnetic layer sequentially stacked, and the lower electrode is disposed in contact with the first conductive path, and the material of the tunnel gate layer may include, but is not limited to, magnesium oxide or aluminum oxide. In the structure, the polarization direction of the magnetic tunnel junction can be driven to change by an external magnetic field or an electric field, so that the free magnetic layer and the fixed magnetic layer of the magnetic tunnel junction are in a parallel state and an anti-parallel state, and The Magnetic Resistances (TMR) corresponding to the parallel state and the anti-parallel state are greatly different, so that the low resistance and the high resistance can be used as two different states of 0 and 1.
In the case where the random access memory cell is the phase change random access memory cell, the phase change random access memory cell may include a lower electrode, a phase change layer, and an upper electrode sequentially stacked along a side facing away from a substrate, wherein the lower electrode is disposed in contact with the first conductive path, and the material of the phase change layer may include, but is not limited to, chalcogenides (represented by intel), and germanium, antimony, and tellurium-containing synthetic materials (GST), such as Ge2Sb2Te5 (represented by an artificial semiconductor), and the like. In this structure, since the material corresponding to the phase change layer can be transformed between the crystallized (low resistance state) and the amorphous (high resistance state), the difference in conductivity after transformation between the crystalline and amorphous states of the material corresponding to the phase change layer can be used to store information.
Wherein, in the case that the random access memory cell is the resistive random access memory cell, the resistive random access memory cell may include a lower electrode, a thin dielectric layer, and an upper electrode sequentially stacked along a side facing away from a substrate, wherein the thin dielectric layer serves as an ion transport and storage medium, wherein the thin dielectric layer may include a binary Transition Metal Oxide (TMO), a perovskite-type compound, a solid electrolyte, an organic dielectric material, and the like, wherein the binary transition metal oxide may include, but is not limited to, any one of nickel oxide (NiO), titanium oxide (TiO 2), and zinc oxide (ZnO). In this structure, the high-low resistance state of the structure can be detected by forming and breaking filaments (conductive filaments formed by ion transport between upper and lower electrodes) in a thin dielectric layer.
In addition, in some alternative embodiments, in order to align the random access memory unit and the first conductive via, an alignment mark is formed in the substrate near one side of the random access memory unit, and the alignment mark is typically disposed at the periphery of the chip.
Exemplary embodiments of a method of fabricating a random access memory structure provided in accordance with the present application will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be appreciated that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
In some alternative embodiments, as shown in FIG. 1, the inventor provides a method for fabricating a random access memory structure, the method comprising providing a substrate 10, the substrate 10 comprising an array region and a logic region adjacently disposed, the array region having a first conductive via 40 therein and the logic region having a second conductive via 50 therein, etching at least a portion of the substrate 10 corresponding to the array region to form a step structure in the substrate 10, the step structure having a first step surface corresponding to the array region and a second step surface corresponding to the logic region, the first conductive via 40 extending from the first step surface to a first metal wiring layer 20 of the array region, the second conductive via 50 extending from the second step surface to a second metal wiring layer 30 of the logic region, forming a random access memory cell 90 on the first step surface, the random access memory cell 90 being disposed in contact with the first conductive via 40, and forming a top metal layer 120 disposed in contact with at least a side of the random access memory cell 90 remote from the first conductive via 40. Optionally, a barrier material layer 130 may be further included between the random access memory cell 90 and the first conductive via 40. Optionally, the above-mentioned random access memory structure further includes a protection layer 100, where the protection layer 100 covers the sidewalls and the first step surface of the random access memory unit 90, and a dotted line in the figure may be understood as a boundary line between the array area and the logic area.
Specifically, in the above embodiment, as shown in fig. 2, a metal wiring layer is further disposed in the substrate 10, where the metal wiring layer includes a first metal wiring layer 20 in an array area and a second metal wiring layer 30 in a logic area, and further, the array area has a first conductive via 40 contacting the first metal wiring layer 20, and the logic area has a second conductive via 50 contacting the second metal wiring layer 30. After etching the portion of the substrate 10 corresponding to the array region in the substrate 10, a step structure is formed in the substrate 10, so that the array region has a first step surface corresponding to the step structure, the logic region has a second step surface corresponding to the step structure, so that the first conductive via 40 extends from the first step surface to the first metal wiring layer 20 in the array region, and the second conductive via 50 extends from the second step surface to the second metal wiring layer 30 in the logic region, as shown in fig. 3.
It should be noted that the first conductive via 40 and the second conductive via 50 described above and shown in fig. 2 are formed in the same etching step and the same filling step. Specifically, the first substrate 10 includes an array region having a first metal interconnect layer 20 and a logic region having a second metal interconnect layer 30. In order to form the first conductive via 40 and the second conductive via 50, a photolithography process is first used to provide a photomask on the surface of the substrate 10 to form a first pattern on the surface of the substrate 10 corresponding to the array region, a second pattern on the surface of the substrate 10 corresponding to the logic region, and then etching is performed according to the first pattern and the second pattern to form a first via hole extending from the surface of the substrate 10 to the first metal wiring layer 20 in the substrate 10 corresponding to the array region, and a second via hole extending from the surface of the substrate 10 to the second metal wiring layer 30 in the substrate 10 corresponding to the logic region. Then, a metal material is deposited on the surface of the substrate 10 through a deposition process, and at least the metal material fills the first and second through holes, and further, the metal material outside the first and second through holes may be removed by a chemical mechanical polishing process to form the first and second conductive vias 40 and 50. Further, at least a portion of the substrate corresponding to the array region is etched to form a step structure in the substrate as shown in fig. 3.
By the above manufacturing method, the first conductive via 40 is used as a bottom conductive via in the random access memory structure, the second conductive via 50 is used as a top conductive via in the random access memory structure, and the bottom conductive via and the top conductive via are formed by etching at least twice in different process steps, which results in higher manufacturing cost, while the present application forms the first conductive via 40 and the second conductive via 50 in the same process step, and only one etching is needed to achieve the purpose of using the first conductive via 40 as a bottom conductive via of the random access memory structure, and the second conductive via 50 as a top conductive via of the random access memory structure, thereby forming the random access memory cell 90 disposed in contact with the first conductive via 40 on the first conductive via 40, and forming the top metal layer 120 disposed at least in contact with the random access memory cell 90. Therefore, the application can reduce the etching times and the number of photomasks corresponding to etching, thereby greatly reducing the manufacturing cost of the random access memory structure.
In some alternative embodiments, as shown in fig. 3, the step of forming the step structure includes providing a first mask plate on the substrate 10, where the first mask plate has a hollowed-out area, and the hollowed-out area is at least corresponding to the array area, and etching the substrate corresponding to the hollowed-out area to remove a portion of the substrate 10 corresponding to the array area, so as to form the step structure.
Specifically, in the above embodiment, in order to make the first conductive via 40 be the bottom conductive via in the random access memory structure and the second conductive via 50 be the top conductive via in the random access memory structure, by disposing the above-described first mask plate and etching, the step structure is first formed in the array region and the logic region so that the first conductive via 40 has a first height in the direction perpendicular to the first step surface, the second conductive via 50 has a second height, and the first height is smaller than the second height, so that the random access memory cell can be disposed on the first conductive via 40 having the first height, and the first conductive via 40 having the first height can be the bottom conductive via of the random access memory structure.
Optionally, in order to align the formed random access memory unit with the first conductive channel 40, when the first mask is disposed, the hollow area in the first mask includes a first hollow area and a second hollow area, where the first hollow area corresponds to the array area and is used to form the step structure, and the second hollow area corresponds to the substrate 10 located at the periphery of the array area and the logic area and is used to form the alignment mark. In this step, the etching of the step structure and the etching of the alignment mark can be simultaneously implemented by using the same mask, so that the bottom conductive channel (the first conductive channel 40), the top conductive channel (the second conductive channel 50) and the alignment mark of the random access memory structure are simultaneously formed in the same process step, thereby further simplifying the process flow and reducing the manufacturing cost of the random access memory structure.
Further, in order to electrically connect the array region and the logic region of the random access memory structure, after the step of forming the random access memory cell 90 on the first step surface on the basis of forming the top metal layer 120 disposed in contact with the side of the random access memory cell away from the first conductive via 40, the method further includes forming the top metal layer 120 disposed in contact with the side of the random access memory cell away from the first conductive via and the second conductive via, respectively, as shown in fig. 1.
In some alternative embodiments, as shown in fig. 4 and 5, the step of forming the random access memory unit includes forming a random access memory unit film 51 on at least the first step surface, as shown in fig. 4, disposing a second mask plate on the random access memory unit film 51, the second mask plate having a predetermined pattern and exposing at least a remaining portion of the random access memory unit film 51 except for the corresponding predetermined pattern, and sequentially etching the random access memory unit film 51 according to the predetermined pattern to remove the exposed random access memory unit film 51, thereby forming a random access memory unit 90, as shown in fig. 5.
In the above embodiment, as shown in fig. 4, in order to form the random access memory structure on the first conductive channel 40, the random access memory cell film 51 may be formed at least on the first step surface, where the random access memory cell film 51 may include the lower electrode material layer 60, the intermediate material layer 70, and the upper electrode material layer 80 that are stacked, and then by providing the second mask plate with the corresponding pattern (preset pattern) of the random access memory cell, the random access memory cell film 51 corresponding to the preset pattern on the first conductive channel 40 may be retained when etching is performed according to the second mask plate, and the remaining random access memory cell film 51 on the first step surface may be removed, so as to form the above random access memory cell 90, and optionally, after forming the above random access memory cell 90, a protective layer 100 may be formed on a side of the random access memory cell 90 away from the substrate 10, as shown in fig. 5. Further, as shown in fig. 6, an insulating dielectric layer 110 is formed on a side of the protective layer 100 away from the substrate 10 shown in fig. 5, and further, a part of the insulating dielectric layer 110 is removed by chemical mechanical polishing to form a flat upper surface, and as shown in fig. 7, a top metal layer 120 is formed on a side of the insulating dielectric layer 110 away from the protective layer 100.
Optionally, the ram cell layer 51 may also be disposed on the first step surface and the second step surface, and after etching according to the second mask, only the ram cell layer 51 corresponding to the preset pattern on the first conductive path 40 is still remained, and the remaining ram cell layer 51 on the first step surface and the second step surface is removed, so as to form the ram cell 90.
In some alternative embodiments, in order to form a better-quality random access memory cell on the first conductive channel 40, after the step of forming the step structure and before the step of forming the random access memory cell, the manufacturing method further comprises forming a barrier material layer 130 on the first step surface and the second step surface, as shown in fig. 8, and in the step of forming the random access memory cell, forming a random access memory cell film layer on a side of the barrier material layer 130 away from the first conductive channel 40, and sequentially etching the random access memory cell film layer to form the random access memory cell and the barrier layer.
Optionally, the barrier material layer 130 is a conductive material layer, and the material of the barrier material layer 130 may be one or more selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN).
In some alternative embodiments, as shown in fig. 8-11, after the step of forming the barrier material layer 130, and before the step of forming the random access memory cell and barrier layer, the step of forming the random access memory cell film layer includes forming a lower electrode material layer 60 that covers the barrier material layer 130, as shown in fig. 8, removing portions of the lower electrode material layer 60 using chemical mechanical polishing such that the remaining lower electrode material layer 60 located in the array region has a first thickness in a first direction, as shown in fig. 9, thinning the remaining lower electrode material layer 60 located in the array region such that the lower electrode material layer 60 after thinning has a second thickness in the first direction, the first thickness being greater than the second thickness, as shown in fig. 10, forming an intermediate material layer 70 that covers at least the lower electrode material layer 60 after thinning, and an upper electrode material layer 80 that covers the intermediate material layer 70, the lower electrode material layer 60, the intermediate material layer 70, and the upper electrode material layer 80 after thinning forming the random access memory cell film layer 51, as shown in fig. 11.
Alternatively, the material of the lower electrode material layer 60 may be selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). It should be noted that the material of the barrier material layer 130 is different from the material of the lower electrode material layer 60 in the random access memory cell.
Specifically, in the case where the random access memory cell is a magnetic random access memory cell, the intermediate material layer 70 is a material layer corresponding to a magnetic tunnel junction, that is, the intermediate material layer 70 is a material layer corresponding to a free magnetic layer, a material layer corresponding to a tunnel gate layer, and a material layer corresponding to a fixed magnetic layer, which are sequentially stacked, in the case where the random access memory cell is a phase change random access memory cell, the intermediate material layer 70 is a material layer corresponding to a phase change layer, and in the case where the random access memory cell is a resistive random access memory cell, the intermediate material layer 70 is a material layer corresponding to a thin dielectric layer.
In the above embodiment, as shown in fig. 9, in order to facilitate the etching process of the bottom electrode material, after the bottom electrode material layer 60 is formed, the bottom electrode material layer 60 is first subjected to planarization treatment by chemical mechanical polishing to make the bottom electrode material layer 60 have a flat surface, in particular, in order to facilitate the chemical mechanical polishing process to control the thickness of the bottom electrode material layer 60, the planarization process removes the bottom electrode material layer 60 located in the logic region, so that the barrier material layer 130 located in the logic region is exposed, and the bottom electrode material layer 60 located in the array region is left, further, after the step of chemical mechanical polishing, the bottom electrode material layer 60 located in the array region is thinned by etching, as shown in fig. 10, so that the thinned bottom electrode material layer 60 is used to form the bottom electrode of the magnetoresistive random access memory cell, in particular, after the chemical mechanical polishing process is adopted to remove a part of the bottom electrode material layer 60, if a part of the bottom electrode material layer 60 is still reserved on the barrier material layer 130 located in the logic region, then the remaining bottom electrode material layer 130 located in the logic region is removed in the thinning process, so that the bottom electrode material layer 60 located in the logic region is sequentially removed, and the middle electrode material layer 80 is sequentially stacked, as shown in fig. 10, and the middle electrode layer 80 is sequentially deposited, and the bottom electrode material layer 60 is located in the middle layer 80 is sequentially stacked, and the layer is stacked, as shown in fig. layer 80.
Alternatively, after the upper electrode material layer 80 is formed, a hard mask layer may be further formed on the upper electrode material layer 80 and used as a sacrificial layer for etching the formation of the random access memory cell film layer 51, so as to remove the hard mask layer during the formation of the random access memory cell film layer 51.
Further, in some embodiments, after the barrier material layer and the bottom electrode material layer are first deposited, and then the film layers corresponding to the random access memory cells are formed on the bottom electrode material layer after the etching back, the film layers corresponding to the random access memory cells can have a smoother surface, thereby being beneficial to the formation and performance improvement of the subsequent random access memory structure.
Further, the random access memory cell film layer 51 is etched to form the random access memory cell 90, the protective layer 100 is formed to cover the first step surface, the random access memory cell 90 and the second step surface, so that the protective layer 100 covers the exposed surface after the random access memory cell 90 is formed, as shown in fig. 12, the insulating dielectric layer 110 is formed on the protective layer 100 in the step of forming the top metal layer 120 after the random access memory cell 90 is etched, as shown in fig. 13, further, the insulating dielectric layer 110 and the protective layer 100 are sequentially etched so that the surface of the random access memory cell 90 on the side away from the first conductive channel 40 is exposed, and the second conductive channel 50 on the second step surface is exposed, optionally, the process may be obtained using a chemical mechanical polishing process, then the top metal layer 120 is formed on the exposed surface of the random access memory cell 90 on the side away from the first conductive channel 40, or further, the top metal layer 120 is formed on the exposed surface of the random access memory cell 90 on the side away from the first conductive channel 40 and the exposed second conductive channel 50, as shown in fig. 1.
From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:
According to the application, the substrate of the random access memory structure comprises an array area and a logic area which are adjacently arranged, and the substrate is provided with a step structure, so that the step structure can be provided with a first step surface corresponding to the array area and a second step surface corresponding to the logic area, further, the substrate is provided with a first conductive channel and a second conductive channel, wherein the first conductive channel is positioned in the array area, the second conductive channel is positioned in the logic area, and the substrate is correspondingly provided with a first metal connecting layer positioned in the array area and a second metal connecting layer positioned in the logic area, therefore, under the condition that the array area and the logic area correspond to the step structure, the first conductive channel extends from the first step surface to the first metal connecting layer in the array area, the second conductive channel extends from the second step surface to the second metal connecting layer in the logic area, and thus, in a first direction perpendicular to the first step surface, the first conductive channel is provided with a first height in the first direction, the second conductive channel is provided with a second height in the first direction, and the first conductive channel is in contact with at least one first random access cell. That is, by the random access memory structure of the present application, the first conductive channel and the second conductive channel located in the random access memory unit can be formed in the same step, so that compared with the prior art that the bottom through hole corresponding to the first conductive channel and the top through hole corresponding to the second conductive channel are required to be formed through different etching steps, the number of etching masks is reduced, and the manufacturing cost of the random access memory structure is greatly reduced.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
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