CN119293672A

CN119293672A - VCSEL chip test data processing method and device

Info

Publication number: CN119293672A
Application number: CN202411822570.9A
Authority: CN
Inventors: 刘点昊; 陈浩
Original assignee: Zhejiang Laoying Semiconductor Technology Co ltd
Current assignee: Zhejiang Laoying Semiconductor Technology Co ltd
Priority date: 2024-12-11
Filing date: 2024-12-11
Publication date: 2025-01-10
Anticipated expiration: 2044-12-11
Also published as: CN119293672B

Abstract

The application relates to a method and a device for processing test data of a VCSEL chip. The method comprises the steps of constructing an initial chip multitasking fusion model, obtaining various different types of actual measurement data which directly or indirectly characterize the high-speed performance of the VCSEL chip, importing the various different types of actual measurement data into the initial chip multitasking fusion model to analyze linear or nonlinear relations among the actual measurement data, continuously and iteratively updating the initial chip multitasking fusion model to obtain a trained chip multitasking fusion model, obtaining partial performance test data of the VCSEL chip to be detected, and inputting the partial performance test data into the trained chip multitasking fusion model. The method can output the target performance prediction data of the VCSEL chip to be detected according to the linear relation among the analyzed partial performance test data or output the performance grade of the chip to be detected according to the nonlinear relation among the analyzed partial performance test data with high efficiency and accuracy.

Description

Method and device for processing test data of VCSEL chip

Technical Field

The present application relates to the field of data processing technology, and in particular, to a method for processing test data of a VCSEL chip, a method for predicting chip performance, an apparatus, a computer device, a computer readable storage medium, and a computer program product.

Background

VCSEL chips, vertical cavity surface emitting laser chips, are a special type of semiconductor laser. To obtain the performance of a VCSEL chip, the chip is typically tested to obtain test data for the chip at multiple levels.

If the VCSEL chip is to be tested comprehensively for performance, the chip needs to be tested correspondingly at each level, which results in complex testing process, long time consumption and high cost.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a method, an apparatus, a computer device, a computer-readable storage medium, and a computer program product for processing test data of a VCSEL chip capable of efficiently and accurately obtaining performance-related data of the chip.

In a first aspect, the present application provides a method for processing test data of a VCSEL chip, including:

constructing an initial chip multitasking fusion model;

acquiring a plurality of different types of measured data which directly or indirectly characterize the high-speed performance of the reference VCSEL chip;

Importing the various different types of measured data into the initial chip multi-task fusion model to analyze linear or nonlinear relations among the measured data, and continuously iterating and updating the initial chip performance multi-task fusion model to obtain a trained chip multi-task fusion model;

The method comprises the steps of obtaining partial performance test data of a VCSEL chip to be detected, inputting the partial performance test data into a trained chip multitasking fusion model, and outputting target performance prediction data of the VCSEL chip to be detected according to the linear relation between the analyzed partial performance test data or outputting the performance grade of the VCSEL chip to be detected according to the nonlinear relation between the analyzed partial performance test data by the trained chip multitasking fusion model.

In a second aspect, the present application also provides a test data processing apparatus for a VCSEL chip, including:

the construction module is used for constructing an initial chip multitasking fusion model;

the acquisition module is used for acquiring various different types of measured data which directly or indirectly characterize the high-speed performance of the reference chip;

The training module is used for importing the various different types of measured data into the initial chip multi-task fusion model so as to analyze the linear or nonlinear relation among the measured data, and continuously iterating and updating the initial chip performance multi-task fusion model to obtain a trained chip multi-task fusion model;

The system comprises a prediction module, a trained chip multitasking fusion model, a target performance prediction module and a non-linear relation analysis module, wherein the prediction module is used for acquiring partial performance test data of a VCSEL chip to be detected, inputting the partial performance test data into the trained chip multitasking fusion model, and outputting the target performance prediction data of the VCSEL chip to be detected according to the linear relation between the analyzed partial performance test data or outputting the performance grade of the VCSEL chip to be detected according to the non-linear relation between the analyzed partial performance test data.

In a third aspect, the present application also provides a computer device comprising a memory storing a computer program and a processor implementing the steps described in the above method when the processor executes the computer program.

In a fourth aspect, the application also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps described by the above method.

In a fifth aspect, the application also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps described in the above method.

According to the method, the device, the computer equipment, the computer readable storage medium and the computer program product for processing the test data of the VCSEL chip, the initial chip multitasking fusion model is constructed, various different types of actual measurement data of the VCSEL chip are obtained, the actual measurement data are input into the initial chip multitasking fusion model to analyze linear or nonlinear relations among the actual measurement data, and the initial chip performance multitasking fusion model is continuously and iteratively updated, so that the trained chip multitasking fusion model can be obtained by processing the test data of the chip, and the obtained trained chip multitasking fusion model can analyze the linear relations or nonlinear relations of the performance test data input into the model to respectively obtain target performance prediction data of the chip or performance grade of the chip, so that the time for testing the performance related data of the chip can be greatly reduced, the efficiency for obtaining the performance related data of the VCSEL chip is improved, the performance related data of the chip is obtained efficiently and accurately, and the performance of the chip is comprehensively evaluated.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are needed in the description of the embodiments of the present application or the related technologies will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other related drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a flow diagram of a method of processing test data for a VCSEL chip in one embodiment;

FIG. 2 is a flow chart of the correlation steps between DC data and high-speed data in one embodiment;

FIG. 3 is a schematic diagram of a chip multitasking fusion model in one embodiment;

FIG. 4 is a flow diagram of the steps for obtaining a correlation between chip data and chip level in one embodiment;

FIG. 5 is a schematic diagram of a chip multitasking fusion model according to another embodiment;

FIG. 6 is a block diagram of a test data processing device of a VCSEL chip in one embodiment;

fig. 7 is an internal structural diagram of a computer device in one embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

In an exemplary embodiment, as shown in fig. 1, a method for processing test data of a VCSEL chip is provided, and this embodiment is exemplified by applying the method to a server, it will be understood that the method may also be applied to a terminal, and may also be applied to a system including a terminal and a server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps S102 to S108, wherein:

Step S102, an initial chip multi-task fusion model is constructed.

Wherein the initial chip multitasking fusion model is a model for training to get a model capable of handling many different types of tasks related to the performance of the chip. The plurality of different types of tasks may be, for example, tasks that predict certain performance data of the chip, or tasks that evaluate the performance level of the chip.

Illustratively, as shown in fig. 3, the initial chip multitasking fusion model includes an input layer, two fully connected layers, and an output layer connected in sequence. Between the two fully connected layers, a function is set to process the data in the model. I.e. the data output by the first fully connected layer is input to the function and the data output by the function is input to the second fully connected layer. The result output by the second full connection layer is input to the output layer to obtain a target output based on the output layer. In this model, the functions include a first function and a second function. The first function is used to capture the linear relationship of the data input into the model. The second function is used to capture the nonlinear relationship of the data input into the model. Therefore, the built initial chip multi-task fusion model can match corresponding functions to the data input into the model, so that corresponding target output is obtained. Optionally, the first function corresponds to target performance data of the predictive chip. And the second function correspondingly obtains the performance grade of the chip to be tested.

Step S104, obtaining a plurality of different types of measured data which directly or indirectly characterize the high-speed performance of the VCSEL chip.

Among them, the VCSEL chip is a vertical cavity Surface emitting laser (VERTICAL CAVITY Surface EMITTING LASER) chip, which is a special type of semiconductor laser chip. The lasing direction of the VCSEL chip is perpendicular to the surface of the chip. The measured data refers to performance data obtained by testing the VCSEL chip. The measured data of a VCSEL chip may include high-speed data and dc data obtained by testing the same, and may also include high-speed data and dc data obtained by testing the same, and performance levels obtained by analyzing the same.

In this embodiment, the actual measurement data directly characterizing the high-speed performance of the VCSEL chip is high-speed data. The actual measurement data indirectly representing the high-speed performance of the VCSEL chip is direct current data. The high-speed data includes at least one of 3dB bandwidth (f _3dB), relaxation oscillation frequency (f _r), relative Intensity Noise (RIN), and TDECQ values. The direct current data includes at least one of a threshold current (I _th), a series resistance (R _s), a light passing hole diameter (OA), a Skew Efficiency (SE), a center wavelength (Wp), and a spectral width (SPECTRAL WIDTH).

After an initial chip multitasking fusion model is constructed, the server may obtain various different types of measured data that directly or indirectly characterize the high-speed performance of the VCSEL chip, so that each task in the model may be trained using these measured data, thereby obtaining a trained chip multitasking fusion model.

Step S106, importing various different types of measured data into an initial chip multi-task fusion model to analyze linear or nonlinear relations among the measured data, and continuously and iteratively updating the initial chip multi-task fusion model to obtain a trained chip multi-task fusion model.

The trained chip multi-task fusion model refers to a trained chip multi-task fusion model. And each time a set of measured data is input to the model, the model adjusts parameters in the model based on the set of measured data so that a difference between an output result of the adjusted parameters after being combined with part of the set of measured data and the other part of the set of measured data is within a preset range. The above steps are then performed for each set of measured data input to the model. When the parameters in the model are not adjusted any more, the training of the chip multitasking fusion model is completed. It will be appreciated that training is performed separately for each task branch model in the model to obtain a trained each task branch model.

Optionally, the chip multitasking fusion model includes a data prediction branch model and a level analysis branch model. The data prediction branch model is used for predicting high-speed data based on direct current data. The level analysis branch model is used for analyzing the performance level of the chip based on the direct current data and the high-speed data of the chip.

Further, when the chip multitasking fusion model is selected as the data prediction branch model, the model can refer to formula (1) to learn, adjust and automatically iterate the relationship between the partial direct current data (threshold current I _th and aperture diameter OA) and the high-speed data (f _3dB、f_r).

(1)

D represents differential gain, I _th is threshold current, I _b is operating current, and f _r represents relaxation oscillation frequency.

When the operating current I _b is fixed, f _3dB can be expressed as the following formula (2):

(2)

Where OA represents the aperture diameter, in most cases (or in the scope of the patent discussion), f _r and f _3dB have a proportional relationship, the proportionality coefficient is denoted by a ₁, the aperture diameter OA affects the magnitude of the differential gain D in an approximately proportional manner, the simplified proportionality coefficient is denoted by a ₂, and in general, the smaller the aperture diameter OA, the larger the differential gain D.

Further, for other dc data, such as series resistance (R _s), skew Efficiency (SE), center wavelength (Wp), and the like, similar to parameters of high-speed performance (such as fr, f3dB, TDECQ), the model can be automatically tuned during training, and corresponding relation is built inside the model.

Alternatively, since the input and output of the data prediction branch model and the level analysis branch model are different from each other, after inputting a plurality of different types of measured data into the models, some processing may be performed on the input data so that the types of data input into each branch model are matched. For the data prediction branch model, the input measured data may be direct current data, and the output data may be high-speed data. For the hierarchical analysis branch model, the input measured data is direct current data and high-speed data, and the output data is the level of the chip, such as the level of the first level, the second level, and the like. Therefore, the processing of the input data can comprise dividing the measured data of different types corresponding to each chip into a direct current data class, a high-speed data class and a chip level class according to a preset major class. And then, the measured data belonging to the direct current data class and the high-speed data class are imported into a data prediction branch model to train the model, wherein the data of the direct current data class is used as model input data. The measured data of the high-speed data class is used as tag data for comparing with output data obtained by the model based on linear relation between input data to adjust model parameters. And importing the measured data belonging to the direct current data class and the high-speed data class into a level analysis branch model to train the model. The measured data of the direct current data class and the high-speed data class are used as model input data. The data of the chip class is used as label data of the model and is used for comparing with an output class obtained by the model based on a nonlinear relation between input data to adjust parameters of the class analysis branch model.

Step S108, partial performance test data of the VCSEL chip to be detected are obtained, the partial performance test data are input into a trained chip multitasking fusion model, and the trained chip multitasking fusion model outputs target performance prediction data of the VCSEL chip to be detected according to the linear relation among the analyzed partial performance test data or outputs the performance grade of the VCSEL chip to be detected according to the nonlinear relation among the analyzed partial performance test data.

After the trained chip multi-task fusion model is obtained, the chip multi-task fusion model can be used for analyzing the linear relation between data input to the model to obtain some performance data of the chip, or analyzing the nonlinear relation between data input to the model to obtain the performance grade of the chip.

Optionally, part of the performance test data of the VCSEL chip to be tested is acquired. Part of the performance test data may be performance data obtained by testing the VCSEL chip. For example, the partial performance test data may be performance data obtained by simply testing the VCSEL chip, such as some dc data. After inputting part of the performance test data into the trained chip multitasking fusion model, the model analyzes the linear relation between the part of the performance test data and outputs the target performance prediction data of the VCSEL chip to be detected. The target performance prediction data is not data obtained by testing the chip, but data predicted by a model. The target performance prediction data may be performance data obtained by performing complex testing on the VCSEL chip, such as data of 3dB bandwidth, TDECQ values, etc. The type of target performance prediction data may be determined based on measured data input during training. If the measured data input during training has only a 3dB bandwidth, the target performance prediction data only includes the 3dB bandwidth. If there is a 3dB bandwidth, TDECQ value for the measured data input during training, then the target performance prediction data may include a 3dB bandwidth, TDECQ value.

Optionally, part of the performance test data of the VCSEL chip to be tested is acquired. The partial performance test data may be performance data obtained by performing simple and complex tests on the VCSEL chip, such as at least one direct current data and at least one high speed data. After inputting these performance test data into the trained chip multitasking fusion model, if the model analysis inputs the type of data of the model including high-speed data, the model determines that a hierarchical analysis branch model is to be executed based on the type of data input. If the model analysis inputs the type of data to the model as belonging to the direct current data, the model determines that the data prediction branch model is to be executed based on the type of data input. At this time, the class analysis branch model obtains the class corresponding to the at least one direct current data and the at least one high-speed data by analyzing the nonlinear relationship between the at least one direct current data and the at least one high-speed data.

In this embodiment, an initial chip multitasking fusion model is constructed to obtain multiple different types of measured data of a VCSEL chip, the measured data are input into the initial chip multitasking fusion model to analyze linear or nonlinear relationships between the measured data, and the initial chip performance multitasking fusion model is continuously and iteratively updated, so that a trained chip multitasking fusion model can be obtained by processing test data of the chip, and the obtained trained chip multitasking fusion model can analyze the linear relationships or nonlinear relationships of performance test data input into the model to respectively obtain target performance prediction data of the chip or performance levels of the chip, so that time for testing performance related data of the chip can be greatly reduced, efficiency for obtaining performance related data of the VCSEL chip is improved, and performance related data of the chip can be obtained efficiently and accurately, and overall evaluation is performed on performance of the chip.

As mentioned above, the initial chip multitasking fusion model includes an input layer, two full-connection layers, and an output layer connected in sequence. The two fully connected layers are connected through a function. The function includes a first function (e.g., a linear function) or a second function (e.g., an activation function). Wherein the linear function is used for performing arithmetic operation on the data input by the previous full connection layer. The activation function is used for performing nonlinear operation on the data input by the previous full connection layer. When the activation function is a ReLU function, the activation function has an output equal to the input for a positive input and zero for a negative input.

The first full-connection layer is used for extracting features of measured data input to the initial chip multi-task fusion model, and the second full-connection layer is used for receiving features of the measured data after function processing and performing decision boundary learning based on the features. In the first fully connected layer, each measured data is connected to each neuron of the layer and linearly transformed by the weight and bias of each neuron, respectively. And extracting the characteristics of the measured data input to the initial chip multitasking fusion model. Decision boundaries refer to boundaries in classification problems that distinguish between different classes, or functions that predict target values in regression problems. Features input to the second fully connected layer are further combined and converted to generate a final output. In the second fully connected layer, the network defines decision boundaries by learning weights and biases. This may be achieved by optimizing a loss function that is used to measure the difference between model predictions and actual tags.

In this embodiment, by connecting two fully-connected layers through a function, the function includes a linear function or an activation function, so that the trained chip multitasking fusion model can obtain output data based on the linear function capturing the linear relationship between input data or obtain output data based on the activation function capturing the nonlinear relationship between input data, thereby realizing the versatility of the model.

In some embodiments, when two fully connected layers are connected by a linear function, part of the test data is part of the direct current data. The model is used for analyzing the linear relation among all measured data and outputting target prediction data representing the high-speed performance of the chip to be detected according to the input partial direct current data.

When the model is the target prediction data for predicting a certain chip, the partial direct current data is at least one direct current data measured by the chip. The target prediction data is high-speed data. Therefore, the relation between the direct current data and the high-speed data is captured through the linear function, so that the high-speed data can be obtained by using a model after the direct current data is measured, the complex testing steps for testing the high-speed data of the chip can be reduced, and the time for obtaining various performance data of the chip is shortened.

In some embodiments, when the two full connection layers are connected through an activation function, part of the test data is part of direct current data and/or part of high-speed data, the model is used for analyzing nonlinear relations among all measured data, and target grade data representing the performance grade of the chip to be detected is output according to the input part of direct current data and/or part of high-speed data.

When the model is used for predicting the target grade data of a certain chip, namely grading the chip, part of direct current data and/or part of high-speed data are at least one type of direct current data and/or at least one type of high-speed data measured by executing a test step on the chip. The target level data refers to the performance level of the chip, such as the first level and the second level. Thus, the nonlinear relation between the direct current data and/or the high-speed data and the chip grade is captured through the nonlinear function, so that the performance grade of the chip can be obtained by utilizing the model according to the input direct current data and/or the high-speed data, the efficiency of analyzing the chip grade can be improved, and the chip grade can be conveniently determined in a large scale.

In some embodiments, when training the model based on data input to the initial chip multitasking fusion model, correlations between various different types of measured data may be obtained by adjusting parameters of various network layers in the model. Thus, when the model is applied, part of the type of test data is input into the model and then combined with the parameters of each network layer to obtain other types of test data.

For the training process of the model for predicting the target performance data by analyzing the correlation between the measured data, see the following.

As shown in fig. 2 and 3, in some embodiments, the step of importing a plurality of different types of measured data into the initial chip multitasking fusion model to analyze the correlation between the measured data includes steps S202 to S212. Wherein:

Step S202, dividing the measured data of various different types into measured direct current data and measured high-speed data according to the types.

Step S204, inputting the actually measured direct current data into the first full connection layer to obtain a plurality of features corresponding to the actually measured direct current data.

In step S206, the plurality of features are input to the linear function, respectively, to obtain a plurality of linear outputs corresponding to the plurality of features.

And step S208, inputting a plurality of linear outputs to the second full-connection layer to obtain a characteristic representation corresponding to the actually measured direct current data.

In step S210, the feature representation is input to the output layer to obtain target prediction data through the output layer.

Step S212, based on the difference between the target predicted data and the actual measured high-speed data, the correlation between the actual measured direct current data and the actual measured high-speed data is obtained.

The actually measured dc data refers to dc data of a chip obtained by actually testing each chip, for example, a threshold current, a series resistance, and the like. The high-speed data is high-speed data of a chip obtained by actually testing each chip, such as an eye pattern value, a 3D bandwidth, and the like.

For example, in order to enable the trained chip multi-task fusion model to predict the high-speed data of the chip based on the direct-current data of the chip, after various different types of measured data are imported into the initial chip multi-task fusion model, the various different types of measured data may be classified into measured direct-current data and measured high-speed data according to types. The method comprises the steps of taking measured high-speed data as tag data, and adjusting parameters of an initial chip multi-task fusion model based on the difference between target prediction data predicted by the measured direct-current data, so as to obtain the relevance between the measured direct-current data and the measured high-speed data, and further obtain a trained chip multi-task fusion model. in the process that the initial chip multitasking fusion model obtains target prediction data based on the actually measured direct current data, the actually measured direct current data is input to the first full-connection layer through the input layer, and a plurality of characteristics corresponding to the actually measured direct current data are obtained. Namely, the first full connection layer performs feature extraction on the actually measured direct current data. And if the measured direct current data input into the model has a plurality of types, extracting the characteristics of the measured direct current data of the plurality of types. As shown in fig. 3, the first fully-connected layer includes a plurality of neurons. And each neuron performs feature extraction on at least one actually measured direct current data input into the model to respectively obtain the corresponding features of each neuron in the first full-connection layer. the features are then input into a linear function, and the linear function carries out digital operation processing on the features to obtain linear output corresponding to each feature. The corresponding linear output of each feature is then input to the corresponding second fully connected layer. The second fully-connected layer also includes a plurality of neurons. Each neuron processes the resulting linear outputs, e.g., performs feature combinations, to obtain a feature representation corresponding to each linear output. Thus, a plurality of characteristic representations of the second fully connected layer output have been obtained. If there is only one high-speed data, there is only one corresponding output neuron of the output layer. The output neurons may process these feature representations to obtain target prediction data. If there are a plurality of high-speed data, there are a plurality of output neurons of the output layer (refer to fig. 3). Each output neuron corresponds to one of the high-speed data to be predicted at this time. Each output neuron stores a processing policy for the representation of the feature. In this manner, each output neuron may derive corresponding target prediction data based on all of the characteristic representations, respectively. For example, the first output neuron is used to predict an eye diagram value. The second output neuron is used to predict 3D bandwidth. During training, the model may not be aware of how the incoming measured dc data is processed. Since the purpose of the model is to analyze the correlation between the measured direct current data and the measured high-speed data, the parameters in the model can be adjusted based on the difference between the target prediction data and the measured high-speed data, so that the target prediction data consistent with the measured high-speed data can be predicted after the measured direct current data is processed by the parameters in the model, or the target prediction data with the difference between the target prediction data and the measured high-speed data within a preset range can be predicted. the preset range is close to 0. Therefore, the correlation between the actually measured direct current data and the actually measured high-speed data can be obtained based on model analysis through the embodiment, so that the accurate high-speed data of the chip can be obtained rapidly after the chip is subjected to simple direct current data test, the complex high-speed data test on the chip is reduced, and the efficiency of obtaining the performance data of the chip can be improved.

It will be appreciated that after the data is input into the model, each network layer in the model will process the data using its own parameters. The network layer comprises a first full-connection layer, a linear function and a second full-connection layer. Thus, in some embodiments, obtaining the correlation between the measured data based on the difference between the target predicted data and the measured high speed data includes adjusting weights and offsets of the first fully connected layer, the linear function, and the second fully connected layer based on the difference between the target predicted data and the measured high speed data to obtain the correlation between the measured data. Wherein the weight is a parameter multiplied by data input to the network layer. The bias is a parameter that is added or subtracted from the data input to the network layer.

In this embodiment, by adjusting the weights and offsets of the first full-connection layer, the linear function, and the second full-connection layer, the difference between the target prediction data and the actually measured high-speed data can be reduced, so that when the target prediction data is substantially consistent with the high-speed data, the correlation between the direct-current data and the high-speed data of the chip is determined.

As shown in fig. 4 and 5, in some embodiments, to analyze the level of the chip, a plurality of different types of measured data are imported into the initial chip multi-task fusion model to analyze the correlation between the measured data, and steps S402 to S412 are further included. Wherein:

In step S402, the measured data of various different types are classified into measured chip data and measured class according to the types.

The actually measured chip data comprise actually measured direct current data and/or actually measured high-speed data.

Step S404, inputting the actually measured chip data into the first full connection layer to obtain a plurality of features corresponding to the actually measured chip data.

In step S406, the plurality of features are input to the activation function, respectively, to obtain a plurality of nonlinear outputs corresponding to the plurality of features.

Step S408, a plurality of nonlinear outputs are input to the second full connection layer, and feature representations corresponding to the measured chip data are obtained.

In step S410, the feature representation is input to the output layer to obtain the target level through the output layer.

Step S412, obtaining the correlation between the measured chip data and the measured level based on the difference between the target level and the measured level.

Since the relationship between the performance data of the chip and the rank data of the chip may be nonlinear, the data is processed based on the activation function in the rank analysis branch model, unlike the branch model that predicts the target performance data. Alternatively, the activation function may select a ReLU function or a tanh function.

For example, to enable the trained chip multi-task fusion model to analyze the performance level of the chip based on the direct current data and/or the high-speed data of the chip, the plurality of different types of measured data may be classified into measured chip data and measured levels by type after the plurality of different types of measured data are imported into the initial chip multi-task fusion model. The actual measurement grade is used as tag data and used for adjusting parameters of the initial chip multi-task fusion model based on the difference between target grades obtained by analysis of actual measurement chip data with the initial chip multi-task fusion model, so that the relevance between the actual measurement chip data and the actual measurement grade is obtained, and the trained chip multi-task fusion model is obtained. In the process that the initial chip multitasking fusion model obtains target prediction data based on actual measurement direct current data, the actual measurement chip data is input to a first full-connection layer through an input layer, and a plurality of characteristics corresponding to the actual measurement chip data are obtained. Namely, the first full connection layer performs feature extraction on the actually measured chip data. And if the measured chip data input into the model have a plurality of types, extracting the characteristics of the measured chip data of the plurality of types. As shown in fig. 3, the first fully-connected layer includes a plurality of neurons. And each neuron performs feature extraction on at least one measured chip data input to the model to respectively obtain the corresponding features of each neuron in the first full-connection layer. The features are then input to an activation function, which performs nonlinear processing on the features to obtain a linear output corresponding to each feature. For example, features corresponding to greater than zero are processed by the activation function to output the feature itself. Features corresponding to less than zero are processed by the activation function to output features corresponding to zero. The nonlinear output corresponding to each feature is then input to the corresponding second fully-connected layer. The second fully-connected layer also includes a plurality of neurons. Each neuron processes the obtained nonlinear output, for example, performs feature combination, to obtain a feature representation corresponding to each nonlinear output. Thus, a plurality of characteristic representations of the second fully connected layer output have been obtained. Since the performance level of the chip should be one, there is only one output neuron of the output layer (refer to fig. 5). The output neurons may process these feature representations to obtain the target level. During training, the model may not be aware of how the incoming measured chip data is processed to analyze the chip's rank. Because the purpose of the model is to analyze the correlation between the measured chip data and the measured grade, the parameters in the model can be adjusted based on the difference between the target grade and the measured chip data, so that the target grade consistent with the measured grade can be obtained through analysis after the parameters in the model process the measured chip data. Therefore, the correlation between the actually measured chip data and the actually measured grade can be obtained based on the model analysis, so that the effort consumed by manpower for grading the chips in the analysis of the chip performance data can be reduced, the error caused by the man is reduced, and the efficiency and the speed for grading the chips can be improved. And the model analyzes the actual measurement chip data and the actual measurement grades of a large number of chips, and the obtained correlation between the actual measurement chip data and the actual measurement grades can accurately analyze the grades of the chips based on the performance data of the chips.

Optionally, obtaining the correlation between the measured chip data and the measured grade based on the difference between the target grade and the measured grade includes adjusting weights and biases of the first fully-connected layer and the second fully-connected layer based on the difference between the target grade and the measured grade to obtain the correlation between the measured chip data and the measured grade. Wherein the weight is a parameter multiplied by data input to the network layer. The bias is a parameter that is added or subtracted from the data input to the network layer. In this embodiment, by adjusting the weights and the biases of the first full connection layer and the second full connection layer, the target level and the actual measurement level can be consistent, so as to determine the association relationship between the direct current data and the high-speed data of the chip.

In some embodiments, a plurality of different types of measured data may be preprocessed to ensure quality and availability of the measured data prior to being imported into the initial chip multitasking fusion model. The preprocessing step comprises the steps of data cleaning, data standardization, data enhancement and the like.

In some embodiments, determining the difference between the target level and the measured level or determining the difference between the target predicted data and the measured high-speed data may be determined based on a corresponding loss function. During the training process, a proper optimizer and loss function should be selected, so that the convergence and accuracy of the model can be ensured. After training is completed, a trained chip multitasking fusion model is obtained, and the model can be verified based on actual measurement data of some chips so as to evaluate the performance of the model.

In some embodiments, the trained chip multitasking fusion model may also evolve by adding data for a newly designed chip (iterative, upgraded version of the chip used in training) to better evaluate and predict the performance of the new design.

Through the training of the model, the trained model can perform task matching on the data input to the model, and if the direct current data of the chip is input to the model, the model can output high-speed data for predicting the chip. If the data input into the model includes high-speed data of the chip, the model may output a performance level obtained by analyzing the data of the chip. By training the model using the measured test data of the chip, the test data can be sufficiently subjected to reason and analysis, the correlation between various performance data can be obtained by analysis, and the accuracy and efficiency of the obtained performance data can be improved by the model.

It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.

Based on the same inventive concept, the embodiment of the application also provides a testing data processing device of the VCSEL chip for realizing the testing data processing method of the VCSEL chip. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in the embodiments of the test data processing device for one or more VCSEL chips provided below may be referred to the limitation of the test data processing method for a VCSEL chip hereinabove, and will not be described herein.

In an exemplary embodiment, as shown in fig. 6, a training apparatus for a chip performance prediction model is provided, including a construction module 601, an acquisition module 602, a training module 603, and a prediction module 604, where:

the construction module 601 is configured to construct an initial chip multitasking fusion model.

An acquisition module 602 is configured to acquire a plurality of different types of measured data that directly or indirectly characterize the high-speed performance of the VCSEL chip.

The training module 603 is configured to import multiple different types of measured data into the initial chip multi-task fusion model, analyze a linear or nonlinear relationship between the measured data, and continuously and iteratively update the initial chip multi-task fusion model to obtain a trained chip multi-task fusion model.

The prediction module 604 is configured to obtain partial performance test data of the VCSEL chip to be detected, input the partial performance test data to a trained chip multitasking fusion model, and output target performance prediction data of the VCSEL chip to be detected according to a linear relationship between the analyzed partial performance test data or output a performance level of the VCSEL chip to be detected according to a nonlinear relationship between the analyzed partial performance test data.

In some embodiments, the initial chip multi-task fusion model comprises an input layer, two full-connection layers and an output layer which are sequentially connected, wherein the two full-connection layers are connected through a function, the first full-connection layer is used for extracting features of measured data input into the initial chip multi-task fusion model, and the second full-connection layer is used for receiving features of the measured data after the function processing and performing decision boundary learning based on the features.

In some embodiments, the function comprises a linear function or an activation function.

In some embodiments, when two fully connected layers are connected through a linear function, part of the test data is part of direct current data, the model is used for analyzing the linear relation between all measured data, and outputting target prediction data representing the high-speed performance of the chip to be detected according to the input part of direct current data, wherein the target prediction data is high-speed data.

In some embodiments, the measured data directly characterizing the high speed performance of the VCSEL chip is high speed data, the measured data indirectly characterizing the high speed performance of the VCSEL chip is direct current data, the high speed data comprises at least one of a 3dB bandwidth, a relative intensity noise, and TDECQ values, and the direct current data comprises at least one of a threshold current, a series resistance, a clear aperture diameter, a skew efficiency, a center wavelength, and a spectral width.

In some embodiments, the training module 603 is further configured to divide the measured data of the plurality of different types into measured dc data and measured high-speed data according to the types, input the measured dc data into the first fully-connected layer to obtain a plurality of features corresponding to the measured dc data, input the plurality of features into a linear function to obtain a plurality of linear outputs corresponding to the plurality of features, input the plurality of linear outputs into the second fully-connected layer to obtain a feature representation corresponding to the measured dc data, input the feature representation into the output layer to obtain target prediction data through the output layer, and obtain a correlation between the measured dc data and the measured high-speed data based on a difference between the target prediction data and the measured high-speed data.

In some embodiments, the training module 603 is further configured to adjust weights and offsets of the first fully connected layer, the linear function, and the second fully connected layer based on a difference between the target prediction data and the measured high speed data to obtain a correlation between the measured data.

In some embodiments, the training module 603 is further configured to divide the plurality of different types of measured data into measured chip data and measured class according to types, where the measured chip data includes measured direct current data and/or measured high speed data;

inputting the actually measured chip data into the first full-connection layer to obtain a plurality of features corresponding to the actually measured chip data;

respectively inputting the multiple features into an activation function to obtain multiple nonlinear outputs corresponding to the multiple features;

Inputting a plurality of nonlinear outputs to a second full-connection layer to obtain a characteristic representation corresponding to the actually measured chip data;

Inputting the feature representation to an output layer to obtain a target grade through the output layer;

and obtaining the correlation between the measured chip data and the measured grade based on the difference between the target grade and the measured grade.

In some embodiments, the training module 603 is further configured to adjust weights and offsets of the first fully-connected layer and the second fully-connected layer based on a difference between the target level and the measured level to obtain a correlation between the measured chip data and the measured level.

The respective modules in the test data processing apparatus of the VCSEL chip described above may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In one exemplary embodiment, a computer device is provided, which may be a server, the internal structure of which may be as shown in fig. 7. The computer device includes a processor, a memory, an Input/Output interface (I/O) and a communication interface. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface is connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is used to store data for training and applying the chip performance prediction model. The input/output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, implements a training method for a chip performance prediction model, and a chip performance prediction method.

It will be appreciated by those skilled in the art that the structure shown in FIG. 7 is merely a block diagram of some of the structures associated with the present inventive arrangements and is not limiting of the computer device to which the present inventive arrangements may be applied, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.

In an exemplary embodiment, a computer device is provided, comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of any of the methods of the embodiments described above when the computer program is executed.

In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, implements the steps of any of the methods of the embodiments described above.

In an embodiment, a computer program product is provided comprising a computer program which, when executed by a processor, implements the steps of any of the methods of the embodiments described above.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in embodiments provided herein may include at least one of non-volatile memory and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (RESISTIVE RANDOM ACCESS MEMORY, reRAM), magneto-resistive Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (PHASE CHANGE Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in various forms such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computation, an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor, or the like, but is not limited thereto.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the present application.

The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims

1. A method of processing test data for a VCSEL chip, the method comprising:

constructing an initial chip multitasking fusion model;

acquiring a plurality of different types of measured data which directly or indirectly characterize the high-speed performance of the VCSEL chip;

importing the various different types of measured data into the initial chip multi-task fusion model to analyze linear or nonlinear relations among the measured data, and continuously iterating and updating the initial chip multi-task fusion model to obtain a trained chip multi-task fusion model;

2. The method for processing test data of the VCSEL chip according to claim 1, wherein the initial chip multi-task fusion model comprises an input layer, two full-connection layers and an output layer which are sequentially connected, the two full-connection layers are connected through a function, the first full-connection layer is used for extracting features of actual measurement data input into the initial chip multi-task fusion model, and the second full-connection layer is used for receiving features of the actual measurement data after the function processing and performing decision boundary learning based on the features.

3. A method of processing test data of a VCSEL chip according to claim 2, characterized in that the function comprises a linear function or an activation function.

4. The method for processing test data of a VCSEL chip according to claim 3, wherein when two fully connected layers are connected by the linear function, the partial performance test data is partial dc data, the model is used for analyzing a linear relationship between each of the actually measured data, and outputting target prediction data representing high-speed performance of the VCSEL chip to be detected according to the inputted partial dc data, wherein the target prediction data is high-speed data.

5. A method of processing test data of a VCSEL chip according to claim 3, wherein when two fully connected layers are connected by the activation function, the partial performance test data is partial dc data and/or partial high-speed data, the model is used to analyze a nonlinear relationship between each of the measured data, and target level data representing the performance level of the VCSEL chip to be detected is output according to the inputted partial dc data and/or the partial high-speed data.

6. The method of claim 1, wherein the measured data directly characterizing the high-speed performance of the VCSEL chip is high-speed data, and the measured data indirectly characterizing the high-speed performance of the VCSEL chip is direct-current data, the high-speed data including at least one of a 3dB bandwidth, a relaxation oscillation frequency, a relative intensity noise, and TDECQ values, and the direct-current data including at least one of a threshold current, a series resistance, a via diameter, a skew efficiency, a center wavelength, and a spectral width.

7. The method of claim 4, wherein the step of importing the plurality of different types of measured data into the initial chip multitasking fusion model to analyze correlations between the measured data comprises:

Dividing the measured data of various different types into measured direct current data and measured high-speed data according to the types;

Inputting the actually measured direct current data into the first full-connection layer to obtain a plurality of characteristics corresponding to the actually measured direct current data;

Inputting the characteristics into the linear function respectively to obtain a plurality of linear outputs corresponding to the characteristics;

inputting the plurality of linear outputs to the second full-connection layer to obtain a characteristic representation corresponding to the actually measured direct current data;

inputting the characteristic representation to the output layer to obtain target prediction data through the output layer;

And obtaining the relevance between the actual measurement direct current data and the actual measurement high-speed data based on the difference between the target prediction data and the actual measurement high-speed data.

8. The method of claim 7, wherein the obtaining the correlation between the measured data based on the difference between the target predicted data and the measured high-speed data comprises:

And adjusting weights and offsets of the first fully-connected layer, the linear function and the second fully-connected layer based on the difference between the target prediction data and the actually-measured high-speed data so as to obtain the relevance between the actually-measured data.

9. The method of claim 5, wherein the step of importing the plurality of different types of measured data into the initial chip multitasking fusion model to analyze correlations between the measured data comprises:

Dividing the measured data of various different types into measured chip data and measured grades according to the types, wherein the measured chip data comprises measured direct current data and/or measured high-speed data;

inputting the actually measured chip data into the first full-connection layer to obtain a plurality of characteristics corresponding to the actually measured chip data;

inputting the characteristics into the activation function respectively to obtain a plurality of nonlinear outputs corresponding to the characteristics;

inputting the nonlinear outputs to the second full-connection layer to obtain a characteristic representation corresponding to the actually measured chip data;

Inputting the characteristic representation to the output layer to obtain a target grade through the output layer;

10. The method of claim 9, wherein the obtaining the correlation between the measured chip data and the measured level based on the difference between the target level and the measured level comprises:

and adjusting the weights and the biases of the first full-connection layer and the second full-connection layer based on the difference between the target grade and the actual measurement grade so as to obtain the relevance between the actual measurement chip data and the actual measurement grade.

11. A test data processing device for a VCSEL chip, the test data processing device comprising:

The acquisition module is used for acquiring various different types of actual measurement data which directly or indirectly characterize the high-speed performance of the VCSEL chip;

The training module is used for importing the various different types of measured data into the initial chip multi-task fusion model so as to analyze the linear or nonlinear relation among the measured data, and continuously iterating and updating the initial chip multi-task fusion model to obtain a trained chip multi-task fusion model;