CN119300346B - Memory manufacturing method, memory, device and equipment - Google Patents
Memory manufacturing method, memory, device and equipmentInfo
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- CN119300346B CN119300346B CN202411258204.5A CN202411258204A CN119300346B CN 119300346 B CN119300346 B CN 119300346B CN 202411258204 A CN202411258204 A CN 202411258204A CN 119300346 B CN119300346 B CN 119300346B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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Abstract
The application provides a preparation method of a memory, the memory, a device and equipment, wherein the method comprises the steps of forming a first active structure, a semiconductor structure and a second active structure which are stacked in sequence on a substrate, wherein the doping concentration of the first active structure is the same as that of the second active structure, and the doping concentration of the semiconductor structure is different from that of the first active structure; the method comprises the steps of forming a first memory based on a first active structure, rewinding the first memory and removing a substrate to expose a second active structure and a semiconductor structure, depositing metal materials on two sides of the semiconductor structure in a BL area to form a metal structure, wherein the metal structure communicates the semiconductor structure with an adjacent semiconductor structure, forming a second memory based on a second active structure, and sharing the semiconductor structure and the metal structure by the first source drain structure of the first memory and the second source drain structure of the second memory. The application can improve the integration level of the memory.
Description
Technical Field
The present application relates to the field of integrated semiconductors, and in particular, to a method for manufacturing a memory, a device, and an apparatus.
Background
Dynamic random access memory (dynamic random access memory, DRAM) typically employs a structure of a transistor and a capacitor (1T 1C) as the memory cells of the chip. With the continued evolution of architecture, the area of DRAM memory cells is 4F 2 (F is the feature size). However, as moore's law continues, the area shrinking of conventional DRAM encounters a bottleneck, and thus a method capable of reducing the area of DRAM memory cells and increasing the memory density is needed.
Disclosure of Invention
The application provides a preparation method of a memory, the memory, a device and equipment, which can reduce the area of a storage unit of the memory and improve the storage density and the integration level.
In a first aspect, an embodiment of the application provides a method for manufacturing a memory, the method comprising the steps of forming a stacked structure on a substrate, forming a first active structure, a semiconductor structure and a second active structure, wherein the first active structure, the semiconductor structure and the second active structure are sequentially stacked in a first direction, the first active structure is far away from the substrate compared with the second active structure, the first active structure, the semiconductor structure and the second active structure are self-aligned along the first direction, the doping concentration of the first active structure is the same as that of the second active structure, the doping concentration of the semiconductor structure is different from that of the first active structure, forming a first memory based on the first active structure, rewinding the first memory and removing the substrate to expose the second active structure and the semiconductor structure, depositing metal materials on two sides of the semiconductor structure in a bit line BL area to form a metal structure, the metal structure communicates the semiconductor structure with the adjacent semiconductor structure, and forming a second memory based on the second active structure, wherein the first active structure in the first memory and the second memory share the semiconductor structure and the metal structure.
In one possible embodiment, depositing a metal material on both sides of the semiconductor structure in the bit line BL region to form the metal structure includes depositing a metal material on both sides of the semiconductor structure, the metal material having a height that is the height of the semiconductor structure, and etching the metal material in the WL region to form the metal structure.
In one possible embodiment, forming a stacked structure on a substrate includes sequentially stacking a first material layer, a second material layer, and a third material layer on the substrate, and etching the third material layer, the second material layer, and the first material layer to form a first active structure, a semiconductor structure, and a second active structure.
In one possible implementation, forming the first memory based on the first active structure includes forming a first transistor based on the first active structure, forming a first capacitance structure on the first transistor, forming the second memory based on the second active structure includes forming a second transistor based on the second active structure, and forming a second capacitance structure on the second transistor.
In one possible embodiment, forming the first transistor based on the first active structure comprises forming a first gate structure based on the first active structure, removing the first gate structure in the BL region to form a first groove, depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, wherein the upper surface of the first insulating layer is flush with the upper surface of a first mask, the first mask is positioned on the first active structure, removing the first mask to form a second groove, and forming a first source drain structure in the second groove.
In one possible embodiment, the first gate structure comprises a first gate electrode layer and a first gate dielectric layer surrounding the first gate electrode layer, wherein the first gate electrode layer is lower than the first gate dielectric layer in height, the first gate structure is removed in the BL region to form a first groove, the first groove comprises the steps of forming a sacrificial layer on the first gate electrode layer in the BL region, the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer, and the bottom of the sacrificial layer and the first gate electrode layer below the sacrificial layer are anisotropically etched to form the first groove.
In one possible implementation, forming a first capacitance structure over a first transistor includes forming a first dielectric layer over a first source-drain structure, etching a first portion of the first dielectric layer to expose the first source-drain structure, and forming the first capacitance structure over the first source-drain structure.
In a second aspect, an embodiment of the present application provides a memory, where the memory is made by using the preparation method described in the first aspect and any embodiment of the first aspect, and the memory includes a BL structure, where the BL structure is formed by a semiconductor structure and a metal structure, a first memory, and a second memory, where the second memory is disposed opposite to the first memory, and a first source drain structure in the second memory and a second source drain structure in the first memory share the BL structure.
In a third aspect, an embodiment of the present application provides a semiconductor device including a memory as described in the second aspect above.
In a fourth aspect, an embodiment of the present application provides an electronic device, including a circuit board and a semiconductor device as described in the third aspect, where the semiconductor device is disposed on the circuit board.
In the present application, a first memory (front memory) may be prepared based on a front-side active structure (first active structure) by forming a stacked structure including the first active structure, a semiconductor structure, and a second active structure on a substrate, then rewinding the front-side memory and removing the substrate to expose the first active structure and the semiconductor structure, then depositing a metal material on both sides of the semiconductor structure in a BL region to form a metal structure that communicates the semiconductor structure with an adjacent semiconductor structure, and finally preparing a second memory (back memory) based on the second active structure. In the embodiment of the application, the active structure is formed by etching the BL area and the WL area at one time, so that the self alignment of the front and back BL and the WL is ensured. Through wafer bonding and rewinding, two storage units with the size of 4F 2 are integrated on the front side and the back side, so that the equivalent area of the memory is 2F 2, the area of the storage unit of the memory is reduced, and the storage density and the integration level of the memory are improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic flow chart of an embodiment of a method for manufacturing a memory according to the present application;
FIG. 2 is a schematic top view of a memory according to an embodiment of the application;
FIGS. 3 to 21 are schematic views showing the structure of a memory in a first manufacturing process according to an embodiment of the present application;
FIG. 22 is a schematic diagram of a first structure of a memory according to an embodiment of the application;
FIG. 23 is a schematic top view of another memory according to an embodiment of the application;
FIGS. 24 to 33 are schematic diagrams showing the structure of a memory in a second manufacturing process according to an embodiment of the present application;
fig. 34 is a schematic diagram of a second structure of a memory according to an embodiment of the application.
The figures above:
10. Memory, 11, first transistor (front-side transistor), 111, first active structure, 112, first source-drain structure, 113, first gate structure, 1131, first gate dielectric layer, 1132, first gate electrode layer, 12, second transistor, 121, second active structure, 122, second source-drain structure, 123, second gate structure, 1231, second gate dielectric layer, 1232, second gate electrode layer, 13, third insulating layer, 14, carrier wafer, 20, substrate, 21, first material layer, 22, second material layer, 23, third material layer, 24, first mask, 25, semiconductor structure, 26, first shallow trench isolation structure, 27, isolation layer, 28, sacrificial layer, 29, first recess, 30, first oxide layer, 31, first insulating layer, 32, second recess, 33, first dielectric layer, 34, first capacitor structure, 35, BL structure, 36, active structure, 37, second shallow trench isolation structure, 38, second oxide layer, 39, second capacitor layer, 40, second dielectric layer, 41.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.
While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits. With the continuous development of transistor technology, a flip-chip stacked transistor has been developed, in which active regions of upper and lower homologous transistors are formed by etching, and the flip-chip stacked transistor is fabricated on the front and back sides of a wafer by chamfering, so that the disadvantages of the conventional schemes can be overcome.
In a DRAM, ferroelectric random access memory (ferroelectric random access memory, feRAM), or other memory, the memory cells may include transistor and capacitor structures. The transistor is arranged on the substrate, the capacitor structure is positioned at one end of the transistor far away from the substrate, and the transistor is electrically connected with the capacitor structure.
Taking DRAM as an example, the basic composition of DRAM is 1T1C. At present, the DRAM mainly has three forms, wherein the area of the first DRAM is 8F 2, the first DRAM is realized by horizontally placing a transistor and a capacitor structure, the area of the second DRAM is 6F 2, the arrangement density can be increased by inclining the placement positions of the transistor and the capacitor structure, so that the smaller integrated area is realized, the area of the third DRAM is 4F 2, and the volume in the vertical direction is fully utilized by vertically placing the transistor and the capacitor structure, so that the smaller area of the DRAM is scaled.
At the moment of further shrinking the size of integrated circuits, there is a need for a method that can reduce the area of memory cells of a memory and increase the memory density.
Based on the above, the embodiment of the application provides a preparation method of a memory, which can reduce the area of a memory unit of the memory and improve the memory density and the integration level.
In some embodiments, the memory may include a plurality of memory cells, each of which may include a flip-chip stacked transistor and a capacitive structure (capacitor), wherein the capacitive structure is electrically connected to the flip-chip stacked transistor.
In some embodiments, the flip-chip stacked transistor may include a gate structure, a source structure, and a drain structure, and the capacitor structure may be electrically connected to the source structure of the flip-chip stacked transistor and the capacitor structure, or the drain structure of the flip-chip stacked transistor may be electrically connected to the capacitor structure, and the flip-chip stacked transistor controls writing, changing, or reading information in the capacitor structure. I.e., flip-chip stacked transistors, as select devices (or switching devices) may control writing, modifying, or reading of information in the capacitive structure.
In some embodiments, a capacitive structure may include a first electrode and a second electrode, and a capacitive dielectric layer between the first electrode and the second electrode. Illustratively, the first electrode may be electrically connected to the drain structure of the flip-chip stacked transistor and the second electrode may be grounded.
In some embodiments, the memory cell may further include a plurality of Word Line (WL) structures and a plurality of Bit Line (BL) structures, wherein the WL structures are disposed perpendicular to the BL structures. Wherein the WL structure may be connected to the gate structure of the flip-chip stacked transistor, thereby controlling on and off of the flip-chip stacked transistor. The BL structure may be connected to a source structure or a drain structure of the flip-chip stacked transistor, thereby writing data into a capacitance structure connected to the flip-chip stacked transistor when the flip-chip stacked transistor is turned on.
In some embodiments, the flip-chip stacked transistor may include at least two transistors, for example, a first transistor and a second transistor, where the first transistor and the second transistor are disposed opposite to each other, and a first active structure of the first transistor and a second active structure of the second transistor are formed through the same process, so it may be understood that the first transistor and the second transistor share the active structure.
In the embodiment of the present application, the first transistor and the second transistor in the flip-chip stacked transistor are transistors of the same type, such as a vertical channel transistor (VERTICAL CHANNEL transistor, VCT), which may also be referred to as a vertical gate-all transistor.
Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a memory according to an embodiment of the present application, as shown in fig. 1, the method for manufacturing a memory according to an embodiment of the present application may include:
and S110, forming a stacked structure on the substrate.
The stacked structure comprises a first active structure, a semiconductor structure and a second active structure which are stacked in sequence in a first direction, wherein the first active structure is far away from the substrate compared with the second active structure, and the first active structure, the semiconductor structure and the second active structure are self-aligned along the first direction.
In some embodiments, the implementation process of the step S110 may be divided into a first step of stacking a first material layer, a second material layer and a third material layer on a substrate in sequence, and a second step of etching the third material layer, the second material layer and the first material layer to form a first active structure, a semiconductor structure and a second active structure.
In the first step, the first material layer and the third material layer are doped the same, and the doping concentration of the second material layer is different from the doping concentration of the first material layer.
The substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon carbide substrate, or the like.
It will be appreciated that the doping concentration of the first material layer is the same as that of the third material layer, and the doping concentration of the second material layer is different from that of the first material layer, so that the first material layer and the third material layer with the same doping can be etched later to be used as an active structure shared by a front-side transistor (first transistor) and a back-side transistor (second transistor) in the flip-chip stacked transistor, and the second material layer with the different doping is used as a BL structure of the memory.
In some embodiments, the doping concentration of the second material layer may be higher than the doping concentration of the first material layer. The BL structure is used as a data transmission channel, the doping concentration of the BL structure mainly influences the data transmission efficiency and the noise performance, and the higher doping concentration can improve the conductivity of the BL structure and reduce the resistance, so that the data transmission speed is increased.
Since the memory cell of the memory includes the WL region and the BL region, after the first material layer, the second material layer, and the third material layer are sequentially stacked on the substrate, the material layers in the WL region and the BL region may be etched to form the active structure.
In some embodiments, the second step may be implemented by forming a first mask on the third material layer, where the first mask is used to locate the WL area and the BL area, and etching the third material layer, the second material layer, and the first material layer based on the first mask to form a first active structure, a semiconductor structure, and a second active structure. That is, after forming a mask by photolithography, etching is performed in both the BL direction and the WL direction, so that self-alignment of the BL region and the WL region can be ensured.
It will be appreciated that the first mask is formed over the third material layer, the first mask being used to locate the WL region and the BL region, and thus the first mask covers a portion of the third material layer in both the WL region and the BL region, such that the first active structure, the semiconductor structure and the second active structure may be formed by etching the third material layer, the second material layer and the first material layer based on the first mask. Wherein the semiconductor structure is not connected in both the WL region and the BL region.
Illustratively, the etching process may be at least one of dry etching, wet etching, reactive ion etching, and the like.
In some embodiments, after forming the first active structure, the semiconductor structure, and the second active structure, an oxide material may be deposited on the substrate to form a first shallow trench isolation (shallow trench isolation, STI) structure.
It is understood that an oxide material may be deposited on the substrate and thinned to a predetermined height such that an upper surface of the first shallow trench isolation structure is formed higher than an upper surface of the semiconductor structure and exposes the gate structure of the front side transistor for subsequent fabrication of the gate structure of the front side transistor. The oxide material forming the shallow trench isolation structure may be, for example, any of silicon nitride (SiN, si3N 4), silicon dioxide (SiO 2), silicon oxycarbide (SiCO), or the like. The thinning process may be, for example, a chemical-mechanical planarization (CMP) process or the like.
Step S120, forming a first memory based on the first active structure.
In some embodiments, the implementation of step S120 may include two steps, forming a first transistor based on the first active structure, and forming a first capacitance structure on the first transistor.
In some embodiments, forming the first transistor based on the first active structure may be performed by forming a first gate structure based on the first active structure, removing the first gate structure in the BL region to form a first recess, depositing an insulating material on the first gate structure in the WL region and in the first recess to form a first insulating layer, an upper surface of the first insulating layer being flush with an upper surface of the first mask, removing the first mask to form a second recess, and forming a first source drain structure in the second recess.
It will be appreciated that after the first shallow trench isolation structures are thinned to a predetermined height, the gate regions of the front-side transistors are exposed, i.e., first gate recesses are formed between the first active structures, such that an insulating material may be deposited at the first gate recesses to form a first gate dielectric layer, and a metal material may be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate electrode layer and the first gate dielectric layer surrounding the first gate electrode layer together form a first gate structure. The height of the first gate dielectric layer may be higher than the height of the first gate electrode layer.
For example, the first gate dielectric layer may be composed of a silicon oxide layer and a high K hafnium oxide layer, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.
By way of example, the first gate electrode layer may be composed of multiple layers of electrode materials, each layer of electrode material including, but not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals.
Since the WL structure in the WL region is connected to the gate structure of the transistor, the first gate structure in the WL region is necessary, and the first gate structure in the BL region may not exist, and thus the first gate structure in the BL region may be selectively removed.
In some embodiments, removing the first gate structure in the BL region and forming the first recess may be performed by forming a sacrificial layer on the first gate electrode layer in the BL region, wherein an upper surface of the sacrificial layer is flush with an upper surface of the first gate dielectric layer, and anisotropically etching a bottom of the sacrificial layer and the first gate electrode layer under the sacrificial layer to form the first recess.
It can be appreciated that a sacrificial layer attached to the bottom of the first gate electrode layer, the sidewall of the first gate dielectric layer, and the sidewall of the first mask may be deposited on the first gate electrode layer in the BL region, the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer, and then the bottom of the sacrificial layer and the first gate electrode layer under the sacrificial layer are anisotropically etched to obtain the first recess. Since the anisotropic etch is from the bottom of the sacrificial layer down, and there is also a portion of the first gate electrode layer under the sidewalls of the sacrificial layer, this portion of the first gate electrode layer remains.
The insulating material may be, for example, oxide, nitride, or the like. In the deposition of the sacrificial layer, a very thin film may be deposited on the surface of the substrate by atomic layer deposition (atomic layer deposition, ALD).
In some embodiments, the sacrificial layer may be removed after the first recess is formed.
It will be appreciated that after forming the first recess, an insulating material may be deposited over the first gate structure in the WL region and within the first recess to form a first insulating layer, an upper surface of the first insulating layer being flush with an upper surface of the first mask. And then removing the first mask to form a second groove, and forming a first source-drain structure of the front-side transistor in the second groove. The first insulating layer is used for being isolated from the first source-drain structure of the front-side transistor. In the case that the transistor formed in the embodiment of the present application is VCT, the source structure and the drain structure of VCT are approximately symmetrical, so for convenience of explanation, the first source-drain structure referred to in the embodiment of the present application is simply referred to as a first source structure and/or a first drain structure. In addition, the same is true for the second source drain structure which appears later.
For example, a metal material may be first ion-implanted into the second recess, and then annealed to form a silicide, where the silicide is used as the first source drain structure, and this is only exemplary, and may be determined according to needs in actual operation. In the case of using silicide as the first source structure, the BL structure may be used as the first drain structure. In the case of silicide as the first drain structure, the BL structure may be used as the first source structure.
In some embodiments, an insulating material may be deposited on the first gate structure in the WL region, forming an isolation layer, so that only the BL region is processed. In this manner, the isolation layer over the WL region may be removed after the sacrificial layer is removed, so that the first insulating layer is formed on both the WL region and the BL region.
In some embodiments, after the sacrificial layer is removed, an oxide material may also be deposited within the first recess in the BL region, forming a first oxide layer. A first insulating layer is then formed over the first oxide layer in the BL region and the first gate structure in the WL region. The first oxide layer may also be formed by ALD deposition, for example.
After forming the first source drain structure, a capacitance structure of the front side memory may be formed on the front side transistor.
In some embodiments, forming the first capacitor structure on the first transistor may be performed by forming a first dielectric layer on the first source-drain structure, etching a first portion of the first dielectric layer to expose the first source-drain structure, and forming the first capacitor structure on the first source-drain structure.
It will be appreciated that a first capacitor structure comprising a first electrode and a second electrode and a capacitor dielectric layer between the first electrode and the second electrode may be formed by depositing an insulating medium over the first source drain structure, forming a first dielectric layer, then etching a portion of the first dielectric layer to expose the underlying first source drain structure, and depositing a layer of metal material over the first source drain structure, then depositing a dielectric material, and then depositing a layer of metal material. The first dielectric layer between the first capacitor structures can be used as an isolation structure between the first capacitor structures.
And S130, rewinding the first memory and removing the substrate to expose the second active structure and the semiconductor structure.
In some embodiments, the step S130 may be implemented by rewinding the first memory and removing the substrate, and thinning the first shallow trench isolation structure to a predetermined height to expose the second active structure and the semiconductor structure, where the thinned first shallow trench isolation structure is used to isolate the first transistor from the second transistor.
It will be appreciated that after the first capacitor structure is formed, the first capacitor structure may be bonded to the carrier wafer, then the first capacitor structure is reworked, and the substrate is removed and the first shallow trench isolation structure is thinned so that the second active structure and the semiconductor structure are exposed, facilitating subsequent formation of the BL structure and preparation of the backside memory.
In some embodiments, an insulating material (e.g., silicon oxide) may be deposited over the first capacitor structure to form a third insulating layer and bonded to the carrier wafer, after which the first capacitor structure is reworked and the substrate removed.
After the substrate is removed, the upper surface of the second active structure is flush with the upper surface of the first shallow trench isolation structure, so that the first shallow trench isolation structure can be thinned to a preset height to expose the semiconductor structure. The preset height can be set according to actual requirements, which is not limited in the embodiment of the present application.
And step 140, depositing metal materials on two sides of the semiconductor structure in the BL area to form the metal structure.
It will be appreciated that the semiconductor structures in step S110 are not connected in both the BL region and the WL region, while the BL structure in the memory is not connected in the WL region and is connected in the BL region, and therefore, the embodiment of the present application forms a metal structure by depositing a metal material between the semiconductor structures in the BL region, and connects adjacent semiconductor structures through the metal structure, so that a BL structure including the semiconductor structure and the metal structure can be formed, and the semiconductor structure in the WL region is not affected.
In some embodiments, step S140 may be performed by depositing a metal material on both sides of the semiconductor structure, the metal material having a height that is the height of the semiconductor structure, and etching the metal material in the WL region to form the metal structure.
It will be appreciated that metallic material may be deposited first on both sides of the semiconductor structure in the WL and BL regions, and then etched in the WL region, leaving metallic material in the BL region. Since the height of the metal material is the height of the semiconductor structures, the semiconductor structures in the BL region can be connected through the metal material, and the metal material between the semiconductor structures in the WL region is removed to prevent short circuit, so that the metal structures can be formed.
In some embodiments, metal materials may be deposited in both the WL region and the BL region, but due to the difference in coverage areas of the metal deposition in the BL region and the WL region caused by layout design and process fabrication, the metal materials in the BL region may fill both sides of the semiconductor structure and the second active structure, i.e. fill the recess between the adjacent semiconductor structure and the second active structure, while the metal materials in the WL region only cover the surfaces of both sides of the semiconductor structure and the second active structure. And then, the metal materials of the two areas can be etched through anisotropic etching, and the etching rate is strictly controlled, so that enough metal materials exist at the semiconductor structure in the BL area, the conduction of the BL structure can be realized, and the metal materials at the semiconductor structure in the WL area are removed, thereby preventing the short circuit of BL and WL.
In some embodiments, the deposition of the metallic material may also be formed by ALD deposition, for example.
In some embodiments, after forming the BL structure, an oxide material may be deposited on the BL structure in the BL region and the first shallow trench isolation structure in the WL region to form a second shallow trench isolation structure.
It is understood that after the second shallow trench isolation structure is formed, the third shallow trench isolation structure may be thinned to a predetermined height to expose the gate region of the back side transistor for subsequent fabrication of the gate structure of the back side transistor.
Step S150, forming a second memory based on the second active structure.
In some embodiments, the implementation of step S150 may include two steps of forming a second transistor based on the second active structure, and forming a second capacitance structure on the second transistor.
In some embodiments, forming the second transistor based on the second active structure may be performed by forming a second gate structure based on the second active structure, removing the second gate structure in the BL region to form a third recess, depositing an insulating material on the second gate structure in the WL region and in the second recess to form a second insulating layer, an upper surface of the second insulating layer being flush with an upper surface of a second mask located on the second active structure, removing the second mask to form a fourth recess, and forming a second source drain structure in the fourth recess.
It will be appreciated that after thinning the second shallow trench isolation structures to a predetermined height, the gate regions of the back side transistors are exposed, i.e., a second gate recess is formed between the second active structures, such that an insulating material may be deposited at the second gate recess to form a second gate dielectric layer, and a metal material may be deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together form a second gate structure. The height of the second gate dielectric layer may be higher than the height of the second gate electrode layer.
In some embodiments, removing the second gate structure in the BL region and forming the third recess may be performed by forming a sacrificial layer on the second gate electrode layer in the BL region, the upper surface of the sacrificial layer being flush with the upper surface of the second gate dielectric layer, anisotropically etching the bottom of the sacrificial layer and the second gate electrode layer under the sacrificial layer to form the third recess.
It can be appreciated that a sacrificial layer attached to the bottom of the second gate electrode layer, the sidewall of the second gate dielectric layer, and the sidewall of the second mask may be deposited on the second gate electrode layer in the BL region, the upper surface of the sacrificial layer is flush with the upper surface of the second gate dielectric layer, and then the bottom of the sacrificial layer and the second gate electrode layer under the sacrificial layer are anisotropically etched to obtain the third recess. Since the anisotropic etch is from the bottom of the sacrificial layer down and there is also a portion of the second gate electrode layer under the sidewalls of the sacrificial layer, this portion of the second gate electrode layer remains.
In some embodiments, the sacrificial layer may be removed after the third recess is formed.
In some embodiments, a second mask may be formed on the second active structure in the WL area and the BL area before forming the second insulating layer, and a width of the second mask is the same as a width of the second active structure. After forming the third recess, an insulating material may be deposited on the second gate structure in the WL region and in the third recess to form a second insulating layer, an upper surface of the second insulating layer being flush with an upper surface of the second mask. And removing the second mask to form a fourth groove, and forming a second source-drain structure of the back side transistor in the fourth groove.
In some embodiments, an insulating material may be deposited on the second gate structure in the WL region, forming an isolation layer, so that only the BL region is processed. In this manner, the isolation layer over the WL region may be removed after the sacrificial layer is removed, so that the second insulating layer is formed on both the WL region and the BL region.
In some embodiments, after the sacrificial layer is removed, an oxide material may also be deposited in the third recess in the BL region, forming a second oxide layer. A second insulating layer is then formed over the second oxide layer in the BL region and the second gate structure in the WL region. The second oxide layer may also be formed by ALD deposition, for example.
After forming the second source drain structure, a capacitance structure of the back side memory may be formed on the back side transistor.
In some embodiments, forming the second capacitor structure on the second transistor may be performed by forming a second dielectric layer on the second source-drain structure, etching a first portion of the second dielectric layer to expose the second source-drain structure, and forming the second capacitor structure on the second source-drain structure.
It will be appreciated that a second capacitor structure comprising a first electrode and a second electrode and a capacitor dielectric layer between the first electrode and the second electrode may be formed by depositing an insulating medium over the second source drain structure, forming a second dielectric layer, then etching a portion of the second dielectric layer to expose the underlying second source drain structure, and depositing a layer of metal material over the second source drain structure, then depositing a dielectric material, and then depositing a layer of metal material. The second dielectric layer between the second capacitor structures can be used as an isolation structure between the second capacitor structures.
In addition, in some embodiments, the spacing between BL structures and the spacing between WL structures in the embodiments of the present application may be the same or different, as long as the product of the two spacings is 4F 2. For example, the spacing between BL structures and WL structures is 2F, or the spacing between BL structures is 4F and the spacing between WL structures is F. The embodiment of the present application is not limited thereto.
In the present application, a first memory (front memory) may be prepared by forming a stacked structure including a first active structure, a semiconductor structure, and a second active structure on a substrate, then based on the front-side active structure (first active structure), rewinding the front-side memory and removing the substrate to expose the first active structure and the semiconductor structure, then depositing a metal material on both sides of the semiconductor structure in a BL region to form the metal structure, and finally preparing a second memory (back memory) based on the second active structure. In the embodiment of the application, the active structure is formed by etching the BL area and the WL area at one time, so that the self alignment of the front and back BL and the WL is ensured. Through wafer bonding and rewinding, two storage units with the size of 4F2 are integrated on the front side and the back side, so that the equivalent area of the memory is 2F2, the area of the storage unit of the memory is reduced, and the storage density and the integration level of the memory are improved. In addition, the embodiment of the application can realize the diversification of the memory structure by changing the spacing between the BL structure and the WL structure.
The following describes a method for manufacturing a memory provided by the embodiment of the present application, taking an active structure in VCT as an example of a nanowire structure. First, the first preparation process is described, namely, the active structure of the transistor in the memory is still a standard nanowire structure, and the WL structure and the BL structure have different pitches. Fig. 2 is a schematic top view of a memory according to an embodiment of the present application, where only a nanowire structure, a BL structure, and a WL structure are shown in the top view for ease of understanding. The A-A 'direction is the tangential direction of the memory along the BL structure, and the B-B' direction is the tangential direction of the memory along the WL structure. Fig. 3 to 21 are schematic structural diagrams of a memory in a first manufacturing process according to an embodiment of the present application, and fig. 22 is a schematic structural diagram of a memory in an embodiment of the present application. Fig. 3 to 22 (a) are sectional views of the memory along a sectional direction (i.e., A-A 'direction) of the BL structure, and fig. 3 to 22 (B) are sectional views of the memory along a sectional direction (i.e., B-B' direction) of the WL structure.
In one example, the process of preparing memory 10 may include the steps of:
in the first step, a first material layer 21, a second material layer 22 and a third material layer 23 are sequentially formed on an original substrate 20, resulting in the structure shown in fig. 3.
The doping concentration of the second material layer is higher than that of the first material layer.
For example, a layer of highly doped silicon may be epitaxially grown on a silicon substrate as a BL structure for the memory, and then a layer of relatively thick, low doped silicon may be epitaxially grown on the same substrate to provide for a front-side memory device.
A second step of forming a first mask 24 on the third material layer 23, the first mask 24 being used to define the active structures of the WL and BL regions, and then etching the third material layer 23, the second material layer 22 and the first material layer 21 in sequence up to the substrate 20 based on the first mask 24 to form self-aligned first active structures 111, semiconductor structures 25 and second active structures 121, resulting in the structure shown in fig. 4.
It will be appreciated that here the etching is performed simultaneously in the WL and BL regions, so that self-alignment of BL and WL is ensured.
Third, oxide material is deposited on the substrate 20 to form the first shallow trench isolation structure 26 and CMP and etching are performed to expose the front side transistor, resulting in the structure shown in fig. 5.
And a fourth step of selectively depositing an insulating material on the surface of the first active structure 111 to form a first gate dielectric layer 1131, thereby obtaining the structure shown in fig. 6.
And fifthly, depositing a metal material on the first gate dielectric layer 1131 and performing CMP to a certain height to form a first gate electrode layer 1132, thereby obtaining the structure shown in fig. 7.
The first gate dielectric layer 1131 and the first gate electrode layer 1132 form the first gate structure 113, and the height of the first gate dielectric layer 1131 is higher than the height of the first gate electrode layer 1132.
A sixth step of forming an isolation layer 27 by photolithography and etching to cover the WL area so that only the BL area is processed later, resulting in the structure shown in fig. 8.
A seventh step of depositing a sacrificial layer 28 attached to the bottom of the first gate electrode layer 1132, the sidewall of the first gate dielectric layer 1131, and the sidewall of the first mask 24 on the first gate electrode layer 1132 to obtain the structure shown in fig. 9.
Eighth, the bottom of the sacrificial layer 28 and the first gate electrode layer 1132 under the sacrificial layer 28 are anisotropically etched, and then the sacrificial layer 28 is removed to form the first recess 29, resulting in the structure shown in fig. 10.
It will be appreciated that the anisotropic etch is from the bottom of the sacrificial layer down to the bottom of the sacrificial layer, and that a portion of the first gate electrode layer is also present under the sidewalls of the sacrificial layer.
Illustratively, in depositing the sacrificial layer, a very thin sacrificial layer may be deposited on the substrate surface by ALD deposition.
A ninth step of depositing an oxide material in the first recess 29 to form a first oxide layer 30, resulting in the structure shown in fig. 11.
Tenth, the isolation layer 27 over the WL area is removed and an insulating material (e.g., siN) is deposited in both areas to form a first insulating layer 31, resulting in the structure shown in fig. 12.
An eleventh step of selectively etching the first mask 24 to form the second recess 32 results in the structure shown in fig. 13.
A twelfth step of forming a first source-drain structure 112 in the second recess 32, and depositing an insulating medium on the first source-drain structure 112 to form a first dielectric layer 33, resulting in the structure shown in fig. 14.
For example, a metal material may be deposited by ion implantation in the second recess 32, and then annealed to form a silicide as the first source drain structure.
A thirteenth step of etching a portion of the first dielectric layer 33 to expose the first source drain structure 112 and forming the first capacitor structure 34 on the first source drain structure 112 results in the structure shown in fig. 15.
The first capacitor structure may include deposition of a metal upper plate, deposition of a dielectric layer, and deposition of a metal lower plate, and fig. 15 is merely a simplified representation.
A fourteenth step of depositing an insulating material on the first capacitor structure 34 to form a third insulating layer 13, bonding the third insulating layer 13 to the carrier wafer 14, and then rewinding to obtain the structure shown in fig. 16.
Fifteenth, the substrate 20 is removed to the first shallow trench isolation structure 26, resulting in the structure shown in fig. 17.
Sixteenth, the first shallow trench isolation structure 26 is thinned to the bottom of the semiconductor structure 25, resulting in the structure shown in fig. 18.
Seventeenth, simultaneously depositing metal materials in the WL area and the BL area to obtain the structure shown in fig. 19.
It will be appreciated that, due to the smaller spacing of the active structures in the BL direction in the top view of the first fabrication process, the deposited metal material is sufficient to fill the recesses between the adjacent second active structures 121 and semiconductor structures 25, corresponding to fig. 19 (a). Whereas the pitch of the active structures in the WL direction is large, so the deposited metal material cannot fill the entire recess, and only the surfaces of the second active structure 121 and the semiconductor structure 25 can be covered, corresponding to fig. 19 (b). For example, the metallic material may be deposited by means of ALD.
Eighteenth, the metal material is anisotropically etched to form BL structure 35, resulting in the structure shown in fig. 20.
It will be appreciated that by anisotropically etching the metal material and tightly controlling the etch rate, there is sufficient metal material at the BL region and metal at the WL region is removed to prevent shorting. As shown in fig. 20 (a) and (b), the BL structure connects the semiconductor structure through the metal material at the BL region, and does not connect at the WL region. Fig. 20 (c) is a schematic top view of a memory structure, where the active structure 36 includes a first active structure 111 and a second active structure 121, and lengths of the active structure 36 in the WL direction and the BL direction are determined by a metal deposition and etching process, and the WL structure and the BL structure have different pitches, where F and 4F are only examples.
Nineteenth, oxide material is deposited and CMP is performed to a height over the BL structure in the BL region and the first shallow trench isolation structure in the WL region to form a second shallow trench isolation structure 37, resulting in the structure shown in fig. 21.
A twentieth step is to prepare the second transistor and the second capacitor structure 41 resulting in the structure shown in fig. 22.
It may be appreciated that a second mask may be formed on the second active structure 121 first, then an insulating material may be selectively deposited on a surface of the second active structure 121 to form a second gate dielectric layer 1231, a metal material may be deposited on the second gate dielectric layer 1231 and CMP to a certain height to form a second gate electrode layer 1232, and thus the second gate structure 123 may be formed. And then forming an isolation layer by photoetching and etching to cover the WL region, so that the BL region is conveniently processed. Thereafter, a sacrificial layer attached to the bottom of the second gate electrode layer 1242, the sidewall of the second gate dielectric layer 1231, and the sidewall of the second mask may be deposited on the second gate electrode layer 1232, the bottom of the sacrificial layer and the second gate electrode layer 1232 under the sacrificial layer may be anisotropically etched, then the sacrificial layer is removed to form a recess, an oxide material is deposited in the recess to form the second oxide layer 38, the isolation layer over the WL area is removed, an insulating material (e.g., siN) is deposited in both areas to form the second insulating layer 39, the second mask is selectively etched to form a recess, the second source drain structure 122 is formed in the recess, and an insulating medium is deposited on the second source drain structure 122 to form the second dielectric layer 40, a portion of the second dielectric layer 40 is etched to expose the second source drain structure 122, and the second capacitor structure 41 is formed on the second source drain structure 122. Here, the second drain structure of the second transistor is connected to the BL structure 35, and the second source structure of the second transistor is connected to the second capacitor structure 41.
Reference may be made here to the fourth to thirteenth steps.
The second manufacturing process is described below, i.e., the active structure of the transistor in storage is still a nanoplatelet structure, but the nanoplatelet structure cross-section varies in length and width. The WL and BL structures have the same pitch. Fig. 23 is a schematic top view of another memory according to an embodiment of the present application, where only the nano-sheet structure, the BL structure and the WL structure are shown in the top view for easy understanding. The A-A 'direction is the tangential direction of the memory along the BL structure, and the B-B' direction is the tangential direction of the memory along the WL structure. Fig. 24 to 33 are schematic structural diagrams of a memory in a second manufacturing process according to an embodiment of the present application, and fig. 34 is a schematic structural diagram of a memory in an embodiment of the present application. Fig. 24 to 34 (a) are sectional views of the memory along the sectional direction of the BL structure (i.e., the A-A 'direction), and fig. 24 to 34 (B) are sectional views of the memory along the sectional direction of the WL structure (i.e., the B-B' direction).
In one example, the process of preparing memory 10 may include the steps of:
First, a first material layer 21, a second material layer 22 and a third material layer 23 are sequentially formed on an original substrate 20, resulting in the structure shown in fig. 24.
The doping concentration of the second material layer is higher than that of the first material layer.
For example, a layer of highly doped silicon may be epitaxially grown on a silicon substrate as a BL structure for the memory, and then a layer of relatively thick, low doped silicon may be epitaxially grown on the same substrate to provide for a front-side memory device.
A second step of forming a first mask 24 on the third material layer 23, the first mask 24 being used to define the active structures of the WL and BL regions, and then etching the third material layer 23, the second material layer 22 and the first material layer 21 in sequence up to the substrate 20 based on the first mask 24 to form self-aligned first active structures 111, semiconductor structures 25 and second active structures 121, resulting in the structure shown in fig. 25.
It will be appreciated that here the etching is performed simultaneously in the WL and BL regions, so that self-alignment of BL and WL is ensured.
Third, oxide material is deposited on the substrate 20 to form the first shallow trench isolation structure 26, and CMP and etching are performed to expose the front side transistor, resulting in the structure shown in fig. 26.
Fourth, a first transistor and first capacitor structure 34 is formed over the first shallow trench isolation structure 26, resulting in the structure shown in fig. 27.
Reference may be made here to the fourth to thirteenth steps in the first preparation process described above, and no further description is given here.
Fifth, an insulating material is deposited on the first capacitor structure 34 to form a third insulating layer 13, and the third insulating layer 13 is bonded to the carrier wafer 14, and then rewound to obtain the structure shown in fig. 28.
The sixth step is to remove the substrate 20 to the first shallow trench isolation structure 26 to obtain the structure shown in fig. 29.
Seventh, the first shallow trench isolation structure 26 is thinned to the bottom of the semiconductor structure 25, resulting in the structure shown in fig. 30.
Eighth, metal materials are simultaneously deposited in the WL region and the BL region, resulting in the structure shown in FIG. 31.
It will be appreciated that, due to the smaller spacing of the active structures in the BL direction in the top view of the second manufacturing process, the deposited metal material is sufficient to fill the recesses between the adjacent second active structures 121 and the semiconductor structures 25, corresponding to fig. 31 (a). Whereas the pitch of the active structures in the WL direction is large, so the deposited metal material cannot fill the entire recess, and only the surfaces of the second active structure 121 and the semiconductor structure 25 can be covered, corresponding to (b) of fig. 31. For example, the metallic material may be deposited by means of ALD.
And a ninth step of anisotropically etching the metal material to form BL structure 35, resulting in the structure shown in fig. 32.
It will be appreciated that by anisotropically etching the metal material and tightly controlling the etch rate, there is sufficient metal material at the BL region and metal at the WL region is removed to prevent shorting. As shown in fig. 32 (a) and (b), the BL structure connects the semiconductor structure through the metal material at the BL region, and does not connect at the WL region. Fig. 32 (c) is a schematic top view of the memory structure, where the active structure 36 includes a first active structure 111 and a second active structure 121, and the lengths of the active structures along the WL direction and the BL direction are determined by the metal deposition and etching process, and the spacing between the WL structure and the BL structure is the same.
Tenth, oxide material is deposited and CMP is performed to a certain height on the BL structure in the BL region and the first shallow trench isolation structure in the WL region to form a second shallow trench isolation structure 37, resulting in the structure shown in FIG. 33.
An eleventh step of preparing the second transistor and the second capacitor structure 41 results in the structure shown in fig. 34.
Reference is made here to the fourth to thirteenth steps in the first preparation process described above.
The application starts from the specific process flow of the self-aligned flip-chip stacked transistor, combines with the manufacturing flow of the 4F 2 DRAM, forms an active structure through the integrated forming of the BL area and the WL area, and ensures the full self alignment of BL and WL. Through wafer bonding and rewinding, two storage units with the size of 4F 2 are integrated on the front side and the back side, so that the equivalent area of the memory is 2F 2, the area of the storage unit of the memory is reduced, and the storage density and the integration level of the memory are improved.
Further, the memory provided by the embodiment of the application can be detected by using a detection and analysis instrument, such as a scanning electron microscope (scanning electron microscope, SEM), a transmission electron microscope (transmission electron microscope, TEM), a scanning transmission electron microscope (scanning transmission electron microscopy, STEM) and the like. Taking TEM as an example, the embodiment of the application can detect the structure of the memory by adopting a TEM section mode, and can observe that the 1T1C structure in the basic structure of the memory exists on the front side and the back side, and simultaneously, the WL structure and the BL structure are all self-aligned.
The embodiment of the application provides a semiconductor device, which comprises the memory of the embodiment.
The embodiment of the application provides electronic equipment, which comprises a circuit board and the semiconductor device in the embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device comprises the memory.
In the description of the embodiments of the present application, the descriptions of the terms "one embodiment," "an example," "a particular example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A method of manufacturing a memory, the method comprising:
forming a stacked structure on a substrate, wherein the stacked structure comprises a first active structure, a semiconductor structure and a second active structure which are stacked in sequence in a first direction, the first active structure is far away from the substrate compared with the second active structure, the first active structure, the semiconductor structure and the second active structure are self-aligned along the first direction, the doping concentration of the first active structure is the same as that of the second active structure, and the doping concentration of the semiconductor structure is different from that of the first active structure;
forming a first memory based on the first active structure;
rewinding the first memory and removing the substrate to expose the second active structure and the semiconductor structure;
depositing a metal material on both sides of the semiconductor structure in the bit line BL region to form a metal structure, wherein the metal structure communicates the semiconductor structure with an adjacent semiconductor structure;
And forming a second memory based on the second active structure, wherein the first source-drain structure in the first memory and the second source-drain structure in the second memory share the semiconductor structure and the metal structure.
2. The method of claim 1, wherein depositing a metal material on both sides of the semiconductor structure in the bit line BL region to form a metal structure comprises:
depositing metal materials on two sides of the semiconductor structure, wherein the height of the metal materials is the height of the semiconductor structure;
and etching the metal material in the WL region to form the metal structure.
3. The method of claim 1, wherein forming a stacked structure on a substrate comprises:
Sequentially stacking a first material layer, a second material layer and a third material layer on the substrate;
and etching the third material layer, the second material layer and the first material layer to form the first active structure, the semiconductor structure and the second active structure.
4. The method of claim 1, wherein forming a first memory based on the first active structure comprises:
forming a first transistor based on the first active structure;
forming a first capacitor structure on the first transistor;
the forming a second memory based on the second active structure includes:
forming a second transistor based on the second active structure;
A second capacitance structure is formed over the second transistor.
5. The method of claim 4, wherein forming a first transistor based on the first active structure comprises:
forming a first gate structure based on the first active structure;
removing the first grid structure in the BL area to form a first groove;
Depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, wherein the upper surface of the first insulating layer is flush with the upper surface of a first mask, and the first mask is positioned on the first active structure;
Removing the first mask to form a second groove;
And forming a first source drain structure in the second groove.
6. The method of claim 5, wherein the first gate structure comprises a first gate electrode layer and a first gate dielectric layer surrounding the first gate electrode layer, the first gate electrode layer having a height that is lower than a height of the first gate dielectric layer;
The removing the first gate structure in the BL region to form a first recess includes:
Forming a sacrificial layer on the first gate electrode layer in the BL region, wherein the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer;
and anisotropically etching the bottom of the sacrificial layer and the first gate electrode layer positioned below the sacrificial layer to form the first groove.
7. The method of claim 5, wherein forming a first capacitance structure on the first transistor comprises:
forming a first dielectric layer on the first source drain structure;
Etching a first part of the first dielectric layer to expose the first source drain structure;
And forming the first capacitor structure on the first source-drain structure.
8. A memory prepared using the preparation method according to any one of claims 1 to 7, comprising:
A BL structure composed of a semiconductor structure and a metal structure;
a first memory;
The second memory is arranged opposite to the first memory, and the BL structure is shared by a first source-drain structure in the second memory and a second source-drain structure in the first memory.
9. A semiconductor device according to claim 8, comprising a memory.
10. An electronic apparatus comprising a circuit board and the semiconductor device according to claim 9, wherein the semiconductor device is provided on the circuit board.
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