CN119300414A - A double-channel planar gate silicon carbide LDMOS and a preparation method thereof - Google Patents

Abstract

The invention provides a double-channel planar gate silicon carbide LDMOS and a preparation method thereof, comprising the steps of forming a barrier layer on a silicon carbide substrate, etching, and implanting ions to form a first channel region and a first N-type source region; the method comprises the steps of forming a barrier layer, etching, ion implantation to form an isolation region, forming a barrier layer again, etching, ion implantation to form a second channel region, forming a barrier layer again, etching, ion implantation to form a P-type well region, forming a barrier layer again, etching, ion implantation to form a second N-type source region, forming a barrier layer again, etching, depositing metal to form a body diode metal layer, forming a barrier layer again, etching, depositing to form a gate dielectric layer, forming a barrier layer again, etching, depositing metal to form a gate metal layer again, forming a barrier layer again, etching, depositing metal to form a source metal layer and a drain metal layer respectively, removing the barrier layer, completing preparation, and carrying out double-channel structure design to reduce the on resistance of the device.

Description

A double-channel planar gate silicon carbide LDMOS and a preparation method thereof

Technical Field

The invention relates to a double-channel planar gate silicon carbide LDMOS and a preparation method thereof.

Background Art

LDMOS (Laterally Diffused Metal Oxide Semiconductor), or laterally diffused metal oxide semiconductor, is a special type of power MOSFET (metal oxide semiconductor field effect transistor) widely used in RF and microwave power amplifiers. LDMOS combines the advantages of bipolar transistors and MOSFETs, providing high gain, high durability and good thermal stability.

LDMOS is widely used in fields that require wide frequency range, high linearity and long service life, such as CDMA, W-CDMA, TETRA, and digital terrestrial television. With the continuous advancement of technology, the performance of LDMOS is also constantly improving. For example, Philips' fifth-generation LDMOS technology provides higher power density and efficiency; however, the on-resistance of existing LDMOS is still relatively large, and there is interference between channels, which reduces the conductivity.

Summary of the invention

The technical problem to be solved by the present invention is to provide a dual-channel planar gate silicon carbide LDMOS and a preparation method thereof, to perform a dual-channel structure design in a lateral power device and to reduce the on-resistance of the device.

In a first aspect, the present invention provides a method for preparing a double-channel planar gate silicon carbide LDMOS, comprising the following steps:

Step 1, forming a barrier layer on a silicon carbide substrate, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate to form a first channel region, wherein the ion implantation energy is 230-330 keV;

Step 2, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate to form a first N-type source region, wherein the ion implantation energy is 10-330kev;

Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate and the first N-type source region to form an isolation region, wherein the ion implantation energy is 130-230kev;

Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate to form a second channel region, wherein the ion implantation energy is 10-130kev;

Step 5: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, perform ion implantation on the silicon carbide substrate and the first N-type source region to form a P-type well region, and the ion implantation energy is 10-130kev;

Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the silicon carbide substrate to form a second N-type source region, with the ion implantation energy being 10-130kev;

Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the silicon carbide substrate to the upper side of the isolation region, depositing metal, and forming a body diode metal layer;

Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer;

Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer;

Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer and a drain metal layer respectively, remove the barrier layer, and complete the preparation.

In a second aspect, the present invention provides a dual-channel planar gate silicon carbide LDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a dual-channel planar gate silicon carbide LDMOS according to the first aspect.

The advantages of the present invention are:

1. The present invention constructs a dual channel based on an N-type LDMOS device. By constructing a low-resistance first channel, the device on-current can be effectively shunted to the top and inside of the device, thereby reducing the on-resistance of the device;

Second, the present invention constructs a body diode metal layer just below the source metal of the device, through which electrons from the source can flow to the P-type isolation region and then to the first N-type source region when the device is not turned on, and a parasitic body diode with the drain is formed through the second channel;

3. The gate structure of the present invention is distributed on the left and right sides of the source, the left gate controls the second channel region on the surface of the device, and the right gate controls the first channel of the device;

Fourth, the present invention adopts a P-type silicon carbide substrate, which can effectively suppress the substrate leakage of the device;

5. P-type isolation regions are set in the first channel region and the second channel region, which can effectively suppress the mutual interference between the second channel of the device and the second channel and improve the conductivity of each channel.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

FIG1 is a schematic diagram of a dual-channel planar gate silicon carbide LDMOS according to the present invention.

FIG. 2 is a cross-sectional view of a process of a dual-channel planar gate silicon carbide LDMOS according to the present invention.

FIG. 3 is a second cross-sectional view of a process of manufacturing a dual-channel planar gate silicon carbide LDMOS according to the present invention.

FIG. 4 is a third cross-sectional view of a process of a dual-channel planar gate silicon carbide LDMOS according to the present invention.

FIG. 5 is a fourth cross-sectional view of a process of a dual-channel planar gate silicon carbide LDMOS according to the present invention.

FIG. 6 is a fifth cross-sectional view of a process of manufacturing a dual-channel planar gate silicon carbide LDMOS according to the present invention.

FIG. 7 is a sixth cross-sectional view of a process of manufacturing a dual-channel planar gate silicon carbide LDMOS according to the present invention.

FIG8 is a seventh cross-sectional view of a process of manufacturing a dual-channel planar gate silicon carbide LDMOS according to the present invention.

FIG. 9 is a cross-sectional view eight of a process of manufacturing a dual-channel planar gate silicon carbide LDMOS according to the present invention.

FIG. 10 is a ninth cross-sectional view of a process of manufacturing a dual-channel planar gate silicon carbide LDMOS according to the present invention.

FIG. 11 is a cross-sectional view of the tenth process of a dual-channel planar gate silicon carbide LDMOS according to the present invention.

FIG. 12 is a cross-sectional view eleven of a process of manufacturing a dual-channel planar gate silicon carbide LDMOS according to the present invention.

DETAILED DESCRIPTION

In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and/or parts, these elements, components, regions, layers, doping types and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

When used herein, the singular forms "a", "an", and "said/the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include/comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and/or" includes any and all combinations of the relevant listed items.

As shown in FIGS. 1 to 12 , the present application embodiment provides a method for preparing a double-channel planar gate silicon carbide LDMOS, comprising the following steps:

Step 1, forming a barrier layer 113 on the silicon carbide substrate 101, etching the barrier layer 113 to form a through hole, and performing ion implantation on the silicon carbide substrate 101 to form a first channel region 103, wherein the ion implantation energy is 230-330 keV;

Step 2, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation on the silicon carbide substrate 101 to form a first N-type source region 102, wherein the ion implantation energy is 10-330 keV;

Step 3, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation on the silicon carbide substrate 101 and the first N-type source region 102 to form an isolation region 104, wherein the ion implantation energy is 130-230 keV;

Step 4, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation on the silicon carbide substrate 101 to form a second channel region 105, wherein the ion implantation energy is 10-130 keV;

Step 5, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation on the silicon carbide substrate 101 and the first N-type source region 102 to form a P-type well region 106, with the ion implantation energy being 10-130 keV;

Step 6: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, perform ion implantation on the silicon carbide substrate 101 to form a second N-type source region 107, and the ion implantation energy is 10-130kev;

Step 7, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, etching the silicon carbide substrate 101 to the upper side of the isolation region 104, depositing metal, and forming a body diode metal layer 108;

Step 8, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and depositing to form a gate dielectric layer 109;

Step 9, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, depositing metal, and forming a gate metal layer 111;

Step 10, remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, deposit metal to form a source metal layer 110 and a drain metal layer 112 respectively, remove the barrier layer, and complete the preparation.

As shown in FIG1 , the planar gate silicon carbide LDMOS obtained by the above manufacturing method comprises:

Silicon carbide substrate 101,

A first N-type source region 102 , wherein the lower side of the first N-type source region 102 is connected to the upper side of the silicon carbide substrate 101 ;

A first channel region 103 , wherein a lower side of the first channel region 103 is connected to an upper side of the silicon carbide substrate 101 , and an outer side of the first channel region 103 is connected to an inner side of the first N-type source region 102 ;

An isolation region 104, wherein the lower side of the isolation region 104 is connected to the first channel region 103 and the first N-type source region 102 respectively; and the outer side of the isolation region 104 is connected to the inner side of the first N-type source region 102;

A second channel region 105 , wherein a lower side of the second channel region 105 is connected to an upper side of the isolation region 104 , and a left side of the second channel region 105 is connected to the first N-type source region 102 ;

A P-type well region 106, wherein the lower side of the P-type well region 106 is connected to the isolation region 104, the left side of the P-type well region 106 is connected to the right side of the second channel region 105, and the right side of the P-type well region 106 is connected to the first N-type source region 102; a first through hole (not shown) is provided in the P-type well region 106;

A second N-type source region 107, wherein the second N-type source region 107 is disposed in the first through hole, wherein the lower side of the second N-type source region 107 is connected to the upper side of the isolation region 104, and wherein a second through hole (not shown) is disposed in the second N-type source region 107;

A body diode metal layer 108, wherein the body diode metal layer 108 is disposed in the second through hole, and a lower side of the body diode metal layer 108 is connected to the isolation region 104;

A gate dielectric layer 109 , wherein the gate dielectric layer 109 is connected to the P-type well region 106 , and a third through hole (not shown) is disposed in the gate dielectric layer 109 ;

A source metal layer 110, wherein the source metal layer 110 is disposed in the third through hole, and the lower side of the source metal layer 110 is respectively connected to the upper side of the second N-type source region 107 and the upper side of the body diode metal layer 108;

A gate metal layer 111, wherein the gate metal layer 111 is connected to the gate dielectric layer 109;

and a drain metal layer 112 , wherein the drain metal layer 112 is connected to the first N-type source region 102 .

In this embodiment, preferably, the doping concentration of the first channel region 103 and the doping concentration of the second channel region 105 are both greater than the doping concentration of the isolation region 104 ; the doping concentration of the first channel region 103 is greater than the doping concentration of the second channel region 105 .

In this embodiment, preferably, the thickness of the second channel region 105 is greater than the thickness of the first channel region 103 , the thickness of the second channel region 105 is greater than the thickness of the isolation region 104 ; and the thickness of the first channel region 105 is equal to the thickness of the isolation region 104 .

In this embodiment, preferably, the silicon carbide substrate 101 is of P type, the first channel region 103 and the second channel region 105 are both of N type, and the isolation region 104 is of P type.

The gate dielectric layer 109 is silicon dioxide, the doping concentration of the silicon carbide substrate 101 is 1-5e17cm ^-3 , the first channel region 103 is N-type doped 1-3e18cm ^-3 , the doping concentration of the first N-type source region 102 is 5-8e18cm ^-3 , the doping concentration of the P-type isolation region 104 is 1-3e17cm ^-3 , the second channel region 105 is doped 5-9e17 cm ^-3 , the doping concentration of the second N-type source region 107 is 5-8e18cm ^-3 , the source metal layer 110 , the gate metal layer 111 , the drain metal layer and the body diode metal layer 108 can be one or more alloys of aluminum, nickel and titanium;

Among them, the P-type silicon carbide substrate 101 is to suppress the reverse leakage of the device. Since the conductive path of the second channel region 105 is longer, the doping concentration of the first channel region 103 and the first N-type source region 102 is to reduce the on-resistance of the second channel region 105 and achieve better shunting in the device body. The doping concentration of the P-type isolation region 104 is to ensure that the first channel region 103 and the second channel region 105 are isolated while not affecting the conductive channel of the device to avoid increasing the on-resistance. The first channel region 103 and the second N-type source region 107 are to achieve a compromise between the on-resistance and withstand voltage of the device. The second N-type source region 107 and the first N-type source region 102 also have the function of forming ohmic contact with the drain metal layer 112 and the source metal layer 110.

The thickness of the P-type silicon carbide substrate 101 of the device is 300-500nm, which is to ensure the support of the subsequent structure preparation of the device. The thickness of the first channel region 103 is 300nm, which is to reserve the influence of the P-type isolation region 104 and the space charge region formed therewith on the on-resistance of the conductive channel. The thickness of the P-type isolation region 104 is 300nm, which is a compromise between achieving the isolation function and avoiding the influence on the conductivity after comprehensive consideration of the doping concentration and thickness. The thickness of the second channel region 105 is 400nm, which is due to the low doping concentration of the second channel region 105. In order to reduce the influence of the P-type isolation region 104 on it, the design is carried out. The thickness of the first N-type source region 102 is 1000nm, which is to reduce the on-resistance of the second channel region 105 and achieve better shunting of the two channels. The thickness of the second N-type source region 107 is equal to that of the second channel region 105.

In the traditional LDMOS, due to the limited gate thickness, the device current is mainly distributed at the top of the device. The present invention constructs a double channel based on the N-type LDMOS device. By constructing a low-resistance first channel region 103, the device conduction current can be effectively shunted at the top and inside of the device, thereby reducing the on-resistance of the device.

A body diode metal layer 108 is constructed directly below the device source metal layer 110, through which electrons from the source can flow to the P-type isolation region 104 and then to the first N-type source region 102 when the device is not turned on, and a parasitic body diode with the drain is formed through the second channel region 105 to complete the freewheeling when the device is not turned on;

The gate structure of the device is distributed on the left and right sides of the source. The left gate controls the second channel region 105 on the surface of the device, and the right gate controls the first channel region 103 of the device. The two gates are controlled by the same driving signal, avoiding the complexity of the driving.

Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims (8)

1. The preparation method of the double-channel planar gate silicon carbide LDMOS is characterized by comprising the following steps:

step 1, forming a barrier layer on a silicon carbide substrate, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate to form a first channel region, wherein the ion implantation energy is 230-330kev;

Step 2, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate to form a first N-type source region, wherein the ion implantation energy is 10-330kev;

Step 3, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate and the first N-type source region to form an isolation region, wherein the ion implantation energy is 130-230kev;

Step 4, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate to form a second channel region, wherein the ion implantation energy is 10-130kev;

step 5, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate and the first N-type source region to form a P-type well region, wherein the ion implantation energy is 10-130kev;

Step 6, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate to form a second N-type source region, wherein the ion implantation energy is 10-130kev;

Step 7, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, etching the silicon carbide substrate to the upper side surface of the isolation region, and depositing metal to form a body diode metal layer;

step 8, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer;

Step 9, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a gate metal layer;

and 10, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, depositing metal, respectively forming a source metal layer and a drain metal layer, and removing the barrier layer to finish the preparation.

2. The method of manufacturing a dual-channel planar gate silicon carbide LDMOS as set forth in claim 1, wherein the doping concentration of said first channel region and the doping concentration of said second channel region are both greater than the doping concentration of said isolation region.

3. The method of manufacturing a dual channel planar gate silicon carbide LDMOS as set forth in claim 1, wherein the doping concentration of said first channel region is greater than the doping concentration of said second channel region.

4. The method of manufacturing a dual-channel planar gate silicon carbide LDMOS as set forth in claim 1, wherein the second channel region has a thickness greater than the thickness of the first channel region and the second channel region has a thickness greater than the thickness of the isolation region.

5. The method of manufacturing a dual channel planar gate silicon carbide LDMOS as set forth in claim 1, wherein the thickness of said first channel region is equal to the thickness of said isolation region.

6. The method for manufacturing a dual-channel planar gate silicon carbide LDMOS as claimed in claim 1, wherein the silicon carbide substrate is P-type.

7. The method of manufacturing a dual-channel planar gate silicon carbide LDMOS as claimed in claim 1, wherein the first and second channel regions are both N-type and the isolation region is P-type.

8. The double-channel planar gate silicon carbide LDMOS is characterized in that the silicon carbide VDMOS is prepared by the preparation method according to any one of claims 1 to 7.