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CN119381381A - A FLASH chip three-dimensional stacking packaging structure and packaging method - Google Patents

A FLASH chip three-dimensional stacking packaging structure and packaging method Download PDF

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Publication number
CN119381381A
CN119381381A CN202411319106.8A CN202411319106A CN119381381A CN 119381381 A CN119381381 A CN 119381381A CN 202411319106 A CN202411319106 A CN 202411319106A CN 119381381 A CN119381381 A CN 119381381A
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chip
layer
substrate
flash chip
flash
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陈平
刘冰
夏良
贺京峰
尹灿
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GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR CO Ltd
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GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR CO Ltd
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Publication of CN119381381A publication Critical patent/CN119381381A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

A FLASH chip three-dimensional stacking packaging structure and a packaging method belong to the technical field of semiconductor chip packaging. The wafer rewiring technology is utilized to lead out the front electrode of the FLASH chip to the front surface of the chip and the back surface of the multilayer substrate according to the setting, copper column bumps are formed for interconnection during stacking, the wire bonding technology is utilized to interconnect the multilayer substrate, and flip-chip packaging technology is utilized to interconnect the substrate BGA and the copper column bumps to realize vertical stacking integration of the chip. The method solves the problems of the prior art that chips are stacked in a staggered manner or vertically stacked on a multi-layer substrate, interconnection welding is difficult, the number and layout of electrodes are limited, the thermal expansion coefficients among materials are not matched, and the packaging cost is high, and realizes the FLASH chip stacking package with high packaging density. The method is widely applied to the technical field of high-performance and low-cost microsystem SiP packaging.

Description

Three-dimensional stacked packaging structure and packaging method for FLASH chips
Technical Field
The invention belongs to the technical field of semiconductor chip packaging, and further relates to the technical field of semiconductor chip three-dimensional packaging, in particular to a three-dimensional stacked packaging structure and a packaging method of a FLASH chip.
Background
The embedded FLASH memory simplifies the design and connection process by integrating the memory chip, the controller and the interface, provides a convenient, compact and high-integration memory solution, and is widely applied to embedded systems and mobile equipment. In order to meet the requirements of high integration and small size of low cost FLASH chip packaging, the three-dimensional stacking packaging technology is one of the most dominant packaging technologies at present. The chip stacking is realized by rewiring, bump and through silicon via technology, which is the three-dimensional stacking packaging technology most widely used, but the packaging technology has higher cost and is only suitable for HBM type high-integration storage stacking packaging. For the memory chips (such as eMMC chips) with low-medium-level packaging density, the stacking mode realized by re-wiring, bump and through-silicon via technology has higher cost, so that the realization of the stack packaging of the low-medium-density memory chips based on the advantages of low cost of traditional packaging and the advantages of re-wiring and bump flexibility is a technical problem to be broken through at present.
The prior art has the defects that:
Under the drive of the requirements of electronic equipment on high performance, miniaturization and modularization of chips, the traditional multi-FLASH chip two-dimensional system integration mode has difficulty in meeting the requirements. As shown in fig. 1, although the current packaging process design has realized multi-layer chip stacking, it is difficult to integrate memory chips of higher packaging density due to the number and layout of electrodes of the packaged chips. For example, chinese patent application No. CN117790483a discloses a stacked package structure of a calculation integrated chip, in which chips are stacked on a carrier (multi-layer substrate) in a staggered manner, the chips are interconnected with the carrier through wire bonding, and the back of the carrier is interconnected through BGA, so as to integrate the calculation chip with the memory chip. Chinese patent application No. CN117612952a discloses a stacking method and structure of LGA package, mainly by forming a step-shaped mold with a soft adhesive, then stacking the chip in a Z-shape on the mold, and realizing interconnection by wire bonding. The two modes are all that the storage chip stacking package is realized through staggered stacking, and the staggered stacking package structure has large limitation and limited application. The Chinese patent with the application number of CN117878064A discloses a vertical stacking method, which is characterized in that a storage chip is wire-bonded on a substrate, chip electrodes are distributed on the back surface of the substrate by using a rewiring technology, and a middle stacked chip-substrate structure of a vertical interconnection structure is manufactured in the same way.
In view of this, the present invention has been made.
Disclosure of Invention
The invention aims to solve the technical problems of difficult interconnection welding, limited electrode quantity layout, unmatched thermal expansion coefficients between materials and high packaging cost in the prior art that chips are stacked in a staggered manner or vertically on a carrier plate (a multi-layer substrate).
The invention is characterized in that the front electrode of the FLASH chip is divided into two parts by a wafer rewiring technology, a multilayer wiring substrate and a wire bonding technology, the two parts are respectively led out to the front surface of the chip and the back surface of the multilayer substrate, the FLASH chip electrode is led out to be a double electrode by the wafer rewiring technology, copper column convex points are formed for interconnection during stacking, the substrate BGA and the copper column convex points are interconnected by the wire bonding technology and the multilayer substrate, and the vertical stacking integration of the chip is realized by the flip-chip packaging technology.
Therefore, the invention provides a three-dimensional stacked package structure of FLASH chips, as shown in FIG. 2. Comprising the following steps:
The chip comprises a FLASH chip 1, an on-chip electrode 101, a chip surface rewiring layer 2, a chip surface rewiring passivation layer 3, chip surface rewiring interconnection copper columns 4, a multilayer substrate 5, a wiring circuit 501 in the substrate, a chip bonding layer 6, bonding wires 7, a plastic layer 8, a substrate BGA9 and an interlayer filling layer 10.
The back of the multilayer substrate 5 is a substrate BGA9, the front is a chip bonding area and a wire bonding area, and the substrate BGA9 is correspondingly connected with the chip bonding area and the wire bonding area through a wiring circuit 501 in the substrate.
The FLASH chip 1 is adhered to the chip adhesion area through the chip adhesion layer 6.
The chip surface rewiring passivation layer 3 is located on the surface of the FLASH chip 1.
The chip surface rerouting layer 2 is located on the surface of the chip surface rerouting passivation layer 3, and the wire bonding area on the surface of the chip surface rerouting layer 2 and the chip surface rerouting interconnection copper pillar 4 are correspondingly connected with the electrode on the chip surface (the on-chip electrode 101).
The wire bonding area on the surface of the chip surface rewiring layer 2 and the wire bonding area on the front surface of the multilayer substrate 5 are bonded and connected according to the circuit connection rule through bonding wires 7.
And the plastic layer 8 seals the bonded substrate and chip, the upper surface of the plastic layer exposes the rewiring interconnection copper column 4 on the surface of the chip, and the bottom surface of the plastic layer exposes the substrate BGA9 to form a FLASH chip packaging unit.
The number of the FLASH chip packaging units is more than 2, an interlayer filling layer 10 is arranged between two adjacent FLASH chip packaging units, and the FLASH chip packaging units are connected with the surface rewiring interconnection copper column 4 of the lower chip through the upper substrate BGA9 in a welding way.
The packaging method of the FLASH chip three-dimensional stacked packaging structure is shown in figures 3-4. The method comprises the following steps:
step S1, manufacturing a multilayer wiring substrate and preparing a FLASH chip wafer;
s2, rewiring is carried out on the surface of the FLASH wafer, and electrodes on the FLASH chip are led out to a design position through the rewiring;
s3, manufacturing copper columns on the middle layer and the bottom layer of the rewiring layer except the top layer;
s4, thinning and scribing the FLASH wafer with the re-wiring and copper column manufactured;
s5, mounting the thinned FLASH chip on a multi-layer substrate;
Step S6, interconnecting the rewiring extraction electrode and the multilayer substrate design electrode through wire bonding;
step S7, performing plastic layer protection on the lead bonding structure, and exposing the top copper column and the back of the substrate;
s8, performing metal BGA ball mounting on the back surface of the substrate to form a FLASH chip packaging unit;
Step S9, according to the setting, taking a top FLASH chip packaging unit as a substrate, and enabling the BGA surface to face upwards, and sequentially welding the top of the setting layer FLASH chip packaging unit to a corresponding position of the bottom BGA of the lower chip in a flip-chip manner;
And S10, filling an interlayer filling layer 10 between the FLASH chip packaging units, and solidifying to obtain the FLASH chip with the three-dimensional stacked packaging structure.
The invention has the technical effects that:
The FLASH chip electrodes are rearranged to be in a double-electrode structure through the wafer rewiring and bump technology, the interconnection of the bottom of the chip is realized through the wire bonding technology, the interconnection of the top of the chip is realized through the flip-chip packaging technology, and therefore the FLASH chip three-dimensional stacking is realized.
The traditional dislocation stacking and wire bonding interconnection mode is changed, and the three-dimensional vertical stacking with low cost is realized through a wafer rewiring process, a flip-chip process and a wire bonding process which are mature in process and low in cost, so that the packaging area is reduced.
Breaks through the limitation of the traditional FLASH chip dislocation stacking packaging structure, and avoids using the wafer-level 3D packaging technology with high cost.
The high-density packaging is realized and the packaging volume is reduced.
The FLASH chip stacking package with high packaging density and low cost is realized, the stacking quantity is larger than that of the traditional staggered lead bonding stacking, the volume of a package finished product is smaller, the stacking packaging cost is lower than that of the wafer-level 3D package, and the technical difficulty of the packaging process is lower.
Can be widely applied to the technical field of high-performance and low-cost microsystem SiP packaging.
Drawings
Fig. 1 is a schematic diagram of a conventional FLASH chip stacking package structure.
Fig. 2 is a schematic diagram of a three-dimensional stacked package structure of a FLASH chip according to the present invention.
Fig. 3 is a schematic diagram of a flow chart of three-dimensional stacked packaging of FLASH chips in the invention.
Fig. 4 is a schematic structural diagram of a three-dimensional stacking and packaging flow of a FLASH chip according to the present invention.
Fig. 5 is a schematic diagram of a single FLASH chip stacked package interlayer connection structure according to the present invention.
Fig. 6 is a schematic diagram of a dual FLASH chip stack package interlayer connection structure according to the present invention.
Fig. 7 is a schematic diagram of a bump array of an intermediate layer of a single FLASH chip stack package according to the present invention.
In the figure, 1 is a FLASH chip (chip for short), 101 is an on-chip electrode, 2 is a chip surface rewiring layer (rewiring layer for short), 3 is a chip surface rewiring passivation layer (passivation layer for short), 4 is a chip surface rewiring interconnection copper pillar (copper pillar bump or copper pillar for short), 401 is a copper pillar metal barrier layer (barrier layer for short), 5 is a multilayer substrate (substrate for short), 501 is a wiring circuit in the substrate, 6 is a chip bonding layer, 7 is a bonding wire (lead wire or bonding wire for short), 8 is a plastic sealing layer, 9 is a substrate BGA (BGA for short), and 10 is an interlayer filling layer (filling layer for short).
Detailed Description
As shown in fig. 2-7, the specific implementation manner of the three-dimensional stacked package structure and the package method of the FLASH chip is as follows:
The FLASH chip is square in shape, the dimensions are 3mm by 3mm to 15mm by 15mm.
The rewiring layer forms interconnected double electrodes, namely a first electrode and a second electrode when the chip electrode is led out. The first electrodes are used for interconnecting corresponding electrodes of the multilayer substrate in a wire bonding mode when being stacked, and the second electrodes are respectively used for interconnecting corresponding electrodes of the multilayer substrate in a flip-chip bonding mode when being stacked. The density of the electrode is 10 pin/mm 2～200 pin/mm2, the material of the rewiring is copper, the electrode is formed on the surface of the rewiring in the modes of electrochemical copper plating, chemical nickel plating, palladium-gold plating and the like, the width of the rewiring line is 2-30 mu m, the distance between the rewiring lines is 2-30 mu m, and the thickness of the rewiring line is 1-20 mu m.
The copper stud bumps are cubic or cylindrical, the width/diameter is 80-600 mu m, the height is higher than the height of the plastic package, the distribution range is the interior of the wire bonding electrode, and the distribution types comprise annular distribution, array distribution and the like.
The metal barrier layer is positioned on the top surface of the copper pillar bump, the barrier layer is a nickel barrier layer, and the thickness of the nickel layer is 1-5 mu m.
The multilayer substrate comprises a ceramic substrate (multilayer cofired ceramic substrate), an organic substrate and the like with multilayer wiring, wherein the inside of the multilayer substrate is wired through copper metal, electrodes on the upper layer are higher than the substrate plane and are distributed in the peripheral edge area of the multilayer substrate, the electrode size is 40-600 μm, and the electrode material is copper, copper-nickel-gold and other structures.
The lead wire (bonding wire) is copper wire, gold wire and the like, and the wire diameter (wire diameter) is 10-30 mu m.
The number of chips attached to each layer of the multilayer substrate is at least 1.
And the ball diameter of the BGA is consistent with the width or diameter of the copper column convex point, and the BGA is made of tin-lead, tin-silver-copper and the like.
Examples of the single chip structure of each layer are as follows:
And rewiring the 12-inch wafer with the FLASH chip manufactured, leading out the electrode on the chip to a design position through the rewiring, and presenting a double-electrode shape (a first electrode and a second electrode). The material of the rewiring layer is copper, the seed layer is deposited through magnetron sputtering, and then the rewiring layer is manufactured through electrochemical deposition, wherein the line width/line distance is 10 mu m/10 mu m, and the thickness is 5 mu m.
The first electrodes are uniformly distributed around the FLASH chip, the size is 65 mu m, the material is copper, and the height of the electrodes is 10 mu m higher than that of the passivation layer;
the second electrodes are uniformly distributed on the inner side of the first electrode of the FLASH chip. And manufacturing a cylindrical copper column on the second electrode, wherein the diameter of the copper column is 90 mu m, the height of the copper column is 100 mu m, and a metallic nickel barrier layer with the thickness of 3 mu m is covered on the copper column through an electrochemical deposition mode.
Thinning and scribing the FLASH wafer with the re-wiring and copper column manufacturing completed to the thickness of 150 mu m, wherein the chip size after scribing is 12mm 4.9mm;
The substrate is an LTCC multilayer co-fired ceramic substrate, front electrodes are distributed around the substrate, back electrodes are distributed under a second electrode of the mounted FLASH chip, the electrode size is 80-20 μm, and the material is copper. The substrate size was 13.5mm by 6.5mm by 0.2mm;
And then the diced chip is attached to the LTCC multilayer cofired ceramic substrate, the first electrode and the front electrode of the multilayer substrate are connected through copper wire lead bonding with the wire diameter of 20 mu m, and an epoxy plastic package (EMC plastic package for short) is carried out to protect the lead bonding structure. The copper column is higher than the whole plastic package height.
BGA ball mounting is carried out on the back electrode of the multilayer substrate, the material is SAC305, and the ball diameter is 120 mu m, so that a stacked chip structure layer is obtained.
And stacking and integrating the stacked chip structure layers according to a set structure in a flip-chip bonding mode, and finally filling the layers to obtain the four-layer single FLASH chip stacked packaging structure.
Examples of the dual chip per layer structure are as follows:
And rewiring the 12-inch wafer with the FLASH chip manufactured, leading out the electrode on the chip to a design position through the rewiring, and presenting a double-electrode shape (a first electrode and a second electrode). The material of the rewiring layer is copper, a seed layer is deposited through magnetron sputtering, the rewiring layer is manufactured through electrochemical deposition, the line width/line distance is 10 mu m/10 mu m, and the thickness is 5 mu m.
The first electrodes are uniformly distributed on the three weeks of the FLASH chip, the size is 65 mu m, the material is copper, and the height of the electrodes is 10 mu m higher than that of the passivation layer;
the second electrodes are uniformly distributed on the inner side of the first electrode of the FLASH chip. And manufacturing a cylindrical copper column on the second electrode, wherein the diameter of the copper column is 90 mu m, the height of the copper column is 100 mu m, and a metallic nickel barrier layer with the thickness of 3 mu m is covered on the copper column through an electrochemical deposition mode.
Thinning and scribing the FLASH wafer with the re-wiring and copper column manufacturing completed to the thickness of 150 mu m, wherein the chip size after scribing is 12mm 4.9mm;
The substrate is an LTCC multilayer co-fired ceramic substrate, the front electrode is distributed around the substrate, and the back electrode is distributed under the second electrode of the mounted FLASH chip. The electrode dimensions were 80 μm by 20 μm. The front electrode material of the substrate is copper-nickel-gold, and the back electrode material is copper. The substrate sizes were 13.5mm by 0.2mm, and the chip spacing was 1mm.
And then the diced chip is attached to the LTCC ceramic multilayer substrate, the first electrode and the front electrode of the multilayer substrate are connected through gold wire bonding with the wire diameter of 18 mu m, EMC plastic packaging is carried out, and the wire bonding structure is protected. The copper column is higher than the whole plastic package height.
BGA ball mounting is carried out on the back electrode of the multilayer substrate, the material is SAC305, and the ball diameter is 120 mu m, so that a stacked chip structure layer is obtained.
And stacking and integrating the stacked chip structure layers according to a set structure in a flip-chip bonding mode, and finally filling the layers to obtain the four-layer double FLASH chip stacked packaging structure.
The invention can realize the FLASH chip stacking package with the electrode density of 10 pin/mm 2～200pin/mm2, the stacking quantity is larger than that of the traditional dislocation wire bonding stacking, the volume of a package finished product is smaller, the stacking package cost is lower than that of the wafer level 3D package, and the technical difficulty of the package process is lower.
Finally, it should be noted that the above-mentioned examples are only examples for the sake of clarity and that the present invention includes, but is not limited to, the above examples, which need not be, nor should they be exhaustive of all embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. All embodiments meeting the requirements of the invention are within the protection scope of the invention.

Claims (13)

1.一种FLASH芯片三维堆叠封装结构，其特征在于：包括FLASH芯片，芯片表面重布线层，芯片表面重布线钝化层，芯片表面重布线互连铜柱，多层基板，芯片粘接层，键合引线，塑封层，基板BGA，层间填充层；1. A FLASH chip three-dimensional stacking packaging structure, characterized by: comprising a FLASH chip, a chip surface redistribution layer, a chip surface redistribution passivation layer, a chip surface redistribution interconnection copper pillar, a multi-layer substrate, a chip bonding layer, a bonding wire, a plastic sealing layer, a substrate BGA, and an interlayer filling layer; 所述多层基板背面为基板BGA，正面为芯片粘接区及引线键合区，基板BGA与芯片粘接区、引线键合区通过基板中布线电路对应连接；The back of the multi-layer substrate is a substrate BGA, and the front is a chip bonding area and a lead bonding area. The substrate BGA is correspondingly connected to the chip bonding area and the lead bonding area through a wiring circuit in the substrate; 所述FLASH芯片通过芯片粘接层与芯片粘接区粘接；The FLASH chip is bonded to the chip bonding area via a chip bonding layer; 所述芯片表面重布线钝化层位于FLASH芯片的表面；The chip surface rewiring passivation layer is located on the surface of the FLASH chip; 所述芯片表面重布线层位于芯片表面重布线钝化层的表面，芯片表面重布线层表面的引线键合区及芯片表面重布线互连铜柱与芯片表面的芯片上电极对应连接；The chip surface redistribution layer is located on the surface of the chip surface redistribution passivation layer, and the wire bonding area on the surface of the chip surface redistribution layer and the chip surface redistribution interconnection copper pillars are correspondingly connected to the chip electrodes on the chip surface; 所述芯片表面重布线层表面的引线键合区与多层基板正面的引线键合区通过键合引线按电路连接规定进行键合连接；The wire bonding area on the surface of the chip surface redistribution layer is bonded to the wire bonding area on the front side of the multi-layer substrate through bonding wires according to circuit connection regulations; 所述塑封层密封键合后的基板及芯片，上表面露出芯片表面重布线互连铜柱，底面露出基板BGA，形成FLASH芯片封装单元；The plastic sealing layer seals the bonded substrate and chip, with the chip surface rewiring interconnection copper pillars exposed on the upper surface and the substrate BGA exposed on the bottom surface, forming a FLASH chip packaging unit; 所述FLASH芯片封装单元为2个以上，相邻两层FLASH芯片封装单元之间为层间填充层，通过上层基板BGA与下层芯片表面重布线互连铜柱进行焊接连接。There are more than two FLASH chip packaging units, and an interlayer filling layer is provided between two adjacent layers of FLASH chip packaging units, which are welded and connected with the upper layer substrate BGA and the lower layer chip surface rewiring interconnection copper pillars. 2.如权利要求1所述的一种FLASH芯片三维堆叠封装结构，其特征在于：所述FLASH芯片为方形，尺寸为3mm*3mm～15mm*15mm。2. A FLASH chip three-dimensional stacking packaging structure as described in claim 1, characterized in that: the FLASH chip is square and has a size of 3mm*3mm to 15mm*15mm. 3.如权利要求1所述的一种FLASH芯片三维堆叠封装结构，其特征在于：所述重布线层将芯片电极引出时形成互连的第一电极和第二电极，重布线层的电极密度为10 pin/mm2～200 pin/mm2，重布线线宽为2μm～30μm，重布线线距为2μm～30μm，重布线厚度为1μm～20μm。3. A FLASH chip three-dimensional stacking packaging structure as claimed in claim 1, characterized in that: the redistribution layer forms interconnected first electrodes and second electrodes when leading out chip electrodes, the electrode density of the redistribution layer is 10 pin/ mm2 ~200 pin/ mm2 , the redistribution line width is 2μm~30μm, the redistribution line spacing is 2μm~30μm, and the redistribution thickness is 1μm~20μm. 4.如权利要求1所述的一种FLASH芯片三维堆叠封装结构，其特征在于：所述重布线层的线材为铜，重布线层的电极是在重布线表面通过电化学镀铜或化学镀镍钯金的方式形成。4. A FLASH chip three-dimensional stacking packaging structure as described in claim 1, characterized in that: the wire material of the redistribution layer is copper, and the electrodes of the redistribution layer are formed on the redistribution surface by electrochemical copper plating or chemical nickel-palladium-gold plating. 5.如权利要求1所述的一种FLASH芯片三维堆叠封装结构，其特征在于：所述铜柱位于引线键合电极的内侧，分布类型为环形分布或阵列分布；所述铜柱为立方体型或圆柱型，宽度/直径为80μm～600μm，高度高于塑封体厚度。5. A FLASH chip three-dimensional stacking packaging structure as described in claim 1, characterized in that: the copper pillar is located on the inner side of the wire bonding electrode, and the distribution type is a ring distribution or an array distribution; the copper pillar is a cube or a cylinder, with a width/diameter of 80μm to 600μm, and a height higher than the thickness of the plastic package. 6.如权利要求1所述的一种FLASH芯片三维堆叠封装结构，其特征在于：所述铜柱顶端表面为金属阻挡层。6 . The FLASH chip three-dimensional stacking packaging structure as claimed in claim 1 , wherein the top surface of the copper column is a metal barrier layer. 7.如权利要求6所述的一种FLASH芯片三维堆叠封装结构，其特征在于：所述阻挡层为镍阻挡层，镍层厚度为1μm～5μm。7 . The FLASH chip three-dimensional stacking packaging structure according to claim 6 , wherein the barrier layer is a nickel barrier layer, and the thickness of the nickel layer is 1 μm to 5 μm. 8.如权利要求1所述的一种FLASH芯片三维堆叠封装结构，其特征在于：所述多层基板为多层共烧陶瓷基板或多层有机基板，多层基板内部通过铜金属进行布线，上层的电极高于基板平面，并分布于多层基板四周边缘区域，电极尺寸为40μm *40μm～600μm *600μm，电极材质为铜或铜-镍-金。8. A FLASH chip three-dimensional stacking packaging structure as described in claim 1, characterized in that: the multi-layer substrate is a multi-layer co-fired ceramic substrate or a multi-layer organic substrate, the multi-layer substrate is wired internally by copper metal, the upper electrode is higher than the substrate plane, and is distributed in the edge area around the multi-layer substrate, the electrode size is 40μm *40μm~600μm *600μm, and the electrode material is copper or copper-nickel-gold. 9.如权利要求1所述的一种FLASH芯片三维堆叠封装结构，其特征在于：所述引线为铜丝、或金丝，线径为10μm ～30μm。9 . The FLASH chip three-dimensional stacking packaging structure according to claim 1 , wherein the lead wire is a copper wire or a gold wire, and the wire diameter is 10 μm to 30 μm. 10.如权利要求1所述的一种FLASH芯片三维堆叠封装结构，其特征在于：每层多层基板上贴装的芯片数量至少为1颗。10. The FLASH chip three-dimensional stacking packaging structure as claimed in claim 1, characterized in that the number of chips mounted on each layer of the multi-layer substrate is at least one. 11.如权利要求1所述的一种FLASH芯片三维堆叠封装结构，其特征在于：所述BGA的球径与所述铜柱的宽度或直径一致，所述BGA的材质为锡-铅合金或锡-银-铜合金。11. A FLASH chip three-dimensional stacking packaging structure as described in claim 1, characterized in that: the ball diameter of the BGA is consistent with the width or diameter of the copper column, and the material of the BGA is tin-lead alloy or tin-silver-copper alloy. 12.如权利要求1所述的一种FLASH芯片三维堆叠封装结构的封装方法，其特征在于，包括以下步骤：12. The packaging method of a FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that it comprises the following steps: 步骤S1：多层布线基板制作、FLASH芯片晶圆准备；Step S1: multi-layer wiring substrate manufacturing and FLASH chip wafer preparation; 步骤S2：在FLASH晶圆表面进行重布线，将FLASH芯片上的电极通过重布线引出至设计位置；Step S2: rewiring is performed on the surface of the FLASH wafer, and the electrodes on the FLASH chip are led out to the designed positions through rewiring; 步骤S3：在重布线层上进行铜柱制作；Step S3: fabricating copper pillars on the redistribution layer; 步骤S4：将完成重布线及铜柱制作的FLASH晶圆进行减薄、划片；Step S4: Thinning and dicing the FLASH wafer after rewiring and copper pillar fabrication; 步骤S5：将减薄后的FLASH芯片贴装至多层基板上；Step S5: mounting the thinned FLASH chip onto the multi-layer substrate; 步骤S6：将重布线引出电极与多层基板设计电极通过引线键合互连；Step S6: interconnecting the rewiring lead-out electrodes and the multi-layer substrate design electrodes through wire bonding; 步骤S7：对引线键合结构进行塑封层保护，露出顶部铜柱及基板背面；Step S7: Protect the wire bonding structure with a plastic layer to expose the top copper column and the back of the substrate; 步骤S8：对基板背面进行金属BGA植球，形成FLASH芯片封装单元；Step S8: performing metal BGA ball planting on the back of the substrate to form a FLASH chip packaging unit; 步骤S9：按设定，以顶层FLASH芯片封装单元为基底，BGA面朝上，依次将设定层FLASH芯片封装单元顶部通过倒装方式焊接到下层芯片的底部BGA对应位置；Step S9: according to the setting, with the top FLASH chip packaging unit as the base and the BGA facing upward, the top of the set layer FLASH chip packaging unit is sequentially soldered to the corresponding position of the bottom BGA of the lower layer chip by flip-chip method; 步骤S10：在FLASH芯片封装单元之间填充层间填充层10，并进行固化，得到三维堆叠封装结构的FLASH芯片。Step S10: filling an interlayer filling layer 10 between the FLASH chip packaging units and curing the interlayer filling layer 10 to obtain a FLASH chip with a three-dimensional stacked packaging structure. 13.如权利要求1所述的一种FLASH芯片三维堆叠封装结构的封装方法，其特征在于：所述重布线层先通过磁控溅射沉积种子层，再通过电化学沉积进行制作，线宽/线距为10μm/10μm，厚度为5μm。13. The packaging method of a FLASH chip three-dimensional stacking packaging structure as claimed in claim 1, characterized in that: the redistribution layer is first deposited by magnetron sputtering as a seed layer, and then is manufactured by electrochemical deposition, with a line width/line spacing of 10 μm/10 μm and a thickness of 5 μm.
CN202411319106.8A 2024-09-21 2024-09-21 A FLASH chip three-dimensional stacking packaging structure and packaging method Pending CN119381381A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030141582A1 (en) * 2002-01-25 2003-07-31 Yang Chaur-Chin Stack type flip-chip package
KR20040023188A (en) * 2002-09-11 2004-03-18 주식회사 하이닉스반도체 Stack package and it's favrication method of center pad chips
KR20070109322A (en) * 2006-05-10 2007-11-15 주식회사 네패스 Stacked Multichip Package and Manufacturing Method Thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030141582A1 (en) * 2002-01-25 2003-07-31 Yang Chaur-Chin Stack type flip-chip package
KR20040023188A (en) * 2002-09-11 2004-03-18 주식회사 하이닉스반도체 Stack package and it's favrication method of center pad chips
KR20070109322A (en) * 2006-05-10 2007-11-15 주식회사 네패스 Stacked Multichip Package and Manufacturing Method Thereof

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